JPH0690610B2 - Character pattern processing method - Google Patents

Description

TECHNICAL FIELD The present invention relates to a character pattern processing method for shifting an output position of a character in a character output unit.

2. Description of the Related Art An image forming information processing unit (printing information processing unit) of a conventional dot beam printer type image forming apparatus such as a laser beam printer or an ink jet printer is generally as shown in FIG. In FIG. 1, character information 121 composed of a character code sent from an input side (not shown) such as a host computer is stored in the page memory 102 by the input control unit 101. The character information stored in the page memory 102 is then sequentially read by the main control unit 103 from the top of the page. The main control unit 103 is
The character code read from the page memory 102 is converted to the dot pattern data 122 of the character by referring to the dot pattern data stored in the character pattern generator 104. The converted dot pattern data 122 of the character is further selected by the main control unit 103 as the dot pattern data 123 for one scanning line according to the scanning of the printing unit (or display unit) (not shown), and the dot pattern shift is performed. Sent to device 105. This dot pattern shift device 105 changes a dot pattern of a character to a desired dot pattern in order to change the position of the character in one line in accordance with the bit shift information for adding or deleting the space between characters in one line. Shift by a few dots.

As described above, the dot pattern data 123 for one scan of the above character is shifted by the desired dot number by the dot pattern shift device 105 and then written in the scan buffer 106. The scan pattern buffer 106 is provided with dot pattern data for one scanning line of the row by repeating the above operation.
124 is written. The dot pattern data written in the scan buffer 106 is further read by the read control unit 107.
Then, the data is read at a print timing of a print unit (not shown), further converted into serial data by the parallel-serial converter 108, and then sent to the print unit (not shown) to be printed on a recording medium.

FIG. 2 shows an example of the structure of the scanning buffer 106 shown in FIG. 1, and 201 and 202 in the drawing are addresses of the memories constituting the scanning buffer. Therefore, for example, if the address 201 of Sukiyanbata 106 is specified, the address 201
The 16-bit data specified by is simultaneously accessed.

Now, assuming that the dot pattern data 123 sent from the main control unit 103 is data as shown in FIG. 3 (A), it is assumed that it is the arbitrary position 203 of the skimmer buffer 106 in FIG.
If you write to Sukiyanbathua 10 as described above.
Since the address arrangement of the memory constituting 6 is like 201, 201 divided in predetermined bit units, in order to write in an arbitrary position 203, a pair of data shifted as shown in FIGS. 3 (B) and (C). Address 2 corresponding to 124
Must be written on 01 and 202. Therefore, the dot pattern data 1
Although it is necessary to shift 23 as shown in FIGS. 3B and 3C, the conventional dot pattern shift device 105 is generally constructed as shown in FIG.

In FIG. 4, the dot pattern data 123 for one character scan is first loaded into the shift register 401. On the other hand, the register 403 is previously loaded with bit shift information indicating how many bit shifts are to be performed, and the shift clock 421 is sent from the shift control circuit 402 to the shift register 401 in accordance with the bit shift information, and a predetermined bit is sent according to the shift clock 421. The dot pattern data 124, which has been shifted by a few numbers, is sent to the scanning buffer 106.

However, since such a conventional dot pattern shifter can shift only one bit at a time, the shift clock is the best for dot pattern data consisting of 16 bits as shown in FIG. 3 (A). Since it has to be sent 15 times, it takes a long time to perform the shift work, and the number of shifts must be changed by the control unit, so that there is a drawback that the load on the control side increases.

It is an object of the present invention to provide a character pattern processing method capable of performing a character pattern shift process at high speed with a simple structure without requiring a complicated circuit structure.

In order to achieve such an object, the present invention controls the output position of a character in the character output means in dot units, and in the character pattern generation means (in the embodiment described later, the character pattern generation unit 104 (FIG. 1)). Signal output means for outputting a signal corresponding to a shift amount for shifting a fixed-length dot pattern forming a part of one character pattern generated from Similarly, a register 505 (corresponding to FIG. 5)) and the dot pattern of the constant length are divided and stored, and a plurality of dot patterns that are shifted corresponding to the signal from the signal output means are stored. Dot pattern shift means having a plurality of storage means (also corresponding to the ROMs 501 to 504 (FIGS. 5 and 7)) (also the dot pattern shift circuit 105) A character pattern for shifting the character output position according to the space between characters by shifting the character output position (corresponding to FIGS. 1 and 5) and writing to the image buffer (also corresponding to the scan buffer 106 (FIG. 1)). A first step of outputting a dot pattern of a constant length from the character pattern generating means to the dot pattern shifting means, dividing the dot pattern of the constant length and inputting the divided dot patterns into the plurality of storage means. 2 steps, 3rd step of inputting the signal output from said signal output means to said plurality of storage means, said dot pattern divided and input in said storage means is shifted corresponding to the signal from said signal output means The fourth step of changing and outputting the dot patterns that have been changed, combining the dot patterns output from the plurality of storage means. And a step of writing the shifted dot pattern of a constant length obtained in the image buffer into the image buffer.

Examples Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 5 shows an example of the configuration of the dot pattern shift device of the present invention, and the other parts are the same as the conventional example of FIG. In FIG. 5, the arrow indicates the flow of data, and the number shown with an oblique line in the middle of the arrow indicates the number of constituent bits of the data. Further, 501 to 504 are read-only memories (hereinafter,
505 is a 16-bit register that stores bit shift information generated according to the shift mode, and 506 and 507 are OR gates that OR the outputs of the ROM.

Next, the operation of the circuit shown in FIG. 5 when the data shown in FIG. 3A is supplied as the dot pattern data 123 for one scan of a character will be described.

First, in the dot pattern data 123, the upper 8 bits “b ₁₆ b ₁₅ b ₁₄ b ₁₃ b ₁₂ b ₁₁ b ₁₀ b ₉ ” are the upper data 521.
Is supplied to the ROM 502 and the ROM 504 and input as the ROM address. Next, the lower 8 bits of the dot pattern data 123, "b ₈ b ₇ b ₆ b ₅ b ₄ b ₃ b ₂ b ₁ ", are the lower data 5
22 is supplied to the ROM 501 and the ROM 503 and is input as the ROM address. On the other hand, the register 505 is shown in FIG. 6 which is determined by how many bit shifts are made to the left or right.
The 16-bit data is preloaded by the main control unit 103 (see FIG. 1), and the 16-bit data is supplied to the corresponding ROMs 501-504 as 4-bit output data 523-526, respectively. It is input as an RM address.

7A and 7B show the dot pattern data 123.
As "b ₁₆ b ₁₅ b ₁₄ b ₁₃ b ₁₂ b ₁₁ b ₁₀ b ₉ b ₈ b ₇ b ₆ b ₅ b ₄ b ₃ b ₂ b ₁ ", the ROM 501 to the input data 523 to 526 is
The respective outputs of 504 are shown.

Now, as shown in FIG. 2, when the dot pattern data 123 is written at the position indicated by 203 with respect to the addresses 201 and 202 of the scan buffer 106 (see FIG. 1), first, for the address 201, As shown in FIG. 3 (B), it is necessary to obtain data obtained by shifting the data of FIG. 3 (A) to the right by 11 bits. Therefore, the register 505 is instructed to shift 11 bits to the right by the arrow 6 in FIG.
The data “0000000000000101” in the line indicated by 01 is loaded in advance. Yotsute, output from ROM501~ROM504, as shown in FIG. 7, ROM501～503 becomes "00000000" ROM 504 is _{"000b 16 b 15 b 14 b} 13 b 12". The outputs of the ROMs 501 and 502 are supplied to the OR gate 506, the outputs of the ROMs 503 and 504 are supplied to the OR gate 507, and the logical sum is obtained.
Output 124 of the combined lower bits output of the upper bit output and the OR gate 507 is _{"00000000000b 16 b 15 b 14 b} 13 b 12" , and the data of 16 bits that need to obtain a time.

Similarly, for the address 202 of the scan buffer 106, data shown in FIG. 3 (C) is required to be shifted to the left by 5 bits as shown in FIG. 3 (C). Therefore, the data "010111011101000" in the line indicated by arrow 602 in FIG.
0 "is loaded.

At this time, as shown in FIGS. 7 (A) and 7 (B), the ROM5
The output of 01 is "000b ₈ b ₇ b ₆ b ₅ b ₄ " and the output of ROM502 is "b ₁₁ b ₁₀
b ₉ 00000 ", the output of ROM 503 is" b ₃ b ₂ b ₁ 00000 ", and the output of ROM 504 is" 00000000 ".
, "B ₁₁ b ₁₀ b ₉ b ₈ b ₇ b ₆ b ₅ b ₄ b ₃ b ₂ b ₁ 00000" can obtain the required 16-bit data at one time.

As described above, according to the present example, the desired shifted data can be obtained at one time only by setting the value corresponding to the shift mode in the register, so that high-speed shift processing can be performed. Further, in this example, since no complicated control circuit is required for shifting the data, there is an effect that the burden on the control side is reduced.

In this example, the 16-bit dot pattern data is divided into two, that is, an upper bit and a lower bit. However, even if this is divided into four or eight,
It goes without saying that the object of the present invention can be achieved.

Effect As described above, according to the present invention, the shift process of the character pattern can be performed at high speed with a simple configuration without requiring a complicated circuit configuration.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of the configuration of a print information processing unit of a conventional image forming apparatus such as a laser beam printer, and FIG. 2 is an explanatory diagram showing an example of the configuration of the scanning buffer 106 shown in FIG. FIG. 3 (A) is an explanatory diagram showing an example of the dot pattern data 123 before the shift of FIG. 1, and FIGS. 3 (B) and 3 (C) are examples of the dot pattern data 124 after the shift of FIG. FIG. 4 is a block diagram showing an example of the configuration of the dot pattern shifting device 105 of FIG. 1, FIG. 5 is a block diagram showing an example of the configuration of the dot pattern shifting device of the present invention, and FIG. 5 is a diagram showing an example of the contents of data (bit shift information) to be loaded into the register 505 of FIG. 5 according to the shift mode, and FIGS. 7 (A) and 7 (B) are stored in the ROMs 501 to 504 of FIG. It is a figure which shows an example of the data content which was. 101 ... Input control unit, 102 ... Page memory, 103 ... Main control unit, 104 ... Character pattern generation unit, 105 ... Dot pattern shifter, 106 ... Skiyan buffer, 107 ... Reading control unit, 108 ... ... Parallel-to-serial converter, 401 ... shift register, 402 ... shift control circuit, 403 ... register, 501-504 ... read-only memory (ROM), 505 ... register, 506, 507 ... OR gate (OR gate).

Front Page Continuation (56) References JP-A-56-52441 (JP, A) JP-A-51-1041 (JP, A) JP-A-51-109743 (JP, A) JP-A-54-3441 (JP , A) JP 55-102046 (JP, A) JP 58-51340 (JP, A) JP 57-29086 (JP, A) JP 58-68094 (JP, A)

Claims (1)

[Claims] 1. A device for controlling a character output position in a character output unit in dot units, wherein a dot pattern of a constant length forming a part of one character pattern generated from a character pattern generating unit is set to the constant length. Signal output means for outputting a signal corresponding to a shift amount to be shifted with respect to the dot pattern, and the dot pattern of the fixed length are divided and stored, and are shifted corresponding to the signal from the signal output means. A character pattern processing method for shifting by a dot pattern shift means having a plurality of storage means for storing a plurality of dot patterns and writing in an image buffer, and shifting a character output position according to an inter-character space, A first pattern for outputting a fixed-length dot pattern from the character pattern generating means to the dot pattern shifting means A second step of dividing the dot pattern of a certain length into the plurality of storage means and inputting the signal output from the signal output means into the plurality of storage means; A fourth step of changing the dot pattern input by dividing into a shifted dot pattern corresponding to the signal from the signal output means and outputting the dot pattern, obtained by synthesizing dot patterns output from the plurality of storage means And a fifth step of writing the shifted dot pattern having a fixed length in the image buffer.