JP2502530B2 - Printer - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a printing device for printing data sent from an external device such as a host computer or a word processor on a sheet.

[Prior art]

Conventionally, a character code sent from an external device such as a computer is formed into a dot pattern, and for example, written in a frame memory having a memory capacity corresponding to one page of paper,
The data written in this frame memory is read sequentially,
Printing devices for printing have been put into practical use. In such a printing device, when performing a halftone process or a reverse process on a print character, once the dot pattern data for one page is written in the frame memory, the halftone process or the like of the area to be performed by the software process is performed. A method is used in which the data is read out, the halftone processing is performed, and then the data is written back to the original address.

[Problems of conventional technology]

However, when performing the above-mentioned halftone processing or attribute processing such as inversion processing, in either case, the character data is dot-patterned and written in the frame memory, then the data is read, and the data is shaded or inverted and the data is read again. Must be written to frame memory. Therefore,
Since the data is written twice, the data processing time becomes longer accordingly.

In addition, the characters in different areas of the frame memory are shaded,
When performing the inversion and the inversion, it is necessary to access the same data four times, for example, the data writing process, the halftone process, the data reading process, and the inversion data writing process.

On the other hand, when the shading and inversion processing is performed on the overlapping areas of the frame memory, the shading and inversion range management becomes complicated.

Further, when the range designation of the reversal processing overlaps, the reversed character is reversed again, so-called double reversal needs to be avoided, so that the attribute and range management become extremely complicated. Also, when different shaded types are specified for the same range, special processing is required.

Therefore, the conventional printing apparatus has a problem that the processing speed is lowered due to a large number of memory accesses and complicated processing.

[Object of the Invention]

In view of the above-mentioned conventional drawbacks, the present invention provides a printing apparatus that can accelerate the data processing speed of attributes such as halftone processing or inversion processing, and can easily manage the processing range of attribute data processing. The purpose is to

[Main points of the invention]

In order to achieve the above object, the present invention generates pattern data corresponding to print information sent from an external device, expands and stores the pattern data in a frame memory, and outputs the pattern data to a print unit to perform print processing. In the apparatus, an attribute memory that stores a plurality of types of attribute processing information incidental to the print information in a designated area corresponding to a storage area of the frame memory, and the frame memory and the attribute memory are designated by a common address. Address means, read means for reading the pattern data and attribute data stored in the frame memory and the attribute memory designated by the address means, and pattern data read from the frame memory for reading from the attribute memory And an attribute processing unit that superimposes a plurality of types of attribute processing,
It is characterized by having.

Example of Invention

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a schematic block diagram of the printing apparatus used in the present invention. The printing apparatus used in this embodiment is composed of an interface board section 1 and a printing section 2, and the interface board section 1 is connected to an external host computer 3 by a host I / F section 4 provided inside. Character code and halftone output from the host computer 3,
Control data such as inversion is input to the host I / F unit 4 in the interface board unit 1. The host I / F unit 4 performs processing such as temporarily holding the input character code and control data and adjusts the processing speed and the like in the host computer 3 and the interface board unit 1.

Controller 5 composed of CPU (Central Processing Unit)
Outputs the above-mentioned character code and control data input from the host I / F unit 4 to the character processing unit 6. The character processing unit 6 outputs a character code to the character pattern generation unit 7 and reads the corresponding dot pattern data from the character pattern generation unit 7. The character processing unit 6 further outputs the shaded and inverted processing data included in the control data to the frame memory unit 8 together with the corresponding dot pattern data, as described later in detail. The frame memory unit 8 stores dot pattern data and data such as halftone and inversion according to address data input from the controller 5.

In the print interface (I / F) unit 9, data such as character codes in the frame memory unit 8 is read according to the control data of the controller 5, combined with halftone data, etc. as described later, and made into print data and then printed. Output to section 2.

FIG. 1 shows the frame memory unit 8 and the print I / F unit 9 described above.
3 is a circuit diagram showing a specific circuit block of FIG. In the figure, a frame RAM (FRAM) 10 and an attribute memory 11 are circuits corresponding to the frame memory section 8 of FIG.
The shaded circuit 12 and the inversion circuit 13 are circuits corresponding to the print I / F unit 9.

The dot pattern data from the character processing unit 6 is input to the bus transceiver 14 via the data bus, and
Input to FRAM 10 via OR array 15.

This dot pattern data is stored in the area designated by the address data output from the controller 5 via the frame memory address bus for each word described later.

The FRAM 10 stores all characters, graphs, etc. to be printed on one page in dot units. For example, when printing on B4 size paper at a recording density of 240 dots / inch, as shown in FIG. 3, 2304 x 3360 dots, that is, about 1M
Requires bytes of storage. In addition, this FRAM10 X,
In the two-dimensional representation of Y, 144 words, that is, 2304 dots are arranged with 16 dots in the X direction as one word, and 3360 dots are arranged in the other Y direction.

On the other hand, when dot pattern data is input via the above-mentioned data bus, an attribute selection signal for selecting the attribute of 1-word data to be input at the same time is output to the attribute data generation circuit 16. The attribute data generation circuit 16 has four types of attribute data, which are shaded a to c and inverted, and the shaded a to c are different in the density of the halftone when the halftone processing is performed on the paper.

The attribute data (4 bits) selectively generated by the attribute data generation circuit 16 is transferred to the attribute memory 11 via the OR array 17.
Output to The attribute data input to the attribute memory 11 is written in the area designated by the address data from the controller 5 input via the frame memory address bus.

FIG. 4 shows the structure of a memory area for one word in the FRAM 10 and the attribute memory 11. For example, the address "00
The upper 16 bits (0 to 15) of 00 _H "are print data to be written to the FRAM10, and the lower 4 bits (16 to 19) are attribute data to be written in the attribute memory 11. For the attribute data, for example, 16 bits are “shaded a”,
17 bits for "shaded b", 18 bits for "shaded c", 19
The bit is defined as “invert”.

The actual shading or inversion processing is performed by the shading circuit 12 or the like when the data is transferred to the printing unit 2.

When outputting the dot pattern of FRAM10 to the printing unit 2, one word of FRAM10 is addressed via the frame memory address bus, and at the same time, from the attribute memory 11,
Attribute data corresponding to the same word is read.

For example, if the address "0001 _H " in FIG. 4 is designated, the print data "0111000111000111" is read from the FRAM 10 and the attribute data "1000" is read from the attribute memory 11. The read attribute data is output to the halftone dot pattern generation circuit 18. The hatched pattern generation circuit 18 uses, for example, the above-mentioned hatched a (“100
In case of 0 "), a predetermined halftone pattern is generated as shown in FIG.

The shaded pattern shown in the figure has an area ratio of 25%,
The address that specifies the address in the Y direction of FRAM10 included in the input address data is analyzed, and if it is an even bit, 2 bits of 01 are repeatedly output, and if it is an odd bit, it is output.
2 bits of 00 are repeatedly output. As a result, the shading process has an area ratio of 25% as a whole. In the example of FIG. 5, the X address designating the X direction of the FRAM 10 has nothing to do with the shaded data.

Also, although not shown in the case of other shaded designations b and c,
Output the corresponding shaded pattern.

The above-mentioned shaded pattern is output to the shaded circuit 12,
It is combined with the output data from FRAM10. The combined data is output to the inversion circuit 13, and when the inversion data is output from the attribute memory 11, the inversion circuit 13 outputs “0” and “1” of the input data by exchanging them to perform black-and-white inversion. .

If there is no inversion designation, the input data is directly output to the printing unit 2. On the other hand, in FRAM10 and attribute memory 11,
For example, signals such as RAS (row address strobe) and CAS (column address strobe) are input from the controller 5 described above. Also, the memory clear signal is the OR array.
It is output to 15,17. For example, when the memory clear signal is input, the OR arrays 15,17 output “0”, and this is output to FRAM1.
By writing 0 to the attribute memory 11, the data in both memories 10 and 11 are cleared.

In the printer with the above configuration, the FRAM1
The operation of writing data to the attribute memory 11 and the reading of data from the printing unit 2 will be described with reference to FIG.

Now, the hatched areas A and B in the substantially central portion of the FRAM 10 are data processing areas designated by the host computer 3, and it is assumed that halftone processing is performed in this area A and inversion processing is performed in the area B.

Further, in the figure, (X _A , Y _B ) is the start point address of the designated area A, (X _{A + n} , Y _{B + m} ) is the end point address,
(X _C , Y _D ) is the start address of the specified area B, (X _{C + k} ,
Y _{D + l} ) is the end point address. However, X is a word unit and Y is a dot unit.

First, the corresponding addresses of the FRAM 10 and the attribute memory 11 are designated by the address data, and the dot pattern of the print data is sequentially written from the address "0000 _H " of the FRAM 10 via the data bus as described above. At this time, at the same time, the attribute data selected by the attribute selection signal is also input to the designated address area of the attribute memory 11. However, the address "0000 _H" shaded as shown in Figure 3, since there is no process of inversion, etc., the attribute memory 11 "0000" is written. As described above, the addresses are sequentially designated as “0000 _H ” → “0002 _H ” → ... And the data is sequentially written in the FRAM 10. During this period, all "0" s are written in the corresponding address area of the attribute memory 11.

Next, when the address data reaches the position (address) of (X _A , Y _B ) in FIG. 3, the data is written in the FRAM 10 and at the same time the attribute data is written in the attribute memory 11. At this time, since the area A is designated by the shaded area a, "1000" is output from the attribute data generation circuit 16 and written in the corresponding word bits (16 to 19). After that, "1000" is sequentially written in the attribute memory 11 in the area corresponding to the area A.
Then, the writing of "1000" to the attribute memory 11 is performed up to the position (X _{A + n} , Y _{B + m} ). However, since writing is sequentially performed in word units in the X direction, "0000" data is written in the attribute memory 11 in the A'area not included in the A area during this period.

Furthermore, when writing the data after the above-mentioned position (X _{A + n} , Y _{B + m} ), the data is written to the FRAM10, and to the attribute memory 11, "000
The data of "0" is the writing process.

Next, the B area is written in the attribute memory 11. This behavior is
According to the start point address (X _C , Y _D ) and end point address (X _{C + k} , Y _{D + l} ) in the X direction latched by the host computer 3 in the area designation circuit (not shown) in the controller 5 to the attribute memory 11. , Addressed data
The data is read to the OR array 17, and the read data and the data output from the attribute data generation circuit 16 are newly written in the B area.

In this case, since the OR array 17 performs an OR addition and the data is written again to the attribute memory 11, for example, in a portion where the area A and the area B overlap, the data "1000" of the shaded a and the inverted "0".
The data of "001" is added to become "1001". Also, for example, even when the A region and the B region are inversion processing, since OR addition is performed, a problem such as double inversion can be avoided.
That is, the data of "1" to be processed for the inversion of the same attribute and the halftone a is rewritten as it is to the attribute memory 11 as the data of "1".

At this time, the address of the FRAM10 is also designated, but the data of the FRAM10 is output to the OR array 15 when the B area is written in the attribute memory. At this time, since the data in the FRAM 10 is not changed, the write data to the FRAM 10 may be output from the controller 5 to the OR array 15 as 0.

As described above, the data written in the FRAM 10 and the attribute memory 11 is output to the hatching circuit 12 by the read signal from the controller 5 as described above, and the attribute data is output to the hatching pattern generating circuit 18 and the inversion circuit. It is output to the circuit 13. Then, the hatching circuit 12 synthesizes the pattern (FIG. 5) of the halftone a output from the halftone pattern generating circuit 18 into the pattern data to create the area A, and the inversion circuit 13 performs the inversion processing of the area B. And output to the printing unit 2.

In the above description, the area A is shaded a and the area B is inverted. However, even if the areas A and B have the same attribute, for example, the shaded a is OR-added to the attribute memory 11 by the OR array 17. Since the new data is rewritten, the overlapping area is not affected by the data to be written later.

In this example, the case where a 4-bit attribute memory is added to one word of the FRAM10 has been described.
By expanding the number of bits of, it is possible to easily increase the types of attribute processing such as shading. Similarly,
It is also possible to divide one word into upper bits and lower bits and give attributes to each.

〔The invention's effect〕

As described above in detail, according to the present invention, since attribute processing such as shading and inversion processing can be executed by the attribute data set in the frame memory in advance, the processing is simple and speeded up.

The attribute memory is not managed by the CPU, so it does not affect the system memory configuration.

[Brief description of drawings]

FIG. 1 is a circuit block diagram of an embodiment of the present invention, FIG. 2 is a schematic circuit block diagram of a printing apparatus according to the present invention, and FIG. 3 is an explanatory diagram schematically showing a frame memory, FIG. 5 is an explanatory view schematically showing a part of the designated area of the frame memory in detail, and FIG. 5 is an explanatory view showing an example of a mesh pattern. 1 ... Interface board section, 2 ... Printing section, 3 ... Host computer, 5 ... Controller, 6 ... Character processing section,
7 ... Character pattern generating section, 8 ... Frame memory section, 9 ...
Print I / F section, 10 ... FRAM, 11 ... Attribute memory, 12 ... Shading circuit, 13 ... Inversion circuit, 15, 17 ... OR array.

 ─────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-60-15531 (JP, A) JP-A-62-151350 (JP, A) JP-A-61-258768 (JP, A) JP-A-63- 118927 (JP, A) JP 53-54924 (JP, A) JP 61-158471 (JP, A) JP 60-201960 (JP, A) JP 63-290761 (JP, A)

Claims (1)

(57) [Claims] 1. A printing apparatus for generating corresponding pattern data from print information sent from an external device, expanding and storing the pattern data in a frame memory, outputting the pattern data to a printing unit, and performing a printing process. An attribute memory for storing a plurality of types of attribute processing information attached to the specified area in a designated area corresponding to the storage area of the frame memory; address means for designating an area for the frame memory and the attribute memory with a common address; Reading means for reading the pattern data and the attribute data stored in the frame memory and the attribute memory designated by the means, and a plurality of types of attribute processing for reading the pattern data read from the frame memory from the attribute memory And a property processing unit that superimposes and applies.