JPH0689945A - Method of packaging semiconductor device - Google Patents
Method of packaging semiconductor deviceInfo
- Publication number
- JPH0689945A JPH0689945A JP4239864A JP23986492A JPH0689945A JP H0689945 A JPH0689945 A JP H0689945A JP 4239864 A JP4239864 A JP 4239864A JP 23986492 A JP23986492 A JP 23986492A JP H0689945 A JPH0689945 A JP H0689945A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- semiconductor device
- lid
- bonding
- adhesive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、気密封止タイプのパッ
ケージを対象とした半導体装置のパッケージング方法に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device packaging method for a hermetically sealed type package.
【０００２】[0002]
【従来の技術】回路基板に搭載した半導体素子を外部雰
囲気からしゃ断するために、半導体素子，および半導体
素子と基板の導体パターンとの間を接続するボンディン
グワイヤを包囲して基板上に蓋体を被着して気密封止し
たハーメチックパッケージが周知である。また、パッケ
ージのシール方法としてろう付け，ガラスシール法のほ
かに、熱硬化性樹脂接着剤によるシール方法が知られて
いる。2. Description of the Related Art In order to shield a semiconductor element mounted on a circuit board from the external atmosphere, a lid is provided on the board by surrounding the semiconductor element and a bonding wire connecting the semiconductor element and a conductor pattern of the board. Hermetically packaged, hermetically sealed packages are well known. In addition to brazing and glass sealing methods, a sealing method using a thermosetting resin adhesive is known as a package sealing method.
【０００３】[0003]
【発明が解決しようとする課題】ところで、前記した従
来のシール方法においては、いずれの方法でも回路基板
に蓋体を接着する際に高温加熱処理が必要となるため、
例えば銅張絶縁基板などでは高温加熱により銅箔接着強
度が劣化する。また、シール作業を大気の雰囲気中で行
うと半導体素子の周辺に配線したボンディングワイヤの
接合点に対しても金属酸化の生じることが避けられな
い。特に、コスト面からボンディングワイヤに銀，錫，
およびそれらの合金を用いたものでは、金属酸化の進行
によりワイヤ接合点の抵抗増加，最悪の場合にはワイヤ
の断線を引き起こすおそれがある。そのために気密封止
を窒素ガスなど不活性ガスの雰囲気中で行う方法も実施
されているが、この方法は工程管理が厄介である。By the way, in any of the above-mentioned conventional sealing methods, high temperature heat treatment is required when the lid is bonded to the circuit board, whichever method is used.
For example, in a copper-clad insulating substrate or the like, high-temperature heating deteriorates the copper foil adhesive strength. Further, if the sealing operation is performed in the atmosphere, it is unavoidable that metal oxidation occurs at the bonding points of the bonding wires arranged around the semiconductor element. Especially, from the viewpoint of cost, the bonding wire is made of silver, tin,
In the case of using those alloys, the resistance of the wire junction may increase due to the progress of metal oxidation, and in the worst case, the wire may be broken. For that purpose, a method of performing hermetic sealing in an atmosphere of an inert gas such as nitrogen gas is also implemented, but this method is difficult to manage the process.
【０００４】本発明は上記の点にかんがみなされたもの
であり、その目的は単純な工程でボンディングワイヤの
酸化進行，回路基板の劣化を抑え、併せて短い硬化処理
時間で蓋体と回路基板との間を接着できるようにした半
導体装置のパッケージング方法を提供することにある。The present invention has been made in view of the above points, and an object of the present invention is to suppress the progress of oxidation of bonding wires and the deterioration of a circuit board in a simple process, and at the same time, to provide a lid and a circuit board in a short curing time. It is another object of the present invention to provide a packaging method of a semiconductor device, which can bond between the two.
【０００５】[0005]
【課題を解決するための手段】上記目的は、本発明によ
り、蓋体と回路基板との接着を酸素量の少ない脱気雰囲
気中で行うことにより達成される。また、前記のパッケ
ージング方法においては、蓋体と回路基板との間を接合
する接着剤として嫌気性接着剤を用いるのがよく、かつ
接着剤の硬化処理を常温で行うことが好ましい。According to the present invention, the above object is achieved by bonding the lid and the circuit board in a degassing atmosphere with a small amount of oxygen. Further, in the above-mentioned packaging method, it is preferable to use an anaerobic adhesive as the adhesive for joining the lid and the circuit board, and it is preferable that the adhesive is cured at room temperature.
【０００６】[0006]
【作用】上記のパッケージング方法によれば、パッケー
ジの蓋体と回路基板との間の封止接合する接着剤として
嫌気性接着剤を用い、かつその作業工程を常温，かつ酸
素量の少ない脱気雰囲気中で行うようにしたので、処理
作業に伴うボンディングワイヤ接合点の酸化進行，およ
び回路基板の劣化が回避されるとともに、脱気雰囲気の
下で嫌気性接着剤の硬化反応が素早く進行し、短時間で
接着剤が硬化して蓋体と回路基板との間が気密封止され
るようになる。しかも、気密封止後はパッケージの内部
がそのまま脱気状態に保持されているので、半導体素子
を外部雰囲気からしゃ断することは勿論のこと、さらに
ボンディングワイヤの接合点に対する金属酸化進行を減
速して半導体装置の特性の長期安定化が図れる。According to the above-mentioned packaging method, an anaerobic adhesive is used as an adhesive for sealing and joining between the package lid and the circuit board, and the working process is performed at room temperature and with a small oxygen content. Since it is performed in an air atmosphere, oxidation of the bonding wire bonding point and deterioration of the circuit board due to processing work are avoided, and the curing reaction of the anaerobic adhesive quickly proceeds in a deaeration atmosphere. Then, the adhesive is cured in a short time so that the space between the lid and the circuit board is hermetically sealed. Moreover, since the inside of the package is kept in the degassed state as it is after the hermetic sealing, it goes without saying that the semiconductor element is cut off from the outside atmosphere, and further the metal oxidation progress to the bonding point of the bonding wire is slowed down. It is possible to stabilize the characteristics of the semiconductor device for a long period of time.
【０００７】[0007]
【実施例】以下本発明の実施例を図面に基づいて説明す
る。図１，図２において、１は半導体装置の回路基板、
１ａはその導体パターン、２は基板１に搭載した半導体
素子、３は半導体槽２と基板側の導体パターン１ａとの
間を接続するボンディングワイヤ、４は半導体素子２，
ボンディングワイヤ３を包囲して回路基板１の上に被着
したパッケージの蓋体であり、該蓋体４と回路基板１と
の間が面接着用の嫌気性接着剤５により接着して気密封
止される。Embodiments of the present invention will be described below with reference to the drawings. 1 and 2, 1 is a circuit board of a semiconductor device,
1a is its conductor pattern, 2 is a semiconductor element mounted on the substrate 1, 3 is a bonding wire for connecting the semiconductor tank 2 and the substrate-side conductor pattern 1a, 4 is a semiconductor element 2,
A lid of a package that surrounds the bonding wire 3 and is adhered onto the circuit board 1. The lid 4 and the circuit board 1 are hermetically sealed by bonding with an anaerobic adhesive 5 for surface bonding. To be done.
【０００８】そして、蓋体４を回路基板１に接着する際
には、図１で示すように蓋体４の底面に嫌気性接着剤５
を塗布した後、基板１，蓋体４を脱気容器６に収容し、
常温のままブロア７により排気して容器内を酸素量の少
ない暖気雰囲気状態にした上で、基板１の上の所定位置
に蓋体４を被着して嫌気性接着剤５を硬化させる。ここ
で、脱気量を適宜に管理することにより、ボンディング
ワイヤ３の金属酸化進行を抑制しつつ、嫌気性接着剤５
の硬化反応を素早く行うことができる。また、嫌気性接
着剤５の硬化処理を常温で行うことにより、高温加熱が
不要となるので回路基板１の導体箔接着強度が劣化する
おそれもなくなる。When the lid 4 is bonded to the circuit board 1, the anaerobic adhesive 5 is applied to the bottom surface of the lid 4 as shown in FIG.
After coating, the substrate 1 and the lid 4 are placed in the deaeration container 6,
At room temperature, the container is evacuated by a blower 7 to make the inside of the container a warm air atmosphere with a small amount of oxygen, and then a lid 4 is attached to a predetermined position on the substrate 1 to cure the anaerobic adhesive 5. Here, by appropriately managing the degassing amount, the anaerobic adhesive 5 is suppressed while suppressing the progress of metal oxidation of the bonding wire 3.
The curing reaction can be performed quickly. Further, since the curing treatment of the anaerobic adhesive 5 is carried out at room temperature, high temperature heating is not required, so that the conductor foil adhesive strength of the circuit board 1 does not deteriorate.
【０００９】[0009]
【発明の効果】以上述べたように、本発明のパッケージ
ング方法によれば、工程管理の厄介な不活性ガス雰囲気
中でのパッケージング方法を採ることなく、脱気のみの
単純な工程でボンディングワイヤの酸化進行，回路基板
の劣化を抑えつつ、併せて短い硬化処理時間で蓋体と回
路基板との間を接着することができ、これにより半導体
装置の組立工程の作業能率アップ，並びに製品の信頼性
向上に大きく寄与することができる。As described above, according to the packaging method of the present invention, bonding is performed by a simple process of only degassing without adopting a packaging method in an inert gas atmosphere where process control is difficult. While suppressing the progress of wire oxidation and deterioration of the circuit board, the lid and the circuit board can be bonded together in a short curing time, which improves the work efficiency of the assembly process of the semiconductor device and the product. It can greatly contribute to the improvement of reliability.
【図１】本発明の実施例による半導体装置のパッケージ
ング工程図FIG. 1 is a process diagram of packaging a semiconductor device according to an embodiment of the present invention.
【図２】図１における半導体装置の要部の平面図FIG. 2 is a plan view of a main part of the semiconductor device in FIG.
１ 回路基板 ２ 半導体素子 ３ ボンディングワイヤ ４ 蓋体 ５ 嫌気性接着剤 ６ 脱気容器 1 circuit board 2 semiconductor element 3 bonding wire 4 lid 5 anaerobic adhesive 6 degassing container
Claims (3)
ングワイヤを包囲して基板上に蓋体を被着して気密封止
した半導体装置に対し、蓋体と回路基板との接着を酸素
量の少ない脱気雰囲気中で行うことを特徴とする半導体
装置のパッケージング方法。1. A semiconductor device, which encloses a semiconductor element mounted on a circuit board and a bonding wire, is covered with a lid on the substrate and hermetically sealed. A method for packaging a semiconductor device, which is performed in a small degassing atmosphere.
て、蓋体と回路基板との間を接合する接着剤として嫌気
性接着剤を用いることを特徴とする半導体装置のパッケ
ージング方法。2. A packaging method for a semiconductor device according to claim 1, wherein an anaerobic adhesive is used as an adhesive for joining the lid and the circuit board together.
て、接着剤の硬化処理を常温で行うことを特徴とする半
導体装置のパッケージング方法。3. The packaging method according to claim 2, wherein the curing treatment of the adhesive is performed at room temperature.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4239864A JPH0689945A (en) | 1992-09-09 | 1992-09-09 | Method of packaging semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4239864A JPH0689945A (en) | 1992-09-09 | 1992-09-09 | Method of packaging semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0689945A true JPH0689945A (en) | 1994-03-29 |
Family
ID=17051022
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4239864A Pending JPH0689945A (en) | 1992-09-09 | 1992-09-09 | Method of packaging semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0689945A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6445062B1 (en) | 1999-02-19 | 2002-09-03 | Nec Corporation | Semiconductor device having a flip chip cavity with lower stress and method for forming same |
| KR20200049970A (en) | 2018-10-30 | 2020-05-11 | 한국생산기술연구원 | Bonding Apparatus Having Align Head |
-
1992
- 1992-09-09 JP JP4239864A patent/JPH0689945A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6445062B1 (en) | 1999-02-19 | 2002-09-03 | Nec Corporation | Semiconductor device having a flip chip cavity with lower stress and method for forming same |
| KR20200049970A (en) | 2018-10-30 | 2020-05-11 | 한국생산기술연구원 | Bonding Apparatus Having Align Head |
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