JPH0864721A - Ball grid array package for multichip module and its manufacture - Google Patents
Ball grid array package for multichip module and its manufactureInfo
- Publication number
- JPH0864721A JPH0864721A JP20181794A JP20181794A JPH0864721A JP H0864721 A JPH0864721 A JP H0864721A JP 20181794 A JP20181794 A JP 20181794A JP 20181794 A JP20181794 A JP 20181794A JP H0864721 A JPH0864721 A JP H0864721A
- Authority
- JP
- Japan
- Prior art keywords
- mcm
- solder
- layer ceramic
- package
- ceramic substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000000919 ceramic Substances 0.000 claims abstract description 49
- 239000002356 single layer Substances 0.000 claims abstract description 37
- 229910000679 solder Inorganic materials 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims description 51
- 239000011347 resin Substances 0.000 claims description 7
- 229920005989 resin Polymers 0.000 claims description 7
- 239000011521 glass Substances 0.000 claims description 4
- 239000011261 inert gas Substances 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 238000002844 melting Methods 0.000 claims description 2
- 230000008018 melting Effects 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 6
- 230000006866 deterioration Effects 0.000 abstract 1
- 239000000853 adhesive Substances 0.000 description 10
- 230000001070 adhesive effect Effects 0.000 description 10
- 238000007789 sealing Methods 0.000 description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical group N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 5
- 230000002950 deficient Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 229910001873 dinitrogen Inorganic materials 0.000 description 3
- 238000003466 welding Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000007872 degassing Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000010926 purge Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、複数のLSIチップが
一つの基板上に実装されているマルチチップ・モジュー
ル用のボール・グリッド・アレイ方式のパッケージに関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ball grid array type package for a multi-chip module in which a plurality of LSI chips are mounted on one substrate.
【0002】[0002]
【従来の技術】従来のマルチチップ・モジュール(以下
MCMと略す)のパッケージ技術には、パッケージの信
頼性に主眼を置いたものと低コスト化に主眼を置いたも
のがある。ここでMCMとは、高密度配線基板であるM
CM基板に複数のLSIチップが登載されたもの全体を
指す。2. Description of the Related Art Conventional multi-chip module (hereinafter abbreviated as MCM) packaging technologies include those focusing on package reliability and those focusing on cost reduction. Here, MCM is M, which is a high-density wiring board.
This refers to the entire CM board on which a plurality of LSI chips are mounted.
【0003】信頼性に主眼を置いたものには、図5に示
す積層セラミック基板21に、LSIチップ6が登載さ
れたMCM基板7つまりMCMと、ピン・グリッド・ア
レイ22を取り付けた後に、窒素雰囲気のチャンバー中
で金属のリッドを一個一個電気溶接することにより気密
封止を行うピン・グリッド・アレイ・タイプのパッケー
ジや上記ピン・グリッド・アレイの代わりにリードフレ
ームを用いたクワッド・フラット・パッケージなどがあ
る。また低コスト化に主眼をおいたものには、図6に示
す様なMCMとリードフレーム26をモールド樹脂27
で覆うことによりMCMを外気から遮断したプラスチッ
ク・パッケージがある。For reliability, the MCM substrate 7 on which the LSI chip 6 is mounted, that is, the MCM and the pin grid array 22 are mounted on the laminated ceramic substrate 21 shown in FIG. A pin grid array type package that performs hermetic sealing by electrically welding metal lids one by one in an atmosphere chamber and a quad flat package that uses a lead frame instead of the above pin grid array. and so on. Further, in order to reduce the cost, the MCM and the lead frame 26 as shown in FIG. 6 are molded resin 27.
There is a plastic package that shields the MCM from the outside air by covering it with.
【0004】[0004]
【発明が解決しようとする課題】しかし、図5のような
パッケージ方法では、リワークができるものの、外部端
子にピン・グリッド・アレイやリードフレームを用いる
ため高価な積層セラミック基板21を使用せざるを得な
く、また電気溶接により一個一個気密封止するため、ど
うしてもコストが高くなるという欠点がある。また図6
の様な樹脂封止は、一度封止するとパッケージを分解す
ることができないためリワークができないという欠点が
ある。However, in the packaging method as shown in FIG. 5, although rework is possible, an expensive laminated ceramic substrate 21 must be used because a pin grid array or a lead frame is used for the external terminals. There is a drawback in that the cost is inevitably increased because it is not obtained, and each is hermetically sealed by electric welding. See also FIG.
The resin encapsulation as described above has a drawback in that the package cannot be disassembled once encapsulation is performed and rework cannot be performed.
【0005】ここでリワークとは、パッケージしたMC
Mの動作テストを行い、不良LSIチップが発見された
場合に、不良のLSIチップを取り外し、良品と取り替
える作業をいう。MCMでは複数のLSIチップを登載
しているため、MCMの良品率は、登載しているLSI
チップの一つ一つの良品率の積になる。したがって、登
載するチップ数が増加するにつれ良品率は大幅に低下
し、リワークのできない構成では、パッケージ部品の単
価が低くても、かえって生産コストが高くなる場合があ
る。本発明の目的は、MCMの高速応答、高密度配線と
いう特徴を損なわず、リワークができ、低コストで組立
ができるMCM用ボール・グリッド・アレイ・パッケー
ジを実現することにある。Rework is the packaged MC.
The operation test of M is performed, and when a defective LSI chip is found, the defective LSI chip is removed and replaced with a good product. Since multiple LSI chips are registered in MCM, the good product rate of MCM is
It is the product of the good product rate of each chip. Therefore, as the number of chips to be mounted increases, the non-defective rate decreases significantly, and in a configuration in which reworking is not possible, the production cost may increase even if the unit price of the package component is low. An object of the present invention is to realize a ball grid array package for MCM which can be reworked and can be assembled at low cost without impairing the features of MCM such as high-speed response and high-density wiring.
【0006】[0006]
【課題を解決するための手段】上記目的を達成するため
に本発明は、マルチチップ・モジュール用ボール・グリ
ッド・アレイ・パッケージを、両端で電気的な接続がな
されている多数のスルーホールと前記スルーホールの周
囲に位置する半田と反応する材料で形成されたパッド電
極及び厚膜配線が形成された単層セラミック基板と、前
記スルーホールを塞いでいる半田の外部ボール電極と、
前記単層セラミック基板上に登載されたマルチチップ・
モジュールを覆うセラミックまたは金属のリッドにより
構成し、上記各部品を樹脂またはガラスにより固定した
後に、前記単層セラミック基板のスルーホール上に置い
た半田ボールを真空あるいは不活性ガス雰囲気下で溶融
し、パッド電極と反応させると同時に前記スルーホール
を塞ぐことによってパッケージを気密封止し、かつスル
ーホール外に残った半田を外部ボール電極とした。In order to achieve the above object, the present invention provides a ball grid array package for a multi-chip module having a large number of through holes electrically connected at both ends thereof. A single-layer ceramic substrate formed with a pad electrode and a thick film wiring formed of a material that reacts with solder located around the through hole; and an external ball electrode of the solder that closes the through hole.
Multi-chip mounted on the single-layer ceramic substrate
Composed of a ceramic or metal lid that covers the module, after fixing the above components with resin or glass, melt the solder balls placed on the through holes of the single-layer ceramic substrate under vacuum or an inert gas atmosphere, The package was hermetically sealed by simultaneously reacting with the pad electrode and closing the through hole, and the solder remaining outside the through hole was used as an external ball electrode.
【0007】[0007]
【作用】本発明の作用を、図1、2を用いて説明する。The operation of the present invention will be described with reference to FIGS.
【0008】まず、本発明のMCM用ボール・グリッド
・アレイ・パッケージでは、MCMと外部との電気的な
接続は以下のように取られる。MCM基板7と単層セラ
ミック基板1間はボンディング・ワイヤー9により、単
層セラミック基板1上ではボンディング・パッド5とス
ルーホール2間に形成された厚膜配線4により(図4参
照)、スルーホール2の両端は、スルーホール2の内壁
に導電性ペーストを塗布する等の処理により電気的な接
続がなされている。また半田ボール12を溶融しスルー
ホール2を塞いだ際にスルーホール2外に残った半田
が、外部ボール電極13として機能する。First, in the ball grid array package for MCM of the present invention, the electrical connection between the MCM and the outside is made as follows. Through-holes are formed by bonding wires 9 between the MCM substrate 7 and the single-layer ceramic substrate 1, and by thick-film wirings 4 formed between the bonding pads 5 and the through-holes 2 on the single-layer ceramic substrate 1 (see FIG. 4). Both ends of 2 are electrically connected by a process such as applying a conductive paste to the inner wall of the through hole 2. The solder remaining outside the through hole 2 when the solder ball 12 is melted and the through hole 2 is closed functions as the external ball electrode 13.
【0009】次に気密封止は、以下の様になされる。ま
ず、単層セラミック基板1とリッド10の境界が樹脂あ
るいはガラスによりシールされる。この時点で、パッケ
ージ内と外気は単層セラミック基板1のスルーホール2
を通じてのみ、継がっている。次に単層セラミック基板
1とリッド10間をシール後、パッケージ内を真空にす
るか不活性ガスでパージする。その後、スルーホール2
上に置いた半田ボール12を溶融し、スルーホール2を
塞ぐことにより気密封止が完了する。ここで塞ぐとは、
スルーホール2の開口部が全て半田により覆われ、気体
等の移動が断たれている状態をいい、スルーホール2内
に半田が侵入していても、侵入していなくても、どちら
でもよい。スルーホール2の周囲に形成してあるパッド
電極3(図3参照)が、半田と反応する材料で形成され
ているため、半田ボール12はスルーホール2と強固に
密着する。Next, the hermetic sealing is performed as follows. First, the boundary between the single-layer ceramic substrate 1 and the lid 10 is sealed with resin or glass. At this time, the inside of the package and the outside air are the through holes 2 of the single-layer ceramic substrate 1.
Only through. Next, after sealing between the single-layer ceramic substrate 1 and the lid 10, the inside of the package is evacuated or purged with an inert gas. After that, through hole 2
Airtight sealing is completed by melting the solder ball 12 placed on the upper side and closing the through hole 2. Blocking here means
This means a state in which the openings of the through holes 2 are all covered with solder and the movement of gas or the like is interrupted, and it does not matter whether the solder has entered the through holes 2 or not. Since the pad electrode 3 (see FIG. 3) formed around the through hole 2 is formed of a material that reacts with solder, the solder ball 12 firmly adheres to the through hole 2.
【0010】次にリワークは以下の様に行う。まず不良
LSIチップが発見された場合には、パッケージを加熱
し、樹脂あるいはガラスの接着力を低下させ、リッド1
0を単層セラミック基板1から剥離する。次にLSIチ
ップ6とMCM基板7間が半田で接続されている場合は
半田を溶かし、ボンディング・ワイヤーで結線されてい
る場合はワイヤーを切断した後、不良のLSIチップを
MCM基板7から、リッド10を剥離したときと同様の
方法で剥離し、良品と交換する。LSIチップ交換後
は、請求項2に記載の本発明の製造方法に従いMCMを
パッケージすることにより、リワークが終了する。Next, rework is performed as follows. First, when a defective LSI chip is found, the package is heated to lower the adhesive strength of the resin or glass, and the lid 1
0 is separated from the single-layer ceramic substrate 1. Next, if the LSI chip 6 and the MCM board 7 are connected by solder, the solder is melted, and if the bonding wire is connected, the wire is cut, and then the defective LSI chip is removed from the MCM board 7 by the lid. Peel off in the same manner as when peeling off 10 and replace with a good product. After replacement of the LSI chip, rework is completed by packaging the MCM according to the manufacturing method of the present invention according to claim 2.
【0011】[0011]
【実施例】図1に本発明の実施例の断面図を示す。本発
明は、両端で電気的な接続がなされている多数のスルー
ホール2を有する単層セラミック基板1上に、複数のL
SIチップ6が登載されたMCM基板7、つまりMCM
が接着されている。さらに該MCMを保護するようにリ
ッド10が前記単層セラミック基板1上に接着された構
造となっている。また、前記スルーホール2の下には、
半田による外部ボール電極13が形成されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a sectional view of an embodiment of the present invention. According to the present invention, a plurality of L's are provided on a single-layer ceramic substrate 1 having a large number of through holes 2 electrically connected at both ends.
MCM board 7 on which SI chip 6 is mounted, that is, MCM
Are glued together. Further, the lid 10 is bonded on the single-layer ceramic substrate 1 so as to protect the MCM. Further, under the through hole 2,
The external ball electrode 13 made of solder is formed.
【0012】以下、本発明の製造方法を図2の本発明の
MCM用ボール・グリッド・アレイ・パッケージの組立
手順を表す図を用い説明する。The manufacturing method of the present invention will be described below with reference to the flow chart of FIG. 2 showing the procedure for assembling the ball grid array package for MCM of the present invention.
【0013】単層セラミック基板1として、直径0.4
mmのスルーホール2が224個形成されたアルミナ基
板を用いた(図3、4参照)。前記単層セラミック基板
1の片面には、スルーホール2の周囲に、Ag−Pdペ
ーストによりパッド電極3が形成してある(図3参
照)。また、前記単層セラミック基板1の上記の面と別
の面には、Ag−Pdペーストによる圧膜配線4とAu
ペーストによるボンディング・パッド5が施されており
(図4参照)、スルーホール2の内壁にも、半田との濡
れ性を良くするためAg−Pdペーストが塗布され、ス
ルーホール2両端の電気的接続が取られている。The single-layer ceramic substrate 1 has a diameter of 0.4.
An alumina substrate having 224 mm through holes 2 was used (see FIGS. 3 and 4). A pad electrode 3 is formed on one surface of the single-layer ceramic substrate 1 around the through hole 2 by Ag-Pd paste (see FIG. 3). Further, on the surface other than the above-mentioned surface of the single-layer ceramic substrate 1, the pressure film wiring 4 made of Ag-Pd paste and the Au film are formed.
A bonding pad 5 made of paste is applied (see FIG. 4), and Ag-Pd paste is applied to the inner wall of the through hole 2 to improve wettability with solder, and electrical connection between both ends of the through hole 2 is made. Has been taken.
【0014】まず前記単層セラミック基板1の圧膜配線
4が施されている側(図4参照)に複数のLSIチップ
6を登載したMCM基板7を絶縁性接着剤8により接着
した。絶縁性接着剤8の固化は前記絶縁性接着剤8を1
70℃に2時間保持することにより行った。ここで前記
MCM基板7と前記単層セラミック基板1を接着する
際、全てのスルーホール2がMCM基板7の下に位置し
たのでは気密封止の際のガス抜きが出来ない。そこで、
MCM基板7に覆われない位置にもスルーホール2が存
在するように単層セラミック基板1は設計されている。First, an MCM substrate 7 having a plurality of LSI chips 6 mounted thereon is adhered to the side of the single-layer ceramic substrate 1 on which the pressure film wiring 4 is provided (see FIG. 4) by an insulating adhesive 8. When the insulating adhesive 8 is solidified, the insulating adhesive 8
It was carried out by holding at 70 ° C. for 2 hours. Here, when the MCM substrate 7 and the single-layer ceramic substrate 1 are bonded together, if all the through holes 2 are located under the MCM substrate 7, degassing at the time of airtight sealing cannot be performed. Therefore,
The single-layer ceramic substrate 1 is designed so that the through holes 2 also exist at positions not covered by the MCM substrate 7.
【0015】次に酸素プラズマおよびアルゴンプラズマ
によりMCM基板7と単層セラミック基板1のクリーニ
ングを行った後、LSIチップ6とMCM基板7間、M
CM基板7と単層セラミック基板1間をそれぞれAuの
ボンディング・ワイヤー9により結線した。次に、結線
が終了した単層セラミック基板1にセラミック製の箱型
のリッド10をLSIチップ6が登載されたMCM基板
7を保護するように被せ、接着剤11で固定した。接着
剤11はリッド10と単層セラミック基板1の接触面全
体に塗布し、シールを完全なものとした。接着剤11の
固化は前述の絶縁性接着剤8と同様、170℃の環境に
2時間保持することにより行った。Next, after cleaning the MCM substrate 7 and the single-layer ceramic substrate 1 with oxygen plasma and argon plasma, M between the LSI chip 6 and the MCM substrate 7
The CM substrate 7 and the single-layer ceramic substrate 1 were connected by Au bonding wires 9 respectively. Next, the single-layer ceramic substrate 1 on which the connection was completed was covered with a ceramic box-shaped lid 10 so as to protect the MCM substrate 7 on which the LSI chip 6 was mounted, and fixed with an adhesive 11. The adhesive 11 was applied to the entire contact surface between the lid 10 and the single-layer ceramic substrate 1 to complete the seal. The adhesive 11 was solidified by holding it in an environment of 170 ° C. for 2 hours as in the case of the insulating adhesive 8.
【0016】次にリッド10が接着された単層セラミッ
ク基板1を前記単層セラミック基板1のスルーホール2
が開いている側が上を向くように反転させた後、スルー
ホール2上に直径0.8mmの半田ボール12を置い
た。Next, the single-layer ceramic substrate 1 to which the lid 10 is bonded is attached to the through-hole 2 of the single-layer ceramic substrate 1.
After reversing so that the open side faces upward, a solder ball 12 having a diameter of 0.8 mm was placed on the through hole 2.
【0017】最後にパッケージの気密封止を加熱炉内で
行った。まず、上記のスルーホール2上に半田ボール1
2を置いたパッケージを、室温に保持してある加熱炉内
に挿入した。次に加熱炉内を真空に引いた後に窒素ガス
を炉内に導入する、窒素パージを数回繰り返すことによ
り、パッケージ内を完全に窒素ガスで置換した。窒素ガ
ス置換後、炉内温度を半田が溶融する183℃以上に昇
温し、半田ボール12を溶融した。融けた半田がパッド
電極3と反応するとともにスルーホール2を塞ぐことで
気密封止が終了した。また、単層セラミック基板1外側
に残った半田ボール12は外部ボール電極13として用
いることができた。以上の手順で単層セラミック基板を
用いたマルチチップモジュール用のパッケージが終了し
た。Finally, the package was hermetically sealed in a heating furnace. First, solder balls 1 are placed on the through holes 2 described above.
The package in which No. 2 was placed was inserted into a heating furnace kept at room temperature. Next, the interior of the package was completely replaced with nitrogen gas by evacuating the heating furnace and introducing nitrogen gas into the furnace, and repeating the nitrogen purge several times. After substituting with nitrogen gas, the temperature inside the furnace was raised to 183 ° C. or higher at which the solder melted, and the solder balls 12 were melted. The melted solder reacts with the pad electrode 3 and closes the through hole 2 to complete the hermetic sealing. Further, the solder balls 12 remaining on the outer side of the single-layer ceramic substrate 1 could be used as the external ball electrodes 13. With the above procedure, the package for the multi-chip module using the single-layer ceramic substrate is completed.
【0018】[0018]
【発明の効果】本発明では、MCMを積層セラミック基
板ではなく安価な単層セラミック基板上に実装している
ため、セラミック基板の単価を4分の1に低くすること
ができた。According to the present invention, since the MCM is mounted not on the laminated ceramic substrate but on the inexpensive single-layer ceramic substrate, the unit cost of the ceramic substrate can be reduced to one fourth.
【0019】また半田ボールを溶融し、単層セラミック
基板のスルーホールを塞ぐことにより気密封止を行うた
め、多数個のパッケージを加熱炉により一括処理するこ
とができた。Further, since the solder balls are melted and the through holes of the single-layer ceramic substrate are closed to hermetically seal, a large number of packages can be collectively processed by a heating furnace.
【0020】以上のように本発明を用いることにより、
MCMの高速応答、高密度配線という特徴を損なわず、
低コストで組立ができるMCM用パッケージが実現でき
た。By using the present invention as described above,
Without losing the characteristics of MCM such as high-speed response and high-density wiring,
We have realized a package for MCM that can be assembled at low cost.
【図1】図1は本発明の実施例の断面を示す図である。FIG. 1 is a diagram showing a cross section of an embodiment of the present invention.
【図2】図2は本発明の組立手順を表す図である。FIG. 2 is a diagram showing an assembly procedure of the present invention.
【図3】図3は本発明で用いる単層セラミック基板の一
面を示す図である。FIG. 3 is a diagram showing one surface of a single-layer ceramic substrate used in the present invention.
【図4】図4は本発明で用いる単層セラミック基板の他
の一面を示す図である。FIG. 4 is a diagram showing another surface of a single-layer ceramic substrate used in the present invention.
【図5】図5は従来のピン・グリッド・アレイ・タイプ
のパッケージの断面を示す図である。FIG. 5 is a view showing a cross section of a conventional pin grid array type package.
【図6】図6は従来のプラスチック・パッケージの断面
を示す図である。FIG. 6 is a cross-sectional view of a conventional plastic package.
1 単層セラミック基板 2 スルーホール 3 パッド電極 4 厚膜配線 5 ボンディング・パッド 6 LSIチップ 7 MCM基板 8 絶縁性接着剤 9 ボンディング・ワイヤー 10 リッド 11 接着剤 12 半田ボール 13 外部ボール電極 21 積層セラミック基板 22 ピン・グリッド・アレイ 23 ウェルドリング 24 電気溶接部 25 ダイパッド 26 リードフレーム 27 モールド樹脂 1 Single Layer Ceramic Substrate 2 Through Hole 3 Pad Electrode 4 Thick Film Wiring 5 Bonding Pad 6 LSI Chip 7 MCM Substrate 8 Insulating Adhesive 9 Bonding Wire 10 Lid 11 Adhesive 12 Solder Ball 13 External Ball Electrode 21 Multilayer Ceramic Substrate 22 pin grid array 23 weld ring 24 electric welding part 25 die pad 26 lead frame 27 molding resin
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 25/04 25/18 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Office reference number FI technical display location H01L 25/04 25/18
Claims (2)
ら遮断するパッケージにおいて、両端で電気的な接続が
なされている多数のスルーホールと前記スルーホールの
周囲に位置する半田と反応する材料で形成されたパッド
電極及び厚膜配線が形成された単層セラミック基板と、
前記スルーホールを塞いでいる半田の外部ボール電極
と、前記単層セラミック基板上に登載されたマルチチッ
プ・モジュールを覆うセラミックまたは金属のリッドに
より構成されていることを特徴とするマルチチップ・モ
ジュール用ボール・グリッド・アレイ・パッケージ。1. A package for shielding a multi-chip module from the outside air environment, wherein the package is formed of a material that reacts with a large number of through holes electrically connected at both ends and a solder located around the through holes. A single-layer ceramic substrate on which a pad electrode and a thick film wiring are formed,
For a multi-chip module, which is composed of an external ball electrode of solder that closes the through hole, and a ceramic or metal lid that covers the multi-chip module mounted on the single-layer ceramic substrate. Ball grid array package.
ボール・グリッド・アレイ・パッケージにおいて、上記
各部品を樹脂またはガラスにより固定した後に、前記単
層セラミック基板のスルーホール上に置いた半田ボール
を真空あるいは不活性ガス雰囲気下で溶融し、パッド電
極と反応させると同時に前記スルーホールを半田で塞ぐ
ことによってパッケージを気密封止し、かつスルーホー
ル外に残った半田を外部ボール電極とすることを特徴と
したマルチチップ・モジュール用ボール・グリッド・ア
レイ・パッケージの製造方法。2. The ball grid array package for a multi-chip module according to claim 1, wherein the solder balls placed on the through-holes of the single-layer ceramic substrate after fixing the respective parts with resin or glass are used. The package is hermetically sealed by melting it in a vacuum or an inert gas atmosphere and reacting with the pad electrode, and at the same time closing the through hole with solder, and using the solder remaining outside the through hole as an external ball electrode. A method of manufacturing a featured ball grid array package for a multichip module.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20181794A JPH0864721A (en) | 1994-08-26 | 1994-08-26 | Ball grid array package for multichip module and its manufacture |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20181794A JPH0864721A (en) | 1994-08-26 | 1994-08-26 | Ball grid array package for multichip module and its manufacture |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0864721A true JPH0864721A (en) | 1996-03-08 |
Family
ID=16447403
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP20181794A Pending JPH0864721A (en) | 1994-08-26 | 1994-08-26 | Ball grid array package for multichip module and its manufacture |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0864721A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6032852A (en) * | 1997-09-22 | 2000-03-07 | Trw Inc. | Reworkable microelectronic multi-chip module |
US6229208B1 (en) * | 1997-12-09 | 2001-05-08 | Trw Inc. | Postless large multichip module with ceramic lid for space applications |
KR20030052125A (en) * | 2001-12-20 | 2003-06-26 | 동부전자 주식회사 | Semiconductor package and fabrication method thereof |
KR100656295B1 (en) * | 2004-11-29 | 2006-12-11 | (주)웨이브닉스이에스피 | Package using selective anodized metal and its manufacturing method |
CN110828606A (en) * | 2019-12-09 | 2020-02-21 | 中国电子科技集团公司第四十三研究所 | A kind of ceramic photoelectric coupler and its manufacturing method |
-
1994
- 1994-08-26 JP JP20181794A patent/JPH0864721A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6032852A (en) * | 1997-09-22 | 2000-03-07 | Trw Inc. | Reworkable microelectronic multi-chip module |
US6050476A (en) * | 1997-09-22 | 2000-04-18 | Trw Inc. | Reworkable microelectronic multi-chip module |
US6229208B1 (en) * | 1997-12-09 | 2001-05-08 | Trw Inc. | Postless large multichip module with ceramic lid for space applications |
KR20030052125A (en) * | 2001-12-20 | 2003-06-26 | 동부전자 주식회사 | Semiconductor package and fabrication method thereof |
KR100656295B1 (en) * | 2004-11-29 | 2006-12-11 | (주)웨이브닉스이에스피 | Package using selective anodized metal and its manufacturing method |
CN110828606A (en) * | 2019-12-09 | 2020-02-21 | 中国电子科技集团公司第四十三研究所 | A kind of ceramic photoelectric coupler and its manufacturing method |
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