JPH0685075A - Formation of multilayer interconnection - Google Patents

Abstract

PURPOSE:To accurately form a resist pattern for forming a connecting hole in a layer insulating film in a multilayer interconnection forming method. CONSTITUTION:After forming a wiring layer 18 made of aluminum or an aluminum alloy on an insulating film 16 covering the upper surface of a semiconductor substrate 10, the wiring layer 18 is covered and a layer insulating film 20 such as silicon oxide is formed, and then a reflection preventive film of TiN, etc., is formed on the surface of the insulating film 20. After forming a resist layer on the reflection prevented film, an opening corresponding to a desired connection hole is formed by applying an exposure and developing treatment to this resist layer. And a connecting hole 28 is formed by selectively the insulating film 20 with the resist layer having the opening as mask. After removing the resist layer, a wiring layer 30 is formed on the upper surface of the substrate, but a remaining portion 22A of the reflection preventive film may be used as part of the wiring layer 30.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a multi-layer wiring used in the manufacture of integrated circuit devices such as LSI, and more particularly to forming a contact hole by forming an antireflection film such as TiN on an interlayer insulating film. The resist pattern can be formed with high precision.

[0002]

2. Description of the Related Art Conventionally, as a method of accurately forming a resist pattern for forming a connection hole in an interlayer insulating film, TiN is formed on the surface of the lower wiring layer before the interlayer insulating film is formed so as to cover the lower wiring layer. There is known a method of forming an antireflection film such as the above (see, for example, JP-A-1-266746). 8 and 9 show an example of a conventional multilayer wiring forming method using this type of method.

In the process shown in FIG. 8, TiN, Al alloy (eg, Al-C) is formed on the insulating film 2 covering the surface of the semiconductor substrate 1.
u) and TiN are sequentially deposited and patterned to form the wiring layer 3 including the TiN layer 3a, the Al alloy layer 3b, and the TiN layer 3c. The TiN layer 3a is used as a barrier metal layer, and the TiN layer 3c is used as an antireflection film.

Next, the wiring layer 3 is covered on the insulating film 2,
After forming the interlayer insulating film 4 that has been smoothed, a resist layer 5 is formed on the insulating film 4. Then, the resist layer 5 is exposed and developed to form an opening corresponding to a desired connection hole, and the connection hole 6 is formed into the insulating film 4 by a selective etching process using the resist layer 5 having the opening as a mask. To form. At this time, if the portion of the TiN layer 3c located directly below the connection hole 6 is removed by etching, an increase in contact resistance can be avoided.

When the surface of the wiring material layer having a high reflectance such as the Al alloy layer 3b or the Al layer is covered with the antireflection film such as the TiN layer 3c, the light reflection from the wiring surface is reflected during the exposure process. Since it is suppressed by the prevention film, the opening pattern of the resist layer 5 is distorted due to light reflection from the wiring surface,
It can be prevented from expanding. When the wiring layer 3 is formed on a flat surface, the film thickness of the TiN layer 3c is 30 to 50 [nm] in order to suppress reflection of light for exposure.
Is enough. With this thickness, the insulating film 4 and the T
The light reflected at the interface with the iN layer 3c is not reflected by the layer 3c below it.
And 3b interfere with the light reflected at the interface between them and serve as an antireflection function.

In the step of FIG. 9, after removing the resist layer 5, a wiring material such as Al or Al alloy is deposited on the upper surface of the substrate and patterned to form the wiring layer 7. The wiring layer 7 is connected to the wiring layer 3 via the connection hole 6.

[0007]

According to the above-mentioned conventional method, when patterning the wiring layer 3 in the step of FIG. 8, the TiN layer 3a and the Al alloy layer 3b are used with the resist layer as a mask.
When the stack of the TiN layer 3c and the TiN layer 3c is etched, side etching easily occurs in the Al alloy layer 3b. For this reason, the line width of the Al alloy layer 3b becomes thin, and there is an inconvenience that the wiring resistance increases and electromigration resistance and stress migration resistance decrease.

Further, if a film of TiN or the like is directly deposited on a conventionally used wiring for the purpose of preventing reflection, the characteristics of the wiring are expected to change, and a reliability evaluation test requiring a long time is required. There is also an inconvenience.

An object of the present invention is to provide a novel method for forming a multi-layer wiring which can form a resist pattern for forming a connection hole with high precision by using an antireflection film without causing the above inconvenience. It is in.

[0010]

A multilayer wiring forming method according to the present invention comprises: (a) a step of forming a first wiring layer on an insulating surface of a substrate; and (b) forming a first wiring layer on the insulating surface. A step of forming an interlayer insulating film to cover the first wiring layer,
(C) a step of forming an antireflection film on the interlayer insulating film, and (d) a desired connection by forming a resist layer on the antireflection film and then subjecting the resist layer to an exposure / development process. Forming an opening corresponding to the hole; and (e) selectively stacking the antireflection film and the interlayer insulating film by using the resist layer as a mask to reach the first wiring layer. To form the connection hole,
(F) a step of removing at least the resist layer of the resist layer and the antireflection film remaining after the formation of the connection hole, and (g) connecting to the first wiring layer through the connection hole. And a step of forming a second wiring layer on the interlayer insulating film.

In such a multilayer wiring forming method, the antireflection film remaining after the formation of the connection hole may be used as a part of the second wiring layer.

[0012]

According to the method of the present invention, since the antireflection film is formed on the interlayer insulating film, the light reflection from the interlayer insulating film and the first wiring layer is suppressed when the resist layer is exposed. It Further, since it is not necessary to provide an antireflection film on the surface of the first wiring layer, side etching does not occur in the first wiring layer during patterning.

As described above, the remaining antireflection film is formed into a second film.
When used as a part of the wiring layer, the second wiring layer can be a wiring layer having a two-layer structure in which a TiN layer is arranged under an Al alloy layer, for example.

[0014]

1 and 2 show a method of forming a multi-layer wiring according to an embodiment of the present invention. Steps (1) and (2) corresponding to the respective figures will be sequentially described.

(1) A field insulating film 12 made of silicon oxide is formed on the surface of a semiconductor substrate 10 made of, for example, silicon by a selective oxidation process, and then a gate insulating film 12 made of silicon oxide is formed by a thermal oxidation method.
G is formed. Then, the wiring layer 14 and the gate electrode layer 14G are formed on the upper surface of the substrate by depositing an electrode material such as polysilicon to a thickness of about 400 nm by the CVD method or the like and patterning the electrode material.

Next, an interlayer insulating film 16 made of BPSG (boron phosphosilicate glass) is formed on the upper surface of the substrate by CVD to cover the wiring layer 14 and the gate electrode layer 14G. Then, the insulating film 16 is subjected to a heat treatment at about 900 ° C. so as to be flowed to reduce a step due to a wiring layer and the like below. Even when the step reducing process is performed in this manner, undulations corresponding to the film thickness of the wiring layer remain as shown in FIG.

Next, the wiring layer 18 is formed by depositing and patterning an Al alloy such as Al-Cu on the insulating film 16 by a sputtering method or the like. As shown in FIG. 1, at the location where the wiring layer 18 is formed so as to overlap the step of the insulating film 16, the light reflection is likely to spread particularly during resist exposure, so that anti-reflection measures are highly necessary.

Next, an interlayer insulating film 20 made of SiO ₂ and SOG (spin on glass) is formed on the insulating film 16 by covering the wiring layer 18 by plasma CVD. Then, a TiN film having a thickness of, for example, 20 to 200 [nm] is formed as the antireflection film 22 on the insulating film 20. The TiN film may be formed by reactive sputtering with Ar and N ₂ using a Ti target or TiC.
ECR plasma CVD with l ₄ gas can be used.

Next, a resist layer 24 is formed on the upper surface of the substrate by a spin coating method or the like. Then, the resist layer 24 is subjected to an exposure process for forming a connection hole. That is, in the exposure mask 26, the resist layer 24 is irradiated with the ultraviolet light UV through the transparent portion 26A corresponding to the desired connection hole, and the connection hole pattern is printed on the resist layer 24. After that, when the resist layer 24 is subjected to a development process, an opening portion corresponding to the light transmitting portion 26A of the exposure mask 26 is formed in the resist layer 24.

(2) Next, the resist layer 2 having openings
Insulating film 2 by dry etching process using 4 as a mask
0 and the antireflection film 22 are formed with connection holes 28. Since the antireflection film 22 is formed on the insulating film 20, light reflection from the insulating film 20 and the wiring layer 18 during resist exposure is suppressed, and the resist layer 24 after the development process has an opening as designed. Are formed, and the connection hole 28 as designed is obtained in the subsequent selective etching process. Therefore, it is not necessary to take the width of the wiring layer 18 into consideration in consideration of the distortion and spread of the resist opening pattern, so that the degree of integration can be improved.

Next, the resist layer 24 is removed. Then, a wiring material such as Al or Al alloy is deposited on the upper surface of the substrate and patterned to form the wiring layer 30. In patterning at this time, the remaining portion 2 of the antireflection film 22
2A is also patterned at the same time, and the remaining portion 22A is used as a part of the wiring layer 30. The wiring layer 30 thus obtained is composed of an Al or Al alloy layer and a Ti layer thereunder.
Since it has a two-layer structure with an N layer, it is highly resistant to electromigration and stress migration and highly reliable.

In the above embodiment, the material of the antireflection film 22 is not limited to TiN, but TiON, TiW or the like may be used. The wiring layer 30 may be made of W (tungsten) formed by the CVD method. In this case,
An antireflection film such as TiN works as a W adhesion enhancing layer by the CVD method. Further, as the material of the wiring layer 18, Al
Not limited to alloys, Al or the like may be used. Furthermore, after removing the resist layer 24, the remaining portion 22A of the antireflection film is formed.
It may also be removed so that it does not exist below the wiring layer 30.

FIG. 3 shows a two-layer wiring structure for explaining another embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals and detailed description thereof will be omitted.

As shown in FIG. 3, the wiring layer 18 is connected to the wiring layer 1.
When the insulating film 16 is formed on a non-planar portion such as a step due to 4 or the like, the light for exposure is reflected by the wiring layer 18 not only in the vertical direction but also in the oblique direction when the resist is exposed. The patterning accuracy of the resist is considerably reduced. Therefore, in such a case, it is necessary to pay special attention to the antireflection film 22 formed on the insulating film 20 covering the wiring layer 18.

[0025] In FIG. 3, made of SiO ₂ insulating films 2
0, the TiN film 22 and the positive resist layer 24 have refractive indices of 1.45 to 1.5, 2.3 and 1.67, respectively. As described above, the refractive index between the insulating film 20 and the TiN film 22 is greatly different, and the TiN film 22 and the resist layer 2 are different from each other.
Since the refractive index greatly differs from that of No. 4, when light passes through these layers, the light is reflected at the interface between the layers. In particular, when the TiN film 22 is thin, the light incident through the resist layer 24 undergoes multiple reflection.

That is, the light incident on the resist layer 24 travels through the resist layer 24 and reaches the interface between the TiN film 22 and the resist layer 24, and a part of the light is reflected at this interface, but the rest. Light propagates through the TiN film 22 while being attenuated, and reaches the interface between the TiN film 22 and the insulating film 20.
A part of the light reaching the interface between the TiN film 22 and the insulating film 20 is reflected to the TiN side at the interface, and the rest of the light is the insulating film 2.
It is incident at 0. The light incident on the insulating film 20 receives the insulating film 2
0, and is reflected upward by the wiring layer 18 made of Al alloy. At this time, the light reflected upward is the insulating film 20.
Is reflected downward at the interface between the TiN film 22 and the TiN film 22, and the remaining light travels upward. Part of the light that travels upward is reflected downward at the interface between the TiN film 22 and the resist layer 24, and the remaining light travels into the resist layer 24. In this way, many reflections are overlapped, which is the multiple reflection.

Therefore, it is necessary to control the thickness of the TiN film 22 so that light does not pass through the TiN film 22. Figure 4-
7 shows the relationship between the thickness a of the TiN film 22 (TiN film thickness) a and the reflectance Ir / Io when the g-line (wavelength 436 nm) as the ultraviolet light for exposure is vertically incident as shown in FIG. The result of calculation using the thickness (interlayer film thickness) d of the insulating film 20 as a parameter is shown. Here, Io is the amount of input light, and Ir is the amount of reflected light (the amount of light that emerges from the surface due to surface reflection, lower surface reflection, multiple reflection, etc.).

The inventor of the present application, from this calculation result, Ti
It has been found that when the N film thickness is 80 [nm] or more, the deterioration of the resist patterning accuracy due to reflection can be sufficiently suppressed when the g-line is used.

In order to reach this conclusion, the following (a),
The item (b) is mentioned as a condition.

(B) The reflectivity does not change significantly even if the interlayer film thickness varies. The insulating film 20 is obtained by depositing by the CVD method or by spin-coating and then thermosetting. It is difficult to control. In the multi-layer wiring structure, the second wiring layer 18 is not flat in most cases, and the insulating film 20 formed thereon is not flat in many cases. Therefore, with respect to the light for exposure, the interlayer film thickness with respect to the incident direction varies depending on the location, but if the reflectance Ir / Io does not change so much, the patterning accuracy does not change much.

(B) Reflectance is 0.3 or less A positive resist is used as the resist layer 24,
The smaller the amount of light that is irradiated, the more convenient it is, but in practice,
It is sufficient if the reflectance Ir / Io is 0.3 or less. I
If r / Io exceeds 0.5, there is a high possibility that the resist layer 24 will be exposed undesirably to the masked portion.

If the TiN film thickness is 80 nm or more,
It is clear from FIGS. 4 to 7 that these conditions (a) and (b) are satisfied. 4 to 7, the curve S
₁ , S ₂ , S ₃ , S ₄ , S ₅ , S ₆ , S ₇ , and S ₈ have an interlayer film thickness d of 800 [nm], 825 [nm], and 850.
[Nm], 875 [nm], 900 [nm], 925
[Nm], 950 [nm], and 975 [nm] are shown respectively.

[0033]

As described above, according to the present invention, the antireflection film is provided on the interlayer insulating film to suppress the light reflection from the lower side during the resist exposure. The pattern can be accurately formed.
Further, since side etching does not enter the lower wiring layer at the time of patterning, it is possible to avoid problems such as an increase in wiring resistance and a decrease in reliability due to a thin line width. Further, since the wiring which has been used conventionally can be used as it is, the reliability evaluation test of the wiring is unnecessary.

If a conductive antireflection film such as TiN is left as it is after forming the contact hole and is used as a part of the upper wiring layer, a highly reliable wiring resistant to electromigration and stress migration can be easily formed without additional steps. Can be formed.

[Brief description of drawings]

FIG. 1 is a substrate cross-sectional view showing a resist processing step in a multilayer wiring forming method according to an embodiment of the present invention.

FIG. 2 is a substrate cross-sectional view showing a wiring forming process following the process of FIG.

FIG. 3 is a sectional view showing a two-layer wiring structure for explaining another embodiment of the present invention.

FIG. 4 shows an interlayer film thickness d of 800 [nm] and 825 [n]
3] A graph showing the relationship between the TiN film thickness a and the reflectance Ir / Io when [m].

FIG. 5 is a graph showing the relationship between a and Ir / Io when d is 850 [nm] and 875 [nm].

FIG. 6 is a graph showing the relationship between a and Ir / Io when d is 900 [nm] and 925 [nm].

FIG. 7 is a graph showing the relationship between a and Ir / Io when d is 950 [nm] and 975 [nm].

FIG. 8 is a substrate cross-sectional view showing a connection hole forming step in a conventional multilayer wiring forming method.

9 is a substrate cross-sectional view showing a wiring forming process following the process of FIG.

[Explanation of symbols]

10: semiconductor substrate, 12, 16, 20: insulating film, 14,
18, 30: wiring layer, 22: antireflection film, 24: resist layer, 26: exposure mask.

Claims (2)

[Claims] 1. A step of (a) forming a first wiring layer on an insulating surface of a substrate, and (b) an interlayer insulating film covering the first wiring layer on the insulating surface. Forming step, (c) forming an antireflection film on the interlayer insulating film, and (d) forming a resist layer on the antireflection film, and then subjecting the resist layer to exposure / development treatment. Thereby forming an opening corresponding to a desired connection hole, and (e) selectively using the resist layer as a mask to selectively etch the laminate of the antireflection film and the interlayer insulating film to form the first layer in the laminate. Forming a connection hole so as to reach the wiring layer of (f), (f) removing at least the resist layer of the resist layer and the antireflection film remaining after the formation of the connection hole, (g) the connection hole To be connected to the first wiring layer via Multilayer wiring formation method comprising the steps of a wiring layer formed on the interlayer insulating film. 2. The method for forming a multilayer wiring according to claim 1, wherein an antireflection film remaining after forming the connection hole is used as a part of the second wiring layer.