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JPH0677665A - Multilayered circuit board and manufacture thereof - Google Patents

Multilayered circuit board and manufacture thereof

Info

Publication number
JPH0677665A
JPH0677665A JP4250371A JP25037192A JPH0677665A JP H0677665 A JPH0677665 A JP H0677665A JP 4250371 A JP4250371 A JP 4250371A JP 25037192 A JP25037192 A JP 25037192A JP H0677665 A JPH0677665 A JP H0677665A
Authority
JP
Japan
Prior art keywords
circuit board
film
multilayer circuit
surface layer
passive element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4250371A
Other languages
Japanese (ja)
Inventor
Toshio Ogawa
敏夫 小川
Tadamichi Asai
忠道 浅井
Noritaka Kamimura
典孝 神村
Shuji Kato
修治 加藤
Mitsuru Hasegawa
長谷川  満
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP4250371A priority Critical patent/JPH0677665A/en
Publication of JPH0677665A publication Critical patent/JPH0677665A/en
Pending legal-status Critical Current

Links

Landscapes

  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)

Abstract

PURPOSE:To obtain a small-sized high-density multilayered circuit board for electronic industries including high-frequency applications by forming heat- resistant surface layer portions in the whole of the board surface or in a part thereof on which a film-like passive element is disposed. CONSTITUTION:A multilayered circuit board which has a resistive conductor wiring 16 having a resistivity which does not exceed 5muOMEGA-cm in an inter-layer 22 formed by sequentially depositing insulating materials, and in which surface layer portions 21 and a film-like passive element 12 are disposed. The heat- resistant surface layer portions 21 are formed in the whole of the board surface or at least in a part thereof on which the film-like passive element 12 is disposed. This can prevent damage of the insulator around the board surface and the inner conductor wiring due to the thermal effect of a beam in trimming. Thus, a high-precision trimming is available and a low-resistance wiring including a high-precision film-like passive element can be provided, so that a multilayered circuit board of a smaller size and higher density can be achieved. Further, a high-speed and high-frequency signal can be provided.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、民生用やコンピュータ
用など電子工業に用いられる多層回路基板に係り、詳し
くは低抵抗性導体配線を内蔵し、表面に高精度の電気的
特性を有する膜状受動素子を配置した高密度多層回路基
板及びその製法と用途とに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer circuit board used in the electronics industry such as for consumer use and computers, and more specifically, a film having a low resistance conductor wiring built therein and having highly precise electric characteristics on its surface. High-density multilayer circuit board having passive elements arranged therein, its manufacturing method and use.

【0002】[0002]

【従来の技術】近年のハイブリッドICは、より小型
化、高密度化の要求から、グリーンシート上に電極パタ
ーンを印刷形成し、これらを積層、焼結することによっ
て、もしくは、スクリーン印刷の繰返しによって多層化
し、焼結することによって、基板内部に配線パターンを
持つセラミック多層配線基板が用いられてきた。その基
板を大別すると次の二つがある。その一つとして、例え
ば、特公平3−78798号公報の従来技術として記載
されるように、WやMoを配線導体として使用し、15
00〜1600℃の高い温度で同時焼成するセラミック
ス多層基板がある。他の一つとして、例えば、特開昭6
3−244899号公報に開示される、通常1000℃
以下の比較的低い温度で絶縁体の焼結ができる低温焼結
性セラミックス基板がある。
2. Description of the Related Art In recent years, hybrid ICs have been required to be smaller and have a higher density, by forming electrode patterns on a green sheet by printing, laminating and sintering them, or by repeating screen printing. A ceramic multilayer wiring board having a wiring pattern inside the board by multilayering and sintering has been used. There are two main types of substrates. As one of them, for example, W and Mo are used as wiring conductors as described in Japanese Patent Publication No. 3-78798.
There is a ceramic multilayer substrate that is co-fired at a high temperature of 00 to 1600 ° C. As another one, for example, Japanese Laid-Open Patent Publication No.
Normally disclosed at 1000 ° C., which is disclosed in Japanese Patent Publication No.
There are low-temperature sinterable ceramic substrates that can sinter the insulator at the following relatively low temperatures.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、上記の
高温で焼成される基板は、導体の抵抗率が大きく、高周
波用回路への適用に難があると共に、微細配線化による
回路の高密度化ができないという欠点があった。一方、
低温焼結性の基板では、焼成温度が低いので、同時焼成
する内蔵配線用導体材料として、Au、Ag、Cuなど
のいわゆる低抵抗性導体材料が使用できる。その為、前
述の導体抵抗率に関する問題点は解消できる。しかしな
がら、この基板の表層部に例えば厚膜抵抗体などの受動
素子を配置し、レーザービームによるトリミング工程を
加えると、その熱影響によって素子周辺の絶縁層も同時
に溶融してしまうという問題が生ずる。
However, the above-mentioned substrate fired at a high temperature has a large conductor resistivity and is difficult to apply to a high-frequency circuit, and the circuit density can be increased by fine wiring. There was a drawback that I could not. on the other hand,
Since the low-temperature sinterable substrate has a low firing temperature, a so-called low-resistance conductor material such as Au, Ag, or Cu can be used as the conductor material for built-in wiring that is simultaneously fired. Therefore, the above-mentioned problems regarding the conductor resistivity can be solved. However, when a passive element such as a thick film resistor is arranged on the surface layer portion of this substrate and a trimming process by a laser beam is added, there is a problem that the insulating layer around the element is also melted due to the thermal effect.

【0004】すなわち、レーザービームの出力が低い
と、素子の切断が十分でなく、高い信頼性が得られな
い。一方、出力が高過ぎると、低温焼結性材料であるた
め、絶縁体そのものが損傷を受け、例えば層間の絶縁特
性保障ができなくなってしまうなどの障害がある。従っ
て、レーザートリミングの条件が極めて狭い領域に限定
され、実用上難がある。以上記したように、低抵抗性導
体配線を内蔵し、表層に膜状受動素子を配置した多層回
路基板では高精度の素子を得にくいという問題があっ
た。本発明は、こうした問題点を解決し、高精度の電気
的特性を有する受動素子を包含し、かつ低抵抗性の導体
配線を内蔵した、小型かつ高密度の、高周波用途を含む
電子工業用多層回路基板及びその製法と用途とを提供す
ることを目的とする。
That is, when the output of the laser beam is low, the element is not sufficiently cut and high reliability cannot be obtained. On the other hand, if the output is too high, the insulator itself is damaged because it is a low temperature sinterable material, and there is a problem that the insulation characteristics between layers cannot be guaranteed. Therefore, the conditions for laser trimming are limited to an extremely narrow region, which poses a practical problem. As described above, there is a problem in that it is difficult to obtain a highly accurate element in a multilayer circuit board in which a low resistance conductor wiring is built in and a film-like passive element is arranged on the surface layer. The present invention solves these problems, includes a passive element having high-precision electrical characteristics, and has a built-in low-resistance conductor wiring. An object of the present invention is to provide a circuit board, a manufacturing method thereof and an application.

【0005】[0005]

【課題を解決するための手段】上記目的を達成するため
に、本発明では、絶縁性材料を積層して構成された層間
に、抵抗率5μΩ−cmを超えない低抵抗性導体配線を
有し、かつ表層部に膜状受動素子が配置された多層回路
基板において、該基板表面の全面又は少なくとも該膜状
受動素子が配置された一部に耐熱性表層部が形成されて
いることとしたものである。
In order to achieve the above object, in the present invention, a low resistance conductor wiring having a resistivity of not more than 5 μΩ-cm is provided between layers formed by laminating insulating materials. A heat-resistant surface layer part is formed on the entire surface of the substrate or at least a part of the surface where the filmy passive element is arranged, Is.

【0006】また、本発明では、絶縁性材料を積層して
構成された層間に、抵抗率5μΩ−cmを超えない低抵
抗性導体配線を有し、かつ表層部に膜状受動素子が配置
された多層回路基板の製法において、低抵抗性の導体配
線を含む内層の絶縁性材料の積層体を形成する工程、該
積層体の表面の全面又は局部に耐熱性表層部を形成する
工程、該形成した耐熱性表層部の少なくとも一部が重な
りあう位置に膜状受動素子を形成する工程、該膜状受動
素子の電気的特性をレーザービームによるトリミング工
程によって調節することとしたものである。上記におい
て、耐熱性表層部はアルミナを主成分として構成するの
がよく、また、絶縁性材料は、組成中に含まれるアルミ
ナの占める体積分率が、内層部では最大でも40%であ
り、表層部では少なくとも50%であるのがよい。
Further, according to the present invention, a low resistance conductor wiring having a resistivity of not more than 5 μΩ-cm is provided between layers formed by laminating insulating materials, and a film-like passive element is arranged in the surface layer portion. In the method for producing a multilayer circuit board, a step of forming a laminate of an insulating material of an inner layer including a low resistance conductor wiring, a step of forming a heat resistant surface layer portion on the entire surface or a local portion of the laminate, The step of forming a film-like passive element at a position where at least a part of the heat-resistant surface layer portion is overlapped, and the electrical characteristics of the film-like passive element are adjusted by a trimming step with a laser beam. In the above, it is preferable that the heat-resistant surface layer part is composed mainly of alumina, and the insulating material has a volume fraction of alumina contained in the composition of 40% at maximum in the inner layer part. It should be at least 50% in parts.

【0007】上記のように、本発明は、絶縁性材料を積
層した基板の内層部に、Au、Ag、Cuなどの低抵抗
性導体配線を配置し、少なくともトリミング工程におけ
るレーザービームの照射される部分に対応した位置に耐
熱性表層部を設けることによって、該トリミング工程を
容易ならしめ、高精度の電気的特性を有する受動素子を
包含し、かつ低抵抗性の導体配線を内蔵した、小型かつ
高密度の、高周波用途を含む電子工業用多層回路基板を
実現したものである。
As described above, according to the present invention, the low resistance conductor wiring of Au, Ag, Cu or the like is arranged in the inner layer portion of the substrate in which the insulating material is laminated, and the laser beam is irradiated at least in the trimming step. By providing a heat-resistant surface layer portion at a position corresponding to the portion, the trimming process is facilitated, a passive element having high-precision electrical characteristics is included, and a low-resistance conductor wiring is built in. It is a high-density multi-layer circuit board for the electronic industry including high-frequency applications.

【0008】前記絶縁性材料は通常、軟化点の低い低温
焼結性ガラスで構成され、配線導体と同時焼成される。
前記耐熱性表層部の形成にあたっては、大別二つの方法
がある。一つは、予め例えばアルミナなどの耐熱性の高
い材料が表層部に偏在するように組成分布調整したグリ
ーンシートの成形体を準備し、内層導体配線と同時焼成
する方法である。他の一つは、低抵抗性の導体配線を内
蔵した、所定の積層回路を形成後に、該耐熱性表層部
を、例えばゾル−ゲル法などの他の成膜手段により別工
程で形成する方法である。
The insulating material is usually made of low-temperature sinterable glass having a low softening point and is co-fired with the wiring conductor.
There are roughly two methods for forming the heat resistant surface layer. One is a method of preparing a green sheet molded body whose composition distribution is adjusted in advance so that a material having high heat resistance such as alumina is unevenly distributed in the surface layer portion, and simultaneously firing the inner layer conductor wiring. The other one is a method of forming a predetermined laminated circuit incorporating a low-resistance conductor wiring and then forming the heat-resistant surface layer portion in another step by another film forming means such as a sol-gel method. Is.

【0009】本発明による上記積層回路基板の表面に、
受動素子として厚膜抵抗体を形成することによって、そ
の後のレーザービームを用いたトリミング工程が容易と
なり、高精度の素子を包含し、かつ低抵抗性導体配線を
内蔵する多層回路基板が得られる。さらに、受動素子と
して容量素子を形成した場合にも、その電極部分をレー
ザートリミングすることにより、素子の容量調整が容易
に可能となる。例えば、本発明による多層回路基板の内
層用絶縁体材料として、ほうけい酸鉛系ガラスを用いる
ことによって、850℃程度の温度でも焼結可能とな
り、基板の強度を確保するとともに、Au、Ag、Cu
などの低抵抗性導体材料を同時焼結することができる。
On the surface of the laminated circuit board according to the present invention,
By forming a thick film resistor as a passive element, the subsequent trimming process using a laser beam is facilitated, and a multilayer circuit board including a highly accurate element and including a low resistance conductor wiring is obtained. Further, even when a capacitive element is formed as a passive element, the capacitance of the element can be easily adjusted by laser trimming the electrode portion of the capacitive element. For example, by using lead borosilicate-based glass as the insulating material for the inner layer of the multilayer circuit board according to the present invention, it becomes possible to sinter even at a temperature of about 850 ° C., the strength of the board is secured, and Au, Ag, Cu
Low resistance conductor materials such as can be co-sintered.

【0010】本発明による、前記耐熱性表層部を形成す
るに当たって、組成の異なる内層絶縁体部との境界領域
に、両組成の混合層による適度の濃度勾配を設けた、い
わゆる傾斜組成構造化することによって、たとえば温度
変化時の熱膨張係数の差異による応力の発生など不安定
現象を抑制することができ、高信頼性回路基板が提供で
きる。そして、本発明で得られる多層回路基板は、高精
度の膜状受動素子を包含し、かつ低抵抗導体配線を有し
ているので、携帯用のカメラ一体型ビデオ装置並びに信
号を高速化した通信用電子機器やコンピュータなどを構
成する電子回路基板として有効活用できる。
In forming the heat-resistant surface layer portion according to the present invention, a so-called graded composition structure is provided in which a proper concentration gradient is provided by a mixed layer of both compositions in the boundary region with the inner layer insulator portion having a different composition. As a result, an unstable phenomenon such as stress generation due to a difference in thermal expansion coefficient when the temperature changes can be suppressed, and a highly reliable circuit board can be provided. Since the multilayer circuit board obtained by the present invention includes the film-like passive element with high precision and has the low resistance conductor wiring, the portable camera-integrated video device and the communication for speeding up the signal are carried out. It can be effectively used as an electronic circuit board that constitutes electronic equipment, computers, etc.

【0011】[0011]

【作用】本発明は、低抵抗性の導体配線を内蔵し、その
表面に耐熱性表層部を形成して膜状受動素子を配置する
構造である。従って、レーザービームによるトリミング
に際して、ビームの熱影響による基板表層周辺の絶縁体
並びに内層の導体配線の損傷を抑制することができる。
その為、精度の高いトリミングが容易に可能となり、高
精度の膜状受動素子を包含する低抵抗配線化した多層回
路基板を実現するものである。一方、基板の内層部は耐
熱性は低いが、低温焼結性の良い絶縁材料を用いること
により、基板の強度を確保することができる。
The present invention has a structure in which a low-resistance conductor wiring is built in, a heat-resistant surface layer portion is formed on the surface thereof, and a film-like passive element is arranged. Therefore, at the time of trimming with the laser beam, it is possible to suppress damage to the insulator around the surface layer of the substrate and the conductor wiring in the inner layer due to the thermal effect of the beam.
Therefore, highly accurate trimming can be easily performed, and a multilayer circuit board including a highly accurate film-like passive element and having low resistance wiring is realized. On the other hand, the inner layer portion of the substrate has low heat resistance, but the strength of the substrate can be secured by using an insulating material having good low-temperature sinterability.

【0012】上記多層回路基板用導体材料として、A
u、Ag、Cu、Pt、Pdのうちの少なくとも一つを
適用することによって、WもしくはMo等の高温焼結性
の導体に比較して、回路の導電性を著しく高くすること
ができ、導体配線の微細パターン化が可能である。従っ
て、上記受動素子の高信頼性化と相まって、より小型、
高密度の多層回路基板が実現できる。さらに、5μΩ−
cm以下の低抵抗性の導体材料を適用することで、回路
で処理する信号の高速化もしくは高周波化が可能であ
る。
As the conductor material for the multilayer circuit board, A
By applying at least one of u, Ag, Cu, Pt, and Pd, the conductivity of the circuit can be significantly increased as compared with a high temperature sinterable conductor such as W or Mo. It is possible to make fine wiring patterns. Therefore, in combination with higher reliability of the passive element, smaller size,
A high-density multilayer circuit board can be realized. Furthermore, 5μΩ-
By applying a conductor material having a low resistance of 10 cm or less, it is possible to increase the speed or frequency of signals processed by a circuit.

【0013】[0013]

【実施例】以下、本発明を実施例によって詳細に説明す
るが、本発明はこれらに限定されない。。 実施例1 図1に本発明の一実施例を示す。図1は本発明による多
層回路基板の厚膜抵抗体を含む部分断面図を示してい
る。まず、ほうけい酸鉛ガラス粉と耐熱性フリットとし
てのアルミナ粉末に、ポリビニルブチラール等の有機溶
媒を加えてかくはんし、泥漿化状態にする。この泥漿
を、ドクターブレードを用いたキャスティング成膜法に
よって未焼成の誘導性グリーンシートを複数枚形成す
る。このグリーンシートを形成する段階で、含有するア
ルミナ粉末の量を3つの水準とする。アルミナ粉末の多
い順にA、B、Cの3種のグリーンシートを準備する。
アルミナ粉末の添加量は、焼成後のセラミック中に占め
る体積比基準でそれぞれおよそ60%,40%,20%
となるように調節する。
EXAMPLES The present invention will now be described in detail with reference to examples, but the present invention is not limited thereto. . Embodiment 1 FIG. 1 shows an embodiment of the present invention. FIG. 1 is a partial sectional view including a thick film resistor of a multilayer circuit board according to the present invention. First, an organic solvent such as polyvinyl butyral is added to lead borosilicate glass powder and alumina powder as a heat-resistant frit, and the mixture is stirred to form a sludge. A plurality of unfired inductive green sheets are formed from this slurry by a casting film forming method using a doctor blade. At the stage of forming this green sheet, the amount of alumina powder contained is set to three levels. Three types of green sheets A, B, and C are prepared in the order of the alumina powder.
The amount of alumina powder added is about 60%, 40%, and 20%, respectively, based on the volume ratio in the ceramic after firing.
Adjust so that

【0014】次に、ステンレス等から成る金型で外形と
複数個の孔部(ビアホール)とを同時にパンチングして
形成する。このグリーンシート上に、通常3μΩ−cm
より低い抵抗率が得られる銀を主成分とする導体ペース
トを、スクリーン印刷法によって塗布して、電極パター
ン11もしくは内層導体配線16を形成すると共にビア
ホール14を充填する。同様に作成した複数のグリーン
シートを用いて順次積み重ねる。この時、先に準備した
グリーンシートCを用いて所定層数の内層導体配線部2
2を形成し、続けてB、Aの順にグリーンシートを各一
枚ずつ積層し、グリーンシートAが表層にくるようにす
る。次いで、熱プレス機等を用いて温度120℃、圧力
200kg/cm2 の条件で上下面から熱圧着して、グ
リーンシートの積層体を得る。
Next, the outer shape and a plurality of holes (via holes) are formed by punching at the same time with a metal mold made of stainless steel or the like. On this green sheet, usually 3μΩ-cm
A conductor paste containing silver as a main component, which has a lower resistivity, is applied by a screen printing method to form the electrode pattern 11 or the inner layer conductor wiring 16 and fill the via hole 14. It stacks up sequentially using a plurality of similarly prepared green sheets. At this time, by using the green sheet C previously prepared, the inner layer conductor wiring portion 2 having a predetermined number of layers is formed.
No. 2 is formed, and one green sheet is successively laminated in the order of B and A so that the green sheet A is on the surface. Next, using a hot press machine or the like, thermocompression bonding is performed from the upper and lower surfaces under the conditions of a temperature of 120 ° C. and a pressure of 200 kg / cm 2 to obtain a green sheet laminate.

【0015】この成形体を、空気中、温度350℃で約
1時間脱脂した後、やはり空気中で800−1000℃
約10分の焼成によって、表層部にアルミナ組成部17
を多く含む耐熱性表層部21を有し、かつ低抵抗性の内
層導体配線部27を低温焼結性のガラスセラミック組成
部18に内蔵した多層回路基盤を得る。さらに、この基
板上にRuO2 を主体とする抵抗体12をスクリーン印
刷によって形成した後、乾燥−焼成して厚膜抵抗体を構
成する。通常は、さらにこの抵抗体上にガラスペースト
を印刷−乾燥し、600℃以下の低い温度で焼成して、
保護皮膜15を形成して、多層回路基板が完成する。こ
の状態で、抵抗体12の抵抗値を測定すると、ばらつき
が大きく、通常目標値の約±15%の範囲に分散する。
This molded body was degreased in air at a temperature of 350 ° C. for about 1 hour and then in air again at 800-1000 ° C.
By firing for about 10 minutes, the alumina composition part 17 is formed on the surface layer part.
A multi-layer circuit board having a heat resistant surface layer portion 21 containing a large amount and containing a low resistance inner layer conductor wiring portion 27 in a low temperature sinterable glass ceramic composition portion 18 is obtained. Further, a resistor 12 mainly composed of RuO 2 is formed on this substrate by screen printing, and then dried and fired to form a thick film resistor. Usually, a glass paste is further printed-dried on this resistor and fired at a low temperature of 600 ° C. or lower,
The protective film 15 is formed to complete the multilayer circuit board. When the resistance value of the resistor 12 is measured in this state, there is a large variation, and the resistance value is normally dispersed within about ± 15% of the target value.

【0016】次いで、レーザービームによって、目標と
する個別の抵抗値に対応して、トリミング部13を形成
して抵抗値調節する。この工程により、抵抗体12の抵
抗値は目標値に対する誤差を±1%以内に容易に設定で
きる。この工程のレーザービーム照射時の熱影響によっ
ても、この種基板表面は耐熱性の良好な層が形成されて
いるため、内部の絶縁体及び導体配線の損傷を最小限に
留めることができる。なお、ガラスペーストによる保護
皮膜を形成しない状態で、トリミングした後、抵抗体1
2表面に200℃以下の温度で樹脂等による保護被膜1
5を形成する事により、同様に抵抗値の安定性を向上さ
せることができる。
Then, the trimming portion 13 is formed by the laser beam so as to correspond to the target individual resistance value, and the resistance value is adjusted. By this step, the error of the resistance value of the resistor 12 with respect to the target value can be easily set within ± 1%. Also due to the thermal influence of the laser beam irradiation in this step, since a layer having excellent heat resistance is formed on the surface of the seed substrate, it is possible to minimize damage to the internal insulator and conductor wiring. After trimming without forming a protective film made of glass paste, the resistor 1
2 Protective coating 1 made of resin on the surface at a temperature of 200 ° C or less
By forming 5, the stability of the resistance value can be similarly improved.

【0017】本実施例では、耐熱性材料としてアルミナ
フィラーを用いた例を示したが、他の材料例えば、Al
N、ZrO2 、SiO2 、TiO2 など他の材料系であ
っても良い。また、本実施例では、膜状受動素子として
厚膜抵抗体の例について示したが、これは厚膜もしくは
薄膜プロセスなどで形成される他の受動素子、例えばイ
ンダクタ、容量素子などの場合にも同様にトリミングが
容易に可能である。また、内層の導体材料として、Ag
を用いた例について詳細に記してきたが、Au、Pt、
Pd及びこれらの合金についても同様に使用可能であ
る。Cuについても、不活性ガス中で焼成することによ
り適用可能である。
In the present embodiment, an example in which an alumina filler is used as the heat resistant material is shown, but other materials such as Al can be used.
Other materials such as N, ZrO 2 , SiO 2 , TiO 2 may be used. In addition, in the present embodiment, an example of a thick film resistor is shown as a film passive element, but this is also applicable to other passive elements formed by a thick film or thin film process such as an inductor and a capacitive element. Similarly, trimming is easily possible. In addition, as the conductor material of the inner layer, Ag
The example using is described in detail, but Au, Pt,
Pd and these alloys can be used as well. Cu can also be applied by firing in an inert gas.

【0018】実施例2 実施例1と同様の手順によって、ビアホール14に導体
ペーストが充填され、かつ表層電極パターン11及び内
層導体配線16を形成した複数枚のグリーンシートを得
る。この時、実施例1に示すグリーンシートA中のアル
ミナフィラーの含有量を調節して、焼成後のセラミック
中の体積百分率がおよそそれぞれ80、70、60、5
0、40、30、20、10%となるように準備した。
グリーンシートの厚さは約100μm一定とした。これ
らのうち、アルミナフィラーの含有量が同じ複数枚のグ
リーンシートを組み合わせて積み重ね、その後は実施例
1と同様の要領で導体配線を内蔵した焼成多層体を作製
する。
Example 2 By the same procedure as in Example 1, a plurality of green sheets were obtained in which the via holes 14 were filled with a conductor paste and the surface layer electrode patterns 11 and the inner layer conductor wirings 16 were formed. At this time, the content of the alumina filler in the green sheet A shown in Example 1 was adjusted so that the volume percentage in the fired ceramic was about 80, 70, 60, 5 respectively.
It was prepared so as to be 0, 40, 30, 20, 10%.
The thickness of the green sheet was approximately 100 μm. Among these, a plurality of green sheets having the same content of the alumina filler are combined and stacked, and thereafter, a fired multilayer body containing conductor wiring is manufactured in the same manner as in Example 1.

【0019】図2に本実施例によるサンプルの断面構成
図を示す。この基板の焼成温度は850℃とし、焼成後
の厚さは約0.7mmである。これらサンプルについて
次の評価をした。一つは、4点曲げ抗折強度であり、他
は層間の絶縁抵抗値である。前者については、内層導体
配線の無い状態、すなわちセラミック単体で評価した。
後者の評価については、図2に示すトリミング部13の
位置に、レーザービームを照射してトリミングを行い、
表層電極11及び内層導体16との間の絶縁抵抗値を測
定した。トリミング条件はレーザーパルス発信周波数3
kHz、出力2.4W、ビーム速度25mm/secで
ある。
FIG. 2 is a sectional view showing the structure of a sample according to this embodiment. The baking temperature of this substrate is 850 ° C., and the thickness after baking is about 0.7 mm. The following evaluation was performed on these samples. One is the 4-point bending strength, and the other is the insulation resistance value between layers. The former was evaluated in the state where there was no inner layer conductor wiring, that is, the ceramic alone.
For the latter evaluation, the position of the trimming portion 13 shown in FIG. 2 is irradiated with a laser beam for trimming,
The insulation resistance value between the surface layer electrode 11 and the inner layer conductor 16 was measured. Trimming conditions are laser pulse transmission frequency 3
The output is 2.4 W and the beam velocity is 25 mm / sec.

【0020】これらの測定結果を図3に示す。アルミナ
の体積分率が40%を超えると抗折強度の低下が顕著と
なる。これは、層内のガラス組成の量が不足し、十分な
焼成ができなくなる為である。一方、層間の絶縁抵抗値
は、通常109 Ω以上が要求される。しかし、アルミナ
含有量が50%に満たないと耐熱性が低いために表層部
の絶縁体の損傷が大きく、十分な層間絶縁抵抗が得られ
ない。以上の実験結果からこの両特性、すなわち、低温
焼結性並びに耐熱性を同一組成の基板で実現するのは難
しいことがわかる。従って、絶縁性材料中のアルミナ含
有量は内層部では最大40%、表層部では少なくとも5
0%とする必要がある。
The results of these measurements are shown in FIG. If the volume fraction of alumina exceeds 40%, the transverse rupture strength is significantly reduced. This is because the amount of the glass composition in the layer is insufficient and sufficient firing cannot be performed. On the other hand, the insulation resistance value between layers is usually required to be 10 9 Ω or more. However, if the alumina content is less than 50%, the heat resistance is low and the insulator in the surface layer portion is largely damaged, so that sufficient interlayer insulation resistance cannot be obtained. From the above experimental results, it is understood that it is difficult to realize both of these characteristics, that is, low temperature sinterability and heat resistance with a substrate having the same composition. Therefore, the maximum alumina content in the insulating material is 40% in the inner layer and at least 5 in the surface layer.
It should be 0%.

【0021】実施例3 実施例1と同様の材料及び手順によって、グリーンシー
トの積層体を得る。ここでは、アルミナ含有量の最も少
ない、実施例1に示すグリーンシートCのみで構成す
る。このグリーンシートの積層体を実施例1と同様の条
件で焼成する。さらに、次の工程で厚膜抵抗体を形成す
る位置の基板表面に、前述した耐熱性表層部として、ゾ
ル−ゲル法により、膜厚約3μmのアルミナ皮膜を形成
する。この皮膜上に、実施例1と同様に厚膜抵抗体を形
成する。次いで、この抵抗体にガラスペーストを塗布
し、600℃以下の温度で焼成して保護皮膜15を形成
し、該保護被膜15の上からレーザービームを用いて形
状トリミングし、抵抗値の微調節をすることによって、
実施例1と同様に高精度で安定した厚膜抵抗体素子を含
む高密度多層回路基板を得る。
Example 3 A green sheet laminate is obtained by using the same materials and procedures as in Example 1. Here, only the green sheet C shown in Example 1 having the smallest alumina content is used. This green sheet laminate is fired under the same conditions as in Example 1. Further, an alumina film having a thickness of about 3 μm is formed as the above-mentioned heat resistant surface layer portion by the sol-gel method on the surface of the substrate where the thick film resistor is to be formed in the next step. A thick film resistor is formed on this film as in the first embodiment. Next, a glass paste is applied to this resistor and baked at a temperature of 600 ° C. or less to form a protective film 15, and the protective film 15 is trimmed with a laser beam to finely adjust the resistance value. By,
As in Example 1, a high-density multilayer circuit board including a highly accurate and stable thick film resistor element is obtained.

【0022】本実施例では、ゾル−ゲル法によるアルミ
ナの耐熱性表層部を形成する例について示したが、例え
ばSiO2 、CoO、MnO、TiO2 などの他の材料
を中心とするものであっても良い。さらに、皮膜形成方
法として、たとえばスパッタ、溶射など他の方法であっ
ても良い。以上の実施例は、いずれもセラミック多層回
路基板の例を示したが、例えば絶縁体材料としてガラス
エポキシを用いたプリント配線基板などにも、本発明の
適用が可能である。
In this embodiment, an example of forming the heat resistant surface layer portion of alumina by the sol-gel method has been shown, but other materials such as SiO 2 , CoO, MnO and TiO 2 are mainly used. May be. Further, the film forming method may be another method such as sputtering or thermal spraying. Although all of the above examples show examples of ceramic multilayer circuit boards, the present invention can be applied to, for example, a printed wiring board using glass epoxy as an insulating material.

【0023】実施例4 実施例1と同様の手順によって、導体層6層及び表面に
厚膜抵抗素子を配置した多層回路基板を作製する。この
多層基板に、いわゆる表面実装技術によってLSI、ト
ランジスタなどの能動素子を中心とする電子部品を半田
によって接合する。さらに、回路外部への入出力用リー
ドフレームを1.27mmの狭ピッチで半田接合し、本
発明による映像信号処理回路モジュールが完成する。こ
の基板寸法は35mm×27.5mmである。第1層及
び第2層の回路パターンを図4及び図5に示す。本発明
によれば、高精度で微細な厚膜抵抗素子を高密度に多数
形成でき、さらにその上にLSIなど比較的面積の広い
素子を重ねて実装することができ、30素子/cm2
上の高密度実装が可能となった。このモジュールをカメ
ラ一体型ビデオ装置若しくは携帯用電子機器に適用する
ことによって、装置のより小型化、高性能化に効果的で
ある。
Example 4 By the same procedure as in Example 1, a multilayer circuit board having 6 layers of conductor layers and a thick film resistance element arranged on the surface thereof is prepared. Electronic components centering on active elements such as LSI and transistors are joined to this multilayer substrate by soldering by so-called surface mounting technology. Further, the lead frames for input and output to the outside of the circuit are soldered at a narrow pitch of 1.27 mm, and the video signal processing circuit module according to the present invention is completed. The substrate dimensions are 35 mm x 27.5 mm. Circuit patterns of the first layer and the second layer are shown in FIGS. 4 and 5. According to the present invention, a large number of high-precision and fine thick-film resistance elements can be formed at a high density, and an element having a relatively large area such as an LSI can be stacked and mounted thereon, and 30 elements / cm 2 or more. It has become possible to implement high-density mounting. By applying this module to a video device with a built-in camera or a portable electronic device, it is effective for further miniaturization and high performance of the device.

【0024】実施例5 実施例1と同様の手順によって、導体層15層及び表面
に終端抵抗などの厚膜抵抗素子を配置した多層回路基板
を作製する。この基板に実施例4と同様に電子部品を表
面実装し、周波数GHz帯まで使用できる高周波系回路
を作製し、通信用電子機器に適用する。本発明によれ
ば、厚膜抵抗素子に重ねてLSIを配置することができ
るので基板寸法の小型化が可能となる。その結果LSI
間の信号アクセス配線距離を短縮でき、通信回線の高周
波化、高速化に効果的である。
Example 5 By the same procedure as in Example 1, a multilayer circuit board in which a thick film resistance element such as a terminating resistor is arranged on the conductor layer 15 layer and the surface is prepared. Electronic components are surface-mounted on this substrate in the same manner as in Example 4, a high frequency system circuit that can be used up to a frequency band of GHz is manufactured, and applied to communication electronic devices. According to the present invention, since the LSI can be arranged on the thick film resistance element, the size of the substrate can be reduced. As a result LSI
The signal access wiring distance between them can be shortened, which is effective in increasing the frequency and speed of communication lines.

【0025】[0025]

【発明の効果】本発明によれば、低抵抗性導体配線を内
蔵し、かつ高精度膜状受動素子を包含した多層回路基板
とすることができるので、導体パターンの微細配線化が
可能となり、電子回路の小型化もしくは高密度比に貢献
でき、特に高速化または高周波化回路に有効使用でき
る。
According to the present invention, since it is possible to provide a multi-layer circuit board having a built-in low-resistance conductor wiring and including a high-precision film-like passive element, it is possible to make the conductor pattern fine wiring. It can contribute to downsizing or high density ratio of electronic circuits, and can be effectively used especially for high speed or high frequency circuits.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例による多層回路基板の断面構
成図。
FIG. 1 is a cross-sectional configuration diagram of a multilayer circuit board according to an embodiment of the present invention.

【図2】本発明の実施例2による試験用サンプルの断面
構成図。
FIG. 2 is a sectional configuration diagram of a test sample according to Example 2 of the present invention.

【図3】本発明の実施例2による多層回路基板の特性評
価結果を示すグラフ。
FIG. 3 is a graph showing a characteristic evaluation result of a multilayer circuit board according to a second embodiment of the present invention.

【図4】本発明の実施例4による多層基板の第1層回路
パターン図。
FIG. 4 is a first layer circuit pattern diagram of a multilayer substrate according to Example 4 of the present invention.

【図5】本発明の実施例4による多層基板の第2層回路
パターン図。
FIG. 5 is a second layer circuit pattern diagram of the multilayer substrate according to the fourth embodiment of the present invention.

【符号の説明】[Explanation of symbols]

11:表層電極、12:抵抗体、13:トリミング部、
14:ビア、15:保護皮膜、16:内層導体、17:
アルミナ組成部、18:ガラスセラミック組成部、2
1:耐熱性表層部、22:内層導体配線部。
11: surface electrode, 12: resistor, 13: trimming part,
14: via, 15: protective film, 16: inner layer conductor, 17:
Alumina composition part, 18: Glass-ceramic composition part, 2
1: heat resistant surface layer part, 22: inner layer conductor wiring part.

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 H01L 23/12 23/15 27/01 311 8418−4M H05K 1/16 C 6921−4E 3/28 A 7511−4E (72)発明者 加藤 修治 茨城県日立市久慈町4026番地 株式会社日 立製作所日立研究所内 (72)発明者 長谷川 満 茨城県日立市久慈町4026番地 株式会社日 立製作所日立研究所内─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Internal reference number FI Technical display location H01L 23/12 23/15 27/01 311 8418-4M H05K 1/16 C 6921-4E 3/28 A 7511-4E (72) Inventor Shuji Kato 4026, Kuji-machi, Hitachi City, Hitachi, Ibaraki Prefecture, Hitachi Research Laboratory, Inc. (72) Inventor, Mitsuru Hasegawa 4026, Kuji-machi, Hitachi City, Ibaraki Institute, Hitachi Research Institute, Ltd.

Claims (10)

【特許請求の範囲】[Claims] 【請求項1】 絶縁性材料を積層して構成された層間
に、抵抗率5μΩ−cmを超えない低抵抗性導体配線を
有し、かつ表層部に膜状受動素子が配置された多層回路
基板において、該基板表面の全面又は少なくとも該膜状
受動素子が配置された一部に耐熱性表層部が形成されて
いることを特徴とする多層回路基板。
1. A multi-layer circuit board having low-resistance conductor wiring having a resistivity of not more than 5 μΩ-cm between layers formed by laminating insulating materials, and having a film-like passive element arranged in a surface layer portion. 2. A multilayer circuit board, wherein a heat resistant surface layer portion is formed on the entire surface of the substrate or at least a portion where the filmy passive element is arranged.
【請求項2】 前記膜状受動素子が、膜状抵抗体である
ことを特徴とする請求項1記載の多層回路基板。
2. The multilayer circuit board according to claim 1, wherein the film-shaped passive element is a film-shaped resistor.
【請求項3】 前記耐熱性表層部が、アルミナを主成分
として構成されていることを特徴とする請求項1記載の
多層回路基板。
3. The multilayer circuit board according to claim 1, wherein the heat-resistant surface layer portion is composed mainly of alumina.
【請求項4】 前記絶縁性材料は、組成中に含まれるア
ルミナの占める体積分率が、内層部では最大でも40%
であり、表層部では少なくとも50%であることを特徴
とする請求項1記載の多層回路基板。
4. The volume fraction of alumina contained in the composition of the insulating material is 40% at maximum in the inner layer portion.
The multilayer circuit board according to claim 1, wherein the surface layer portion is at least 50%.
【請求項5】 前記低抵抗性導体配線が、Au、Ag、
Cu、Pt、Pdのうちの少なくとも一つによって形成
されていることを特徴とする請求項1記載の多層回路基
板。
5. The low resistance conductor wiring is made of Au, Ag,
The multilayer circuit board according to claim 1, which is formed of at least one of Cu, Pt, and Pd.
【請求項6】 前記耐熱性表層部と内層部の多層回路を
構成する絶縁性材料との境界領域には、両層を構成する
組成の混合した組成濃度勾配層を設けることを特徴とす
る請求項1記載の多層回路基板。
6. A composition concentration gradient layer, which is a mixture of the constituents of both layers, is provided in a boundary region between the heat resistant surface layer portion and the insulating material constituting the multilayer circuit of the inner layer portion. Item 1. The multilayer circuit board according to item 1.
【請求項7】 前記膜状受動素子は、少なくとも1つの
容量素子を含むことを特徴とする請求項1記載の多層回
路基板。
7. The multilayer circuit board according to claim 1, wherein the film-shaped passive element includes at least one capacitive element.
【請求項8】 絶縁性材料を積層して構成された層間
に、抵抗率5μΩ−cmを超えない低抵抗性導体配線を
有し、かつ表層部に膜状受動素子が配置された多層回路
基板の製法において、低抵抗性の導体配線を含む内層の
絶縁性材料の積層体を形成する工程、該積層体の表面の
全面又は局部に耐熱性表層部を形成する工程、該形成し
た耐熱性表層部の少なくとも一部が重なりあう位置に膜
状受動素子を形成する工程、該膜状受動素子の電気的特
性をレーザービームによるトリミング工程によって調節
することを特徴とする多層回路基板の製法。
8. A multi-layer circuit board having a low resistance conductor wiring having a resistivity of not more than 5 μΩ-cm between the layers formed by laminating insulating materials, and having a film-like passive element arranged in the surface layer portion. In the manufacturing method of, a step of forming a laminated body of an insulating material of an inner layer including a low resistance conductor wiring, a step of forming a heat resistant surface layer portion on the entire surface or a local portion of the laminated body, and the formed heat resistant surface layer A method of manufacturing a multilayer circuit board, comprising: forming a film-like passive element at a position where at least a part of each part overlaps with each other; and adjusting electrical characteristics of the film-like passive element by a trimming step using a laser beam.
【請求項9】 請求項1〜7のいずれか1項記載の多層
回路基板を構成部材として含むことを特徴とするカメラ
一体型ビデオ装置。
9. A video device integrated with a camera, comprising the multilayer circuit board according to claim 1 as a constituent member.
【請求項10】 請求項1〜7のいずれか1項記載の多
層回路基板を構成部材として含むことを特徴とする通信
用電子機器。
10. A communication electronic device comprising the multilayer circuit board according to claim 1 as a constituent member.
JP4250371A 1992-08-27 1992-08-27 Multilayered circuit board and manufacture thereof Pending JPH0677665A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4250371A JPH0677665A (en) 1992-08-27 1992-08-27 Multilayered circuit board and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4250371A JPH0677665A (en) 1992-08-27 1992-08-27 Multilayered circuit board and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH0677665A true JPH0677665A (en) 1994-03-18

Family

ID=17206930

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4250371A Pending JPH0677665A (en) 1992-08-27 1992-08-27 Multilayered circuit board and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH0677665A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003032386A1 (en) * 2001-10-05 2003-04-17 Sony Corporation High-frequency module board device
US7105911B2 (en) 2002-10-16 2006-09-12 Hitachi, Ltd. Multilayer electronic substrate, and the method of manufacturing multilayer electronic substrate

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003032386A1 (en) * 2001-10-05 2003-04-17 Sony Corporation High-frequency module board device
US6889155B2 (en) 2001-10-05 2005-05-03 Sony Corporation High frequency module board device
US7366629B2 (en) 2001-10-05 2008-04-29 Sony Corporation High frequency module board device
US7105911B2 (en) 2002-10-16 2006-09-12 Hitachi, Ltd. Multilayer electronic substrate, and the method of manufacturing multilayer electronic substrate

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