JPH0673369B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention provides a structure of a semiconductor device suitable for a highly integrated dynamic semiconductor random access memory. Particularly, the present invention provides a structure suitable for a one-transistor type memory cell including a capacitor and a transfer gate.

(Prior Art) Conventionally, the structure of a memory cell of a dynamic semiconductor random access memory is generally that shown in FIG. FIG. 2 shows a cross-sectional view of a conventional one-transistor type memory cell (for example, described in "VLSI Data Handbook" Science Forum, P.42-45).

In this structure, a device isolation region 2 made of a thick oxide film, which is selectively provided on a semiconductor substrate 1 of silicon, is formed, and an active region 3 surrounded by the device isolation region is provided. In the active region 3, there is a charge storage gate 4 for storing charges,
It comprises a first polycrystalline electrode 5 and a thin oxide film 6.
The charge storage gate 4 stores information in the memory cell depending on whether charge is stored or not. Adjacent to the storage gate 4,
There is a transfer gate 7, which consists of a second polycrystalline electrode 8 and a thin oxide film 9. Transfer gate 7
Controls the inflow and outflow of charges from the storage gate 4 when reading and writing information. Adjacent to the transfer gate 7 is a bit line 10. This is one in which impurities are diffused to a conductivity type opposite to that of the semiconductor substrate 1, and is formed as an N type diffusion layer with respect to a P type semiconductor substrate. The bit line 10 is connected to the charge storage gate 4 via the transfer gate 7.

Such a semiconductor device is generally manufactured by the following steps. First, a thick oxide film is formed on the semiconductor substrate 1 by the selective oxidation method, and the element isolation region 2 is provided. Next, the thin oxide film 6 is grown by thermal oxidation. Then, polycrystalline silicon is grown and a first polycrystalline electrode is formed by photolithography. Next, a thin oxide film 9 is grown again, polycrystalline silicon is grown, and a second polycrystalline electrode 8 is formed by photolithography. Then, a diffusion region of the bit line 10 is formed by ion implantation or the like in a self-aligned manner by the second polycrystalline electrode and the element isolation region.

(Problems to be Solved by the Invention) In a semiconductor integrated circuit, the integration density is increasing year by year, and a semiconductor memory is required to have a structure of a memory cell which is as compact as possible.

Hitherto, high density of elements has been achieved by so-called scaling such as narrowing an element isolation region or shortening a gate length of a transistor. However, there is a limit to these measures, and we could not expect a dramatic increase in density.

(Means for Solving Problems) According to the present invention, a crystalline insulating film is provided on a semiconductor substrate, the crystalline insulating film is processed by photolithography, and then a single crystal growth layer is formed over the semiconductor substrate and the crystalline insulating film. Is provided, and two layers of polycrystalline electrodes are provided again, and impurities are diffused in a part of the single crystal growth layer to obtain a semiconductive type semiconductor device.

By applying such a structure to a memory cell of a one-transistor type dynamic RAM, the cell size can be greatly reduced.

(Operation) The crystalline insulating film provided on the semiconductor substrate has a lattice constant substantially equal to that of silicon. Therefore, when vapor phase growth of silicon is performed on the semiconductor substrate and the crystalline insulating film, the single crystal layer grows not only on the semiconductor substrate but also on the crystalline insulating film. A compact memory cell can be realized by using this single crystal layer. That is, the semiconductor substrate and the first-layer polycrystalline electrode form a charge storage gate. The adjacent single-crystal layer and the second-layer polycrystalline electrode form a transfer gate. An impurity diffusion region of opposite conductivity type is formed in the single crystal layer adjacent to the transfer gate to form a bit line. By forming part of the bit line and the active region on the crystalline insulating film, the bit line and the transfer gate are partly removed from the active region, thereby making the memory cell compact.

(Embodiment) FIG. 1 is a sectional view of a memory cell according to an embodiment of the present invention.

Reference numeral 1 is a silicon semiconductor substrate. In this embodiment, (10
0) A substrate of P-type silicon single crystal having a crystal axis specific resistance of about 3 Ωcm.

Reference numeral 12 is a crystalline insulating film. This is a single crystal insulating film of magnesia spinel (MgO.Al ₂ O ₃ ) or fluorite (CaF ₂ ), and its thickness is about 0.4 to 0.6 μ. The crystalline insulating film 12 plays the role of the element isolation region 2 in FIG. 2 of the related art, that is, the function of isolation between elements. A P ⁺ channel stopper diffusion layer 11 is provided below the crystalline insulating film 12.

A silicon single crystal growth layer 13 is provided on the crystalline insulating film 12 and the semiconductor substrate 1. The lattice constant of crystalline insulating films such as magnesia spinel and fluorite is very close to that of silicon. Therefore, by epitaxially growing silicon on the crystalline insulating film 12, a single crystal of silicon can be grown on the insulating film 12. It goes without saying that a silicon single crystal layer grows on a single crystal silicon semiconductor substrate by epi growth. The thickness of this single crystal growth layer 13 is preferably about 0.4 to 0.6 μ. A first polycrystalline electrode 5 is provided on the semiconductor substrate 1 with a thin oxide film 6 interposed therebetween. These form the charge storage gate 4. Semiconductor substrate 1 and single crystal growth layer
On top of 13 is a second polycrystalline electrode 8 with a thin oxide film 9 as well. These form the transfer gate 7.

The single crystal growth layer 13 on the crystalline insulating film 12 is provided with an impurity diffusion layer adjacent to the transfer gate 7. This is an N-type impurity diffusion layer because the single crystal growth layer 13 is P-type, and is formed by self-alignment using the second polycrystalline electrode 8 as a mask. This impurity diffusion layer constitutes the bit line 10.

The charge storage gate 4, the transfer gate 7, and the bit line 10 form a memory cell of a one-transistor type dynamic random access memory, as in the case of the prior art shown in FIG. .

The feature of this structure is that the element isolation region 2 is different from the conventional technique.
Is to use the crystalline insulating film 12 instead of, and to form the bit line 10 by forming a single crystal layer on the crystalline insulating film and using a part of this as an impurity diffusion layer of the opposite conductivity type.
That is, the bit line 10 and the insulator for element isolation, and so to speak, have a two-story structure.

Next, an example of a method of manufacturing this structure will be described.

First, a silicon single crystal semiconductor substrate 1 is prepared. This is the same as the conventional technique, and may be an ordinary one used for manufacturing an N-channel type MOS LSI. In this example, a P-type silicon substrate having a (100) crystal axis specific resistance of 3 Ωcm is used.

Next, the channel stopper diffusion layer 11 is formed. This is performed by forming a photoresist into a predetermined pattern with a predetermined mask pattern and using this as a mask material by ion implantation. Ion implantation dose 10 ¹³ / cm ² , voltage 1
Doping boron at 00kV, about. Irradiation range rp = 1000Å
It will be about.

Next, the crystalline insulating film 12 is grown on the semiconductor substrate 1.
As the crystalline insulating film 12, magnesia spinel (MgO
When growing a l ₂ O ₃₎ it is due to the chemical vapor deposition (CVD). That is, the semiconductor substrate 1 is heated to about 1000 ° C.
A mixed gas of ₂ , H ₂ , and N ₂ is flown, and the source is Al, MgCl 2.
_{Use 2} (solid). By these, an insulating single crystal can be grown on a silicon single crystal.

A single crystal of fluorite (CaF ₂ ) can be grown by a vacuum deposition method. That is, the semiconductor substrate 1 is first heated and cleaned at a temperature of about 800 ° C. under an ultrahigh vacuum of 10 ⁻¹⁰ mmHg or less. Next, while heating the semiconductor substrate 1 at a temperature of about 600 ° C., a single crystal of CaF ₂ insulator is grown on the semiconductor substrate 1 by electron beam evaporation or the like.

Next, the crystalline insulating film 12 is processed into a predetermined pattern. This is performed by processing a photoresist into a predetermined pattern and using the mask as a mask to remove an unnecessary portion of the crystalline insulating film 12 by a hydrofluoric acid-based etchant or plasma etching.

Next, epitaxial growth of silicon is performed on the entire surface of the semiconductor substrate 1. This grows a silicon single crystal layer by thermal decomposition of silane (SiH ₄ ) by vapor phase growth or by electron beam evaporation under ultrahigh vacuum. At this time, since the lattice constant is also close to that on the crystalline insulating film 12, the semiconductor substrate 1
A single crystal layer can be grown as above. The thickness of the epitaxial growth layer is 0.4 to 0.6 μ.

Next, the entire surface of the single crystal growth layer 13 is ion-implanted, and impurities are doped to the semiconductor substrate 1 at the same conductivity type and the same concentration. This is ion-implanted at a dose of about 10 ¹² / cm ² and 100
The same concentration distribution as the substrate by heat treatment at 0 ℃ for 3 hours 10 ¹⁶
/ Cm ³ can be obtained.

Next, the single crystal growth layer 13 is processed into a predetermined pattern. An oxide film is formed on the entire surface of the single crystal growth layer, and this is removed by etching into a predetermined pattern. Then, unnecessary portions of the single crystal growth layer 13 are removed by using nitric acid fluoride as a mask.

Next, a thin oxide film 6 is formed and the first polycrystalline electrode 5 is formed to a thickness of 30.
00Å Form. This process is no different from the conventional method.

Next, a thin oxide film 9 is formed, and the thickness of the second polycrystalline electrode 8 is 30
Form 00Å. This step is no different from the conventional method.

Further, a bit line 10 as an impurity diffusion layer is provided by self-alignment using the second polycrystalline electrode 8 as a mask. This is a voltage of 40kV, dose amount by arsenic (As) ion implantation.
It is formed by diffusion at 10 ¹⁶ / cm ² . The diffusion layer has a depth of about 0.2 μm and becomes an N-type conductive layer.

The subsequent steps are exactly the same as the conventional ones. That is, an intermediate insulating film is formed, contact holes are provided, and a vapor deposition wiring layer of aluminum is formed. Then, a semiconductor device is completed by providing a passivation film.

(Effects of the Invention) As described in detail above, the present invention uses a crystalline insulating film instead of the conventional element isolation region, grows a single crystal layer on this, and forms a bit line in a part thereof. It was done. That is, since the bit line has a so-called two-story structure as an insulator for element isolation, the semiconductor memory cell can be compactly formed.

FIG. 3 is a comparison of plan views of the conventional memory cell and the memory cell of the present invention. In FIG. 3 (b), which is a plan view of the cell of the present invention, the area corresponding to the element isolation region 18 is reduced as compared with FIG. 3 (a) which is conventional. The areas of the bit line 15, the first polycrystalline electrode 16, the second polycrystalline electrode 17, etc. are the same as those of the conventional one.

Therefore, the area of the cell whereas the conventional is 6μ × 14μ = 84μ ^2, the cell area of the present invention will become 6μ × 12μ = 72μ ^2. That is, the cell size can be reduced by about 15%.

[Brief description of drawings]

FIG. 1 is a sectional view of a memory cell according to an embodiment of the present invention, and FIG.
FIG. 3 is a sectional view of a conventional memory cell, and FIG. 3 is a plan view of the memory cell. 1 ... semiconductor substrate, 2,18 ... element isolation region, 3 ... active region, 4 ... charge storage gate, 5,16 ... first polycrystalline electrode, 6 ... thin oxide film, 7 ... Transfer gate, 8,17 ... Second polycrystalline electrode, 9 ... Thin oxide film, 1
0,15 …… bit line, 11 …… channel stopper diffusion layer, 12
...... Crystalline insulating film.

Claims (1)

[Claims] 1. A crystalline insulating film formed on a first region of the surface of a first conductivity type semiconductor substrate, and a second region of the surface of the semiconductor substrate adjacent to the first region on the crystalline insulating film. A first conductivity type single crystal layer formed to extend, a second conductivity type diffusion layer formed near the surface of the single crystal layer above the crystalline insulating film, and one end and the other end. A transfer gate portion formed on the surface of the single crystal layer so that the one end is in contact with the second conductivity type diffusion layer, the transfer gate portion being a gate formed on the surface of the single crystal layer. It has a transfer gate part composed of an insulating film and a conductive film formed on the surface of the gate insulating film, and a charge storage gate part formed so as to partially contact the other end of the transfer gate part. Semiconductor device characterized by .