JPH0712058B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular,
It is suitable for application to a device including a transistor having an LDD (Lightly Doped Drain) structure.

[Technical background of the invention and its problems]

Conventionally, there is a memory device shown in FIG. 2 as a memory device including a transistor having an LDD structure.

First, as shown in FIG. 2A, a thermal oxide film (field oxide film) is formed outside the element formation region of the silicon substrate 1 by, for example, a selective oxidation method (LOCOS method) using a silicon nitride film. 2 is grown thick to about 10,000 [Å]. Next, the first gate oxide film 3 is grown on the silicon substrate 1 in the element formation region to about 100 [Å]. Then the first
Over the entire surface with polycrystalline silicon that will become the gate electrode 4 of
After depositing about [Å], N-type impurities are diffused. After this diffusion, the first gate electrode 4 is formed by the photolithography method, and the first gate oxide film 3 is removed by etching using the gate electrode 4 as a mask.

Next, as shown in FIG. 2B, a second gate oxide film 5 is formed on the order of 250 [Å]. At this time, the oxide film 5a is also formed on the first gate electrode 4. Next, after depositing polycrystalline silicon to be the second gate electrode 6 on the entire surface, N-type impurities are diffused, and then the second gate electrode 6 is formed by photoetching.

Next, as shown in FIG. 2C, an N-type impurity such as phosphorus is ion-implanted in an amount of about 1 × 10 ¹³ [cm ⁻² ], and the N
^- forming a diffusion layer 7. After that, CVD (Chemical Vapor
A silicon oxide (hereinafter referred to as CVD-SiO ₂ ) 8 is deposited on the entire surface by a deposition method to a thickness of about 4000 [Å].

Next, as shown in FIG. 2D, RIE (Reactive Ion Et
by etching the CVD-SiO ₂ film 8 by a ching method to introduce a high-concentration diffusion layer on the side wall 9 of the second gate electrode 6.
Forming a residual layer 8 'by CVD-SiO ₂ film 8. Then CV
The D-SiO ₂ film 8, the remaining layer 8 ′ and the gate electrode 6 are used as a mask for N
Arsenic, which is a type impurity, is ion-implanted at about 5 × 10 ¹⁵ [cm ⁻² ] to form an N ⁺ diffusion layer 10. The N ⁺ diffusion layer 10 and the N ⁻ diffusion layer 7 described above form a source and a drain.

Finally, as shown in FIG. 2 (e), the CVD-SiO ₂ film is again formed.
After depositing 11 on the entire surface, a contact hole 12 is formed. Further, aluminum is vapor-deposited on the entire surface, and then aluminum wiring 13 is formed by photo-etching to complete the memory device.

However, in the conventional memory device, the gate electrode 6
RI to the side wall 9 of forming a residual layer 8 'by CVD-SiO ₂ film 8
In step E (FIG. 2 (d)), the surface of the region serving as the source and drain of the transistor is easily damaged by ion collision. Since the damaged layer is not completely removed and remains in the subsequent steps, a leak current due to the damaged layer occurs. When such a leak current occurs, there is a drawback in that the electric charge in the memory cell portion of the dynamic memory is lost, which deteriorates the retention characteristic. In addition to the dynamic memory, in a device that handles a small amount of current, the leak current has an important influence on the characteristics of the device, and thus the yield is low.

[Object of the Invention]

The present invention has been made in order to overcome the above-mentioned drawbacks of the prior art, and an object of the present invention is to provide a semiconductor device which can have good holding characteristics and a manufacturing method thereof.

〔The invention's effect〕

In order to achieve the above object, the present invention provides a MOSFET that constitutes a transistor group in a portion where leakage current prevention is not particularly required, such as a peripheral circuit, and a gate electrode having a mask layer formed on a side wall and the gate electrode and the mask layer. A high-concentration impurity diffusion layer formed by ion-implanting impurities with the mask as a mask, and a low-concentration impurity diffusion layer of the same conductivity type that is in contact with the high-concentration impurity layer and is formed by ion-implanting impurities with the gate electrode as a mask. And a first source / drain made up of, and forming a transistor group in a portion where leakage current prevention is required, such as a memory cell portion and a sense amplifier portion, a MOSFET has a gate electrode not formed with a mask layer on its side wall. A semiconductor having a second source / drain composed of a low-concentration impurity layer formed by ion-implanting impurities using the gate electrode as a mask There is provided a location and a manufacturing method thereof.

Example of Invention

Hereinafter, a semiconductor device and a method of manufacturing the same according to an embodiment will be described in detail with reference to FIG. 1 of the accompanying drawings. In the description of the drawings, the same elements will be denoted by the same reference symbols.

The completed state of this semiconductor device is as shown in FIG. That is, the transistors (first transistor group) in the peripheral circuit section 20 other than the memory cells for which the leak current prevention is not particularly required have the same structure as the conventional device, but the memory cell section 30 for which the leak current prevention is particularly required is performed. In the transistor (first transistor group) in, the source and drain are formed only by the N ⁻ diffusion layer 7, and the second gate electrode 6 is entirely covered with the CVD-SiO ₂ film 8. In such a semiconductor device, since the RIE process is not applied to the memory cell portion 30 in the manufacturing process, the retention characteristic of the memory cell is not deteriorated due to the damaged layer generated by the RIE process. Therefore, good retention characteristics can be exhibited, and the yield can be improved.

Such a semiconductor device is manufactured by the following steps. Note 1 (a), as shown in (b), LDD of N ^-
Each process until the diffusion layer 7 is formed by ion implantation is
Since it is similar to the conventional semiconductor device shown in FIG. 2, its description is omitted.

After forming the N ⁻ diffusion layer 7, as shown in FIG. 1 (c).
A CVD-SiO ₂ film 8 is deposited on the entire surface. Next, a resist pattern 14 is formed only on the memory cell portion 30 by photolithography,
The peripheral circuit section 20 is left in a state where the CVD-SiO ₂ film 8 is exposed.

Next, as shown in FIG. 1 (d), the exposed CVD-Si
The O ₂ film 8 is etched by the RIE method to form a residual layer 8 ′ for forming an N ⁺ diffusion layer on the side wall 9 of the gate electrode 6 of the peripheral circuit section 20. Next, the resist pattern 14 is removed,
Further, arsenic, which is the N-type impurity, is ion-implanted at about 5 × 10 ¹⁵ [cm ⁻² ] to form the N ⁺ diffusion layer 10. Therefore, the source and drain of the transistor in the peripheral circuit section 20 are
It is formed of an N ⁻ diffusion layer 7 and an N ⁺ diffusion layer 10. On the other hand, the source and drain of the transistor in the memory cell section 30 are formed only by the N ⁻ diffusion layer 7.

Next, as shown in FIG. 1 (e), a CVD-SiO ₂ film 11 is deposited again on the entire surface, and then a contact hole 12 is formed. Then, aluminum is vapor-deposited and aluminum wiring 13 is formed by a photo-etching method to complete the semiconductor device.

According to the method of manufacturing a semiconductor device as described above, since the memory cell section 30 can be configured by the transistor that is not damaged by RIE, the semiconductor device can exhibit good holding characteristics.

Needless to say, the present invention is not limited to the above embodiments. For example, in the above-described embodiment, only the transistor in the memory cell section 30 has the drain and the source formed of the diffusion layer 7 containing the low concentration impurity, but the transistor of the sense amplifier circuit section has the low concentration of the drain and the source. The diffusion layer 7 containing impurities may be formed, and the same effect as described above can be obtained.

Moreover, it is not limited to the dynamic memory device (D-RAM),
It can be widely applied to logic devices including dynamic memory cells and memories. Further, it can be applied to a device having a static memory cell or a device in which inverters are connected in multiple stages in series. In other words, it can be widely applied to a semiconductor device including a circuit portion that operates with a minute current and is required to hold charges for a certain time.

〔The invention's effect〕

As described above, according to the present invention, a MOSFET forming a transistor group in a circuit portion (for example, a memory cell portion) where leakage current prevention is desired does not have a mask layer on the side wall of a gate electrode and has a low source / drain. Since the structure is composed of only the high concentration impurity layer, the deposition process of the CVD-SiO ₂ film and the etching process by the RIE method necessary for forming the diffusion layer containing the high concentration impurity become irrelevant to the memory cell part, and therefore the memory Damage layer due to RIE is not formed in the cell part,
Therefore, it is possible to obtain a semiconductor device having good holding characteristics and a method for manufacturing the same. As a result, the yield can be significantly improved.

[Brief description of drawings]

FIG. 1 is a sectional view showing a semiconductor device and a manufacturing process thereof according to an embodiment of the present invention, and FIG. 2 is a sectional view showing a conventional semiconductor device and a manufacturing process thereof. 1 ... Substrate, 2 ... Field oxide film, 3,5,5a ... Gate oxide film, 4,6 ... Gate electrode, 7 ... N ^- diffusion layer, 8,11
...... Silicon oxide film, 8 '... Remaining layer, 9 ... Side wall, 10
...... N ⁺ diffusion layer, 13 ...... Aluminum wiring, 14 ...... Resist pattern, 20 ...... Peripheral circuit section, 30 ...... Memory cell section.

Claims (5)

[Claims] 1. A semiconductor device including a first transistor group that does not particularly need to prevent charge leakage and a second transistor group that needs to prevent charge leakage, wherein a first transistor group that constitutes the first transistor group is provided. The MOSFET includes a gate electrode having a mask layer formed on its sidewall, a high-concentration impurity diffusion layer formed by ion-implanting impurities with the gate electrode and the mask layer as a mask, and a gate electrode contacting the high-concentration impurity layer and the gate. A second MOSFET that forms a second transistor group, having a first source / drain composed of a low-concentration impurity diffusion layer of the same conductivity type formed by ion-implanting impurities using the electrode as a mask, A second source / electrode is formed of a gate electrode not having the mask layer formed on its side wall and a low-concentration impurity layer formed by ion-implanting impurities using the gate electrode as a mask. Wherein a and a rain. 2. The semiconductor device according to claim 1, wherein the second transistor group constitutes a memory cell section. 3. The semiconductor device according to claim 1, wherein the second transistor group constitutes a sense amplifier section. 4. A method of manufacturing a semiconductor device, comprising: a first transistor group that does not particularly need to prevent charge leakage; and a second transistor group that needs to prevent charge leakage. First step of forming gate electrodes of the respective transistors forming the transistor group, and forming a low-concentration impurity diffusion layer by using the gate electrodes as a mask, and forming a low concentration impurity diffusion layer in the regions of the first and second transistor groups. Second step of forming the second mask layer, and a third step of forming the second mask layer in the region of the second transistor group.
And the first mask using the second mask layer as a mask.
Etching the mask layer to leave the first mask layer only on the side wall of the gate electrode of each of the transistors forming the first transistor group, and leaving the gate electrode and the side wall of the gate electrode on the side wall of the gate electrode. And a fifth step of forming a high concentration impurity diffusion layer of the same conductivity type as the low concentration impurity diffusion layer using the first mask layer and the second mask layer as a mask. Production method. 5. The etching in the fourth step is RIE.
5. The method for manufacturing a semiconductor device according to claim 4, wherein the method is etching by a method.