JPH0666655B2 - ECL integrated circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an ECL (Emitter Coupled Logic) integrated circuit, and more particularly to a set, a latch with reset, and a master / slave flip with set, which are configured by ECL.・ Regarding the flop.

[Conventional technology]

The master slice method is often used when designing a logic circuit with ECL. In this device, cells are arranged in an array in a chip, and a plurality of transistors, resistors, etc. are prepared in one cell. Then, the logic circuit is formed by wiring the transistors and the resistors. At this time, the logic amplitude inside the LSI is about 600 mV, and the first reference voltage VR ₁ is located at the intermediate level between the “H” level and the “L” level of the internal logic output. Here, a series gate circuit is often used as a means for speeding up ECL, and a latch, flip,
The flop is well known. As a conventional circuit example, FIG. 4 shows a latch, and FIG. 5 shows a master-slave flip-flop. [Reference: The Semiconductor Data
Library MECL Integrated Circuit (THE SEMICONDUCTOR DATA LIBRARY MECL INTEGRA
TED CIRCUITS) 1974 3-75 Motorola, MECL Integrated Circuit Data Book (MECL IN
TEGRATED CIRCUITS DATA BOOK Third Edition) 19
1973 3-85 Motorola] Both of these have reset inputs. In Fig. 4, transistor Q ₇ , resistors R ₈ , R ₉ and 5
In the figure, the reset function is realized by inserting transistors Q ₁₄ , Q ₁₈ , Q ₂₄ and resistors R _{21 to} R ₂₄ . The second reference voltage VR ₂ is lower than the first reference voltage VR ₁ by the base-emitter forward voltage (V _BE ) of the transistor.

Next, the operation of the circuit shown in FIG. 4 will be described. Now
The CLOCK input signal is "H" that is, the signal input through the transistor Q _8, turns on the transistor Q ₉ constituting a clock circuit including a constant current source 3, the transistor Q ₁₀ in a state of being in an off state, further RESET at the time of the input signal is "L", the base of the transistor Q ₃ is "H", if the base of the transistor Q ₄ is "L", the output Q and output emitter of the transistor Q ₁₁ "H", and the transistor Q ₁₂
The output with the emitter of is as "L". Here RESET input signal changes to "H", the output Q base potential rises of the transistor Q ₇ than the base potential of the transistor Q _3, it is inverted. Here, an output having the same circuit configuration as the output Q in the LSI is applied to the base potential of the transistor Q ₇ , that is, the RESET input signal. Therefore, in order for the RESET function to operate normally, the transistor Q
The potential at the “H” level of the base of ₃ is the “H” level of the RESET input signal.
Must be lower and resistor R ₉ is inserted to reduce the base potential of transistor Q ₃ . When the SET input circuit is present, the resistor R ₈ has the same effect. In addition,
The data input signal in the stationary state is input to the base of the transistor Q ₁ .

In FIG. 5, resistors R ₂₂ and R ₂₃ are resistors R _{9 in} FIG.
And the resistors R ₂₁ and R ₂₄ correspond to the resistor R ₈ in FIG. 4 and perform the same operation.

[Problems to be solved by the invention]

However, there are the following drawbacks in realizing the conventional reset or set-equipped latches and flip-flops described above in an LSI by the master slice method.

The resistors R ₈ , R ₉ , and R _{21 to} R ₂₄ are indispensable in the conventional circuit for configuring the reset, the latch with the set function, and the flip-flop, and the logical operation is performed by using the potential difference generated between both ends of these resistors. It has gained. However, the above resistance requires a very small value as compared with other resistances, and is required to have a relative accuracy with other resistances. In order to satisfy this condition, the area required for the resistance type cannot be ignored, and the cell size and eventually the chip area are increased. Further, the above resistor has the following problems in circuit operation. For example, the potential difference across the resistor R ₉ , in other words, the current flowing through the resistor R ₉ needs to be constant in terms of circuit operation. Even if the ratio accuracy of the resistors R ₉ and R ₆ is maintained, fluctuations in the power supply voltage of the low-potential side power supply 2,
And In conjunction with variations in the base current of the transistor Q ₃ resistor R ₉
The current flowing through the gate also fluctuates. That is, the potential difference between both ends of the resistor R ₉ is greatly influenced by the power source fluctuation of the power source 2 and the h _FE fluctuation of the transistor Q ₃ in addition to the ratio accuracy with the resistor R ₆ . The same applies to the other resistors R ₈ and R _{21 to} R ₂₄ , and there was a problem in ensuring stable operation.

The present invention has been made in view of such drawbacks of the conventional circuit, and a Schottky barrier diode is used in place of the resistor in place of the resistor inserted in the conventional set / reset latch and flip-flop. By inserting it, it is possible to provide an ECL integrated circuit that reduces the cell size and, in turn, the chip area, has little effect on fluctuations in the power supply voltage and h _FE of the transistor, and operates stably. It has original content.

[Means for solving problems]

The ECL integrated circuit according to the present invention includes first and second transistors having emitters commonly connected, third and fourth transistors having emitters commonly connected, collectors of the first transistor, and the first transistor. A fifth transistor having a base connected to the collector of the third transistor and an emitter connected to the base of the fourth transistor; a collector connected to the second transistor; and a base connected to the collector of the fourth transistor; A third transistor having an emitter connected to the base of the third transistor and a first load resistor having one connected to each of the collectors of the first and third transistors and the other connected to a high-potential side power supply terminal; One is connected to each of the collectors of the second and fourth transistors, and A latch circuit having a second load resistor having the other connected to a terminal, and complementary outputs of the clock signal respectively having emitters of the first and second transistors and emitters of the third and fourth transistors. And a clock circuit connected to each of the third and fourth transistors, an emitter is connected to each of the emitters of the third and fourth transistors, and a collector is connected to each of the collectors of the second or fourth transistors to output the output of the latch circuit. An ECL including a flip-flop circuit having a seventh transistor for receiving a set (reset) input signal forcibly set (reset)
In the integrated circuit, a first Schottky barrier is connected to a series circuit including the first resistor, the base of the fifth transistor and the emitter of the fifth transistor.
A diode is inserted in series, and the second resistor and the sixth resistor are connected.
The second Schottky barrier diode is inserted in series in the series circuit including the base of the transistor and the emitter of the sixth transistor.

In the ECL integrated circuit of the present invention, the first Schottky barrier diode is inserted between the emitter of the fifth transistor and the base of the fourth transistor, and the second Schottky barrier diode is inserted. A barrier diode may be inserted between the emitter of the sixth transistor and the base of the third transistor. Furthermore, the ECL integrated circuit of the present invention is the first
A Schottky barrier diode is inserted between the base of the fifth transistor and the first load resistor, and the second Schottky barrier diode is connected to the base of the sixth transistor and the sixth load transistor. It may be configured to be inserted between two load resistors.

〔Example〕

 The present invention will be described below with reference to the drawings.

FIG. 1 is a circuit connection diagram showing an embodiment of an ECL integrated circuit to which the present invention is applied. While the resistors R ₈ and R ₉ are inserted and connected in the conventional circuit shown in FIG. 4, the Schottky barrier diodes D ₁ and D ₂ are inserted and connected in this embodiment as shown in the figure.

The operation of the ECL integrated circuit of the embodiment of the present invention shown in FIG. 1 is basically the same as that of the conventional circuit shown in FIG.
The functions of the Schottky barrier diodes D ₁ and D ₂ are the same as those of the resistors R ₈ and R ₉ . That is, the potential at "H" of the base of the transistor Q ₃ is "H" of the RESET input signal by the potential difference between both ends of the Schottky barrier diode D _2.
Will be lower. Forward voltage V _F of this time Schottky barrier diode is about 300 mV, if the logical amplitude of the LSI and 600 mV, based "H" level of the transistor Q ₃ are approximately the first reference voltage VR _Since it is equal to ₁ , the RESET function operates normally.

As described above, the potential difference across the resistor R _{9 in} FIG. 4 is greatly affected by the relative accuracy with the resistor R ₆ , the power source fluctuation of the power source 2 and the base current fluctuation of the transistor Q ₃ , but the shot in this embodiment. Key barrier diode D ₂
Then, the effect of these fluctuations is extremely small. This is because even if the current flowing through the Schottky barrier diode D ₂ increases 1.5 times due to the above fluctuation, the potential difference across the Schottky barrier diode D ₂ is 10 mV.
Only increase. Therefore, a stable circuit operation can be obtained even with the above fluctuation. Furthermore, since the Schottky barrier diode D ₂ can reduce the element area with respect to the resistor R _{9 in} FIG. 4, the cell size and the chip area can be reduced. To realize the SET function, a transistor corresponding to the transistor Q ₇ may be connected in parallel with the transistor Q ₃ .

FIG. 2 is a circuit connection diagram showing a second embodiment of the present invention. The Schottky barrier diode D ₂ is inserted between the base of the transistor Q ₆ and the resistor R _{2 as} shown in the figure, and the Schottky barrier diode D ₁ is inserted between the base of the transistor Q ₅ and the resistor R _{1 as} shown in the figure. Has been inserted. FIG. 2 shows a latch with reset as in FIG. The current flowing through the resistor R ₂ is the same as the current flowing through the resistor R ₂ of Figure 1, a Schottky barrier diode D ₂ will be lowered base potential of the transistor Q _3. Schottky barrier diode D _{1 for} latch with set
Lowers the base potential of transistor Q ₄ .

Figure 3 is a circuit connection diagram showing a third embodiment of the present invention, Schottky barrier diode D ₃ to D ₆ in place of the resistor R ₂₁ to R ₂₄ in FIG. 5 is inserted.

Regarding the functions and effects of the Schottky barrier diode inserted in the embodiments of FIGS. 2 and 3,
It is the same as the embodiment shown in FIG.

〔The invention's effect〕

As described above, according to the present invention, by inserting a Schottky barrier diode instead of the resistor in the conventional resistor inserted in the set / reset latch and the flip-flop, the cell size, and by extension, the The chip area can be reduced, and there is little effect on fluctuations in the power supply voltage and the h _FE of the transistor, and there is an effect that an ECL integrated circuit that operates stably can be provided.

[Brief description of drawings]

FIG. 1 is a circuit connection diagram of a latch circuit showing an embodiment of an ECL integrated circuit according to the present invention, FIG. 2 is a circuit connection diagram of a latch circuit showing another embodiment of the present invention, and FIG. Circuit connection diagram of a flip-flop circuit showing another embodiment of
FIG. 4 is a circuit connection diagram of a conventional latch circuit, and FIG. 5 is a circuit connection diagram of a conventional flip-flop circuit. In the figure, 1 ... High-side power supply V _CC , 2 ... Low-side power supply V _EE ,
3 ... Constant current source, CLOCK ... Clock input terminal, DATA ...
… Data input terminal, RESET …… Reset input terminal, Q,
...... Output, Q _{1 to} Q ₃₄ …… Transistor, R _{1 to} R ₂₄ …… Resistance, D _{1 to} D ₆ …… Schottky barrier diode,
_VR1 ... 1st reference voltage, _VR2 ... 2nd reference voltage.

Claims (3)

[Claims] 1. A first and a second emitter whose emitters are commonly connected.
Of the third and fourth transistors whose emitters are commonly connected to the collectors of the first transistor and the bases of the collectors of the third transistor and the emitters of the bases of the fourth transistor. A fifth transistor and a sixth transistor having bases connected to collectors of the second transistor and collector of the fourth transistor and emitters connected to bases of the third transistor and the first transistor, respectively. And a first load resistor, one of which is connected to each of the collectors of the third transistor and the other of which is connected to the high potential side power supply terminal, and one of which is connected to each of the collectors of the second and fourth transistors, the high potential side A latch circuit having a second load resistor having the other connected to a power supply terminal; A clock circuit connected to the emitters of each respective complementary output of the clock signal of the emitter of said first and second transistors and said third and fourth transistors, the third
And a set input for forcibly setting (resetting) the output of the latch circuit by connecting the emitter to the emitter of the fourth transistor and connecting the collector to the collector of the second or fourth transistor, respectively. In a ECL integrated circuit including a flip-flop circuit having a seventh transistor for receiving a signal at its base, a series circuit including a first load resistor, a base of the fifth transistor and an emitter of the fifth transistor is provided. A first Schottky barrier diode is inserted in series, and a second Schottky barrier diode is provided in a series circuit including the second load resistor, the base of the sixth transistor and the emitter of the sixth transistor. ECL characterized by inserting diodes in series
Integrated circuit. 2. The first Schottky barrier diode is connected to the emitter of the fifth transistor and the fourth Schottky barrier diode.
The second Schottky barrier diode is inserted between the base of the transistor and the second Schottky barrier diode between the emitter of the sixth transistor and the base of the third transistor. The ECL integrated circuit according to claim 1. 3. The first Schottky barrier diode is inserted between the base of the fifth transistor and the first load resistor, and the second Schottky barrier diode is inserted into the second Schottky barrier diode. The ECL integrated circuit according to claim 1, wherein the ECL integrated circuit is inserted between the base of the transistor No. 6 and the second load resistor.