CA1208308A - Schottky shunt integrated injection logic circuit - Google Patents

Abstract

SCHOTTKY SHUNT INTEGRATED INJECTION LOGIC CIRCUIT
James M. Early ABSTRACT

An improved integrated injection logic structure utilizes a current mirror in conjunction with each switching transistor (M1, M2) of the integrated injection logic circuit of this invention by connecting one of a plurality of collectors (O0, P0) of the switching tran-sistor to the base of said switching transistor. In this manner, the current flowing through conducting switching transistors is limited by the current mirror. This limited current flow through conducting switching transistors, as well as the use of voltage pull up means (D1, D2) connected to the collectors of the switching transistors prevents the saturation of conducting switching transistors. This results in an increase in the voltage on the collectors of conducting switching transistors and a decrease in the voltage swing between a logical one and a logical zero, thereby substantially increasing the speed of the integrated injection logic circuit of this invention as compared to prior art integrated injection logic circuits. The voltage pull up means connected to the collectors of the switching transistors may comprise resistors or preferably forward biased Schottky diodes connected between a voltage source (Vdd) and the collectors of the switching transistors.
This invention is also suitable for use in MOS circuit.

Description

SCEIOTTKX STUNT INTEGRATED INJECTION LOGIC CIRCUIT

2 James M. Early 4 ~9 6 Field of 'che Invention 8 This inve~tlon relates to integrated circuit structures 9 and specifically to an integrated inj ection logic circuit utilizing Schottky diode to limit the signal swing for 11 logic voltages, thus preventing saturation of the tran-l sistors forming the integrated injection logic circuit and 13 whereby resulting in an integrated injection logic circuit 14 having increased switching speeds over prior art circuits.
16 Descri tion of the Prior Art ~7 ~8 Circuits and structures utilizing integrated injection ~9 logic (I2L) are well known in the prior art. I L structures are particularly suited for the formation of logic gates 21 of a type wherein each gate comprises a pair of merged 22 complementary transistors. In such a gate, a PNP injector 23 transistor is typically used as a current source or 24 supplying current to the base o an NPN switching transistor.
The NPN transistor often has multiple collectors which may 26 be used to drive a plurality of other loyic elements.
27 Integrated injection logic circuit are compact, operate 28 at very low voltages, and can be fabricated easily end 29 inexpensively utilizing relatively few masking steps.

3~
3~ Integrated injection logic circuits and structures 32 have been described in various patents and technical 33 articles. See, for example, an article by H. I. Burger 34 and 5. K. Weidm n entitled "Merged Transistor Logic (MTL) -a Low-Cost Bipolar Logic Concept" and an article by K.
36 Hart and A. Slob entitled "Integrated Injection Logic: A
37 New Approach Jo LSI", both in the journal of 501id-State 38 Circuits, Volume SC-7, No. 5, October 1972 at pages 340-346 ~2~

and pages 346-351, respectively; U.S. patent number 4,286,177 issued August 25, 1981 to Hart and Slob; see also the article by H.H. verger and S.K. Wiedmann, "The Bipolar Oxide Break-through", Parts 1 and 2, Electronics, September 4, 1975, pages 89-95 and October 2, 1975, pages 99~103, respectively; and the article by T. Poorter entitled "Electrical Parameters, Static and Dynamic Response of I L", IEEE Journal of Solid-State Circuits, Vol. SC-12, No. 5, October 1977, pages 440-449; and U.S. Patent No. 3,993,513 entitled "Combined Method for Fabricating Oxide -Isolated Bipolar Transistors and Complementary Oxide - Isolated Lateral Bipolar Transistors and the Resulting Structures", assigned to Fairchild Camera and Instrument Corporation, the assignee of this application. A multiple collector structure for bipolar transistors is described in U.S. Patent No. 4,084,174 entitled "Graduated Multiple Collector Structure for Inverted Vertical Bipolar Transistors" of Crippen, Hingarh and Verhofstadt and also assigned to Fairchild Camera and Instrument Corporation.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 is a schematic diagram of a prior art inte-grated injection logic circuit;
Figure 2 is a schematic diagram of an integrated injection logic circuit constructed in accordance with this invention;
Figure 3 is a graphical representation of the relation-ships between the voltage and current characteristics of one output collector of a switching transistor such as Ml or M2 of the integrated injection logic circuit of Figure 2;

.~. - 2 -33~

Figure 4 is a schematic diagram of a eireuit for providing a voltage Vdd to the Schottky diodes utilized in the eircuit of Figure 2; and Figure 5 i5 a schematic diagram of a circuit con-structed in aceordanee with this invention which utilizes metal-oxide-silicon transistors.
Figure 1 shows a schematic diagram of a portion of a typieal prior art integrated injeetion logie eireui-t. PNP
injector transistor Tl serves as a eurrent souree, providing eurrent to the base of NPN switehing transistor Ml. The emitter of transistor Tl is conneeted to a positive voltage souree VEE, the base of injeetor transistor Tl is connected to ground (VGG), and the collector of transistor Tl is eonneeted to input terminal 11, which is used for receiving an input signal Vin. The colleetor of transistor Tl is also eonneeted to the base of switehing transistor Ml. The emitter of transistor Ml is eonnected to ground (VGG), and transistor Ml eontains a plurality of collectors OO through O3. Eaeh eollector OO
through O3 of transistor Ml may be connected to an input lead of another integrated injection logic gate, or may be left floating.
For purposes - 2a -~2~ 8 -3~
L of this specification, collectors 00 through 2 are shown 2 floating, and only collector 03 of transistor Ml is shown 3 connected to a subsequent integrat:ed injection logic gate.
PNP injector transistor T2 and NPN switching transistor 6 ~2 comprise the second integrated inject~.on logic gate of 7 the circuit of Figure l. The emitter of PNP transistor T2 8 is connected to a voltage source VEE and the base of 9 transistor T2 is connected to ground V~&. The collector of trans1stor T2 is connected to collector 03 of transistor 11 Ml, thus receiving as an input signal the output signal ~2 provided by collector 03 of transistor Ml. The collector 13 of translstor T2 is also connected to the base of switching 14 transistor M2. The emitter of NPN switching transistor M2 is connected to ground. The collectors PO through P3 of 16 transistor M2 provide a plurality of open collector outputs 17 for connection to further logic gates or other circuitry 18 if desired.

The operation of the prior art integrated injection 21 logic circuit of Figure 1 i5 as follows. positive 22 voItage VEE is applied to the Pmitter of transistor Tl.
23 The base of transistor Tl and the emitter of transistor M
24 are connected to ground. The emitter-base jun tion of transistor Tl is forward biased, thus turning transistor 26 Tl on. Thus, transistor Tl supplies current from its 27 emitter connected to VEE to its collector connected to the 28 base of switching transistor Ml.

In actual operation, tenminal ll will not be floating 3~ but rather will receive a signal Vin which will be either 32 a logical one (effectively an open circult, resulting in a 33 high voltage on node Nl, typically 0~7 volts,) or logical 34 zero effectively a short circuit, thus sinking the current made available at node Nl by the collector of injector 36 txansistor Tl, resulting in a low voltage on node Nl, 37 typically 0.1 volts). With a logical one applied to ;4 1 ~ermi~al ll, current is no drawn from the collector of T
2 to terminal ll. Thus the inj ctor current made available 3 by the collector of -injector transistor Tl is applied to

4 the base and to the base~emitter lunctlon of NPN transistor Ml, whereby turning on transistor Ml. Thus, transistor M
6 conducts when a logical or.e is applied to input terminal 7 ll.

9 On the other hand, with a logical zero applied to input terminal ll, current will be drawn from the collector 11 of injector transistor Tl to terminzl lll thus depx~ving l transistor Ml of substanti lly all of the current supplied 13 by injector transistor Tl. With the injector current from 14 the collector of transistor Tl slunk by the logical zero applied to input terminal ll, no current is availahle to 16 forward bias the base-emitter junction of NPN transistor 17 Ml, thereby causing transistor Ml to remain off. Thus, 18 transistor Ml does not conduct when a logical zero is 19 applied to input terminal 11.
21 PNP injector transistor T2 operates in a manner 22 similar to injector transistor T1. A positive voltage VEE
23 is applied to the emitter of transistor T2, and its base 24 is connected to ground (VG&). Thus, the emitter-base junction of transistor T2 is forward biased thus turning 26 transistor T2 on. With transistor Ml conducting (logical 27 one on input terminal 11~, the current availakle from the 28 collector of injector transistor T2 is sunk through collector 29 03 of transistor Ml to ground (logical 2ero on node N2), thus depriving transistor ~2 of base current, thereby 31 maintaining transistor M2 off. On the other hand, with 32 tr~nsi~tor Ml off (logical zero on input terminal 11), 33 injector current supplied by transistor T2 is not sunk by 34 collector 03 of transistor Ml, but rather provides the base current to transistor M2. This base current flows 36 from the base to the emitter of transistor M2~ thus turning ~8 0~

-5 transistor M2 on.
3 In this manner, the cixcuit of Figure 1 allows a 4 single input signal Vin to generat:e a plurality of output 5 signals to be applied to vaxious gates and circuits as I-

6 desired. For example, input si~lal Vin provides four

7 inverted signals on open collectors 00 through 03 which

8 are applied to other circuits as desired. Furthenmore, -I

9 the inverted input signal available on collector 03 of transistor Ml is used to generate four non-in~erted open 11 collectox signals on collectors P0 through P3 of transistor 12 M2. The fact that switching transistors Ml and M2 each -13 are shown with a plurality of four collectors serves as an 14 example only, and it is not be interpreted that the 15 switching transistors utilized in accordance with this I--16 invention must contain four.collectors. In fact, a greater 17 or lesser number of collectors may be utilized in accordance 18 with well known semiconductor principles. However, as the 19 number of collectors is increased, the capacitance of the 20 device increases, thereby decreasing the switching speed ::
21 of the circuit.

23 Fuxthermore, it is well known that a plurality of 24 input signals may be connected to nodes Nl and N2 f Figure 1, thus providing for wired NAND logical operations 26 on a plurality of input signals. For example, i a 27 plurality of input terminals (not shown are connected to 28 node Nl as is input terminal 11 of Figure 1, the signal on 29 each input terminal connected to node Nl must be a logical one to turn transistor Ml on, thus grounding (logical 31 zero) output leads 00 through 03 of transistor M1~ Con-32 versely, a single logical zero on any input terminal 33 connected to node Nl will sink the injector current provided 34 by transistor T, thus causing transistor Ml to turn off 3~ and provide a logical one on output lPads 00 through 03 of 36 transistor Ml Thus the additional input leads connected 37 to node Nl perform a wired NAND logic function.

1 One limitation of the prior art integrated injection 2 logic circuits, such as the owe shown in Figure 1, is that 3 upon the creation of a high voltage (typically 0.7 volts 4 on input terminal 11 (i.e. when a logical one applied ta input ~enminal Al), transistor Ml turns on, thus decreaslng 6 the voltage on node N2 to Vs1, where V5l is the collectQr 7 emitter voltage of transistor l when M1 is saturated.
8 Similarly, with a low voltage (typically around 0.1 volts) 9 applied to input terminal ll, transistor Ml turns off, and the voltage on node N2 is approximately VEE - V~2, where 11 Vs2 is egual to the emitter collector voltage of transistor 12 T2 when transistor T2 is conducting. For typical I2L
13 circuits, VEE = 0.8 volts, Vsl 14 volts. Thus, the voltage on node 2 ranges from Vhigh of 15 e approximately 0~7 volts (logical zero on input terminal 16 11, transistor Ml non-conducting) to V10W of appro~im2tely 17 0.1 volts (logical one on input terminal 11, transistor M
18 conducting). Thus, node N2 experiences a rather large 19 voltage swing (O.6 jolts) between its logical zero and logical one states. This results in the prior axt inte-21 grated injection logic circuit of Figure 1 being slow due 22 to the time reguired to increase the charge on the capaci-23 tances of nodes Nl and N2 cO as to change the voltages on 24 these nodes from 0.1 volts to 0.7 volts when nodes Nl and ?5 N2 change from logical zero to logical one and the time 26 required to decrease the charge on the capacitances of 27 nodes Nl and N2 50 as to change the voltages on these nodes 28 from 0.7 volts to 0.1 volts when nodes Nl and N2 change 29 from logical one to logical zero. Furthermore, the prior art I2L circuits such as the circuit of Figure 1 cause the 3~ switching transistors (M1 and M2 of Figure l) tG saturate 32 when turned on, thus requiring a relatively large period 33 of time to turn off and on as compared to transistors 34 which are not operated in saturat1on.
3~ The I2L circuit o Figure 1 has been modified to 37 provide prior art I2L circuits with incr2ased speed. For 2~ n8 example, an article entitled "IS, A Fast and Dense Low-Power Logic, Made in a Standard Schottky Process" written by Lohstroh, IEEE Journal of Solid State Circuits,Vol. SC-]4, No. 3, June 1979, pages 585-590 describes integrated injection logic circuits utilizing Schottky diodes. In Lohstroh's Figure 1, a plurality of Schottky diodes are connected in series with a single collector in order to drive a plurality of outputs.
These Schottky diodes serve to reduce the voltage swing between high and low Outpllt signals as compared with the prior art I2L circuit of Figure 1. This arrangement does not prevent saturation of the switching transistor, and the output voltage swing between high and low states is temperature dependent and influenced by DC voltage offsets between sequential stages of logic. The circuit of Lohstroh's Figure 2 adds an additional Schottky diode to prevent saturation of the switching transistor.
However, Lohstroh admits that this arrangement is not producible in a standard process, because two types of Schottky diodes are needed with different Schottky barrier heights. Furthermore, the circuit of Lohstroh's Figure 2 is temperature dependent and adversely influenced by DC voltage offsets between consecu-tive logic stages. The circuit of Lohstroh's Figure 3 provides a different technique to prevent saturation of the switching transistor However, this circuit is also temperature dependent and adversely affected by the DC voltage offsets between consecutive logic stages.
An article by Peltier entitled "A New Approach to Bipolar LSI: C L", 1975 IEEE International Solid-State Circuits Conference, Friday, February 14, 1975, pages 168-169 describes 'd 12~

yet another prior art integrated injection logic circuit.
Peltier's struc-ture utilizes a plurality of Schottky diodes connected in series with a single collector to provide a plurality of outputs. Peltier utilizes a - 7a --8~
1 Schottky transistor as the switching transistor in ordex 2 to provide a saturation voltage w:hich is not as low as the 3 satuxation voltage o f NPN switching transistors, as well 4 as to minimize charge storage wikhin the switching tran~
S sistor. The ~el~ier circuit is also temperature dependent, 6 and adversely affected by DC offset voltages between 7 consecutive logic stages 9 SU~IARY

11 This invention overcomes several disadva.ntasos of 12 prior art integrated injection logic circuits by providing 13 an integrated injection logic circuit in which the switch-14 ing transistors are prevented from saturating during lS conduction and in which the voltage swing between high and 16 low states is limited to approximately 0.1 volts.
~7 ~8 A current mirrox, wherein maximum current flow through 19 a collector is controlled by the current flow through an associated reference collector, is utilized in conjunction 21 with each switching transistor of the integrated i~jectlon 22 logic circuit of this invention by connecting one of a 23 plurality of the collectors of each switching transistor 24 to its base. In this manner, the current flowing through conducting switching transistors is limited by the current 26 mirror. This limited current flow thxough conducting 27 switching transistors, as well as the use of voltage pull 28 up means connected to the bases of the switching tran-29 sistors, pxevents the saturation of the conducting switch-ing transistors. This results in an increase in the 31 voltage on the collectors of conducting switching tran-32 sistors corresponding to a logical zero, and thus a decrease 33 in the voltage swing between a logical one and a logical 34 zero, thereby substantially increasing the speed of the integrated injection logic circuit of this invention as 36 compared to prior art integrated injection logic circuits.
37 The voltage pull up means connected to the bases of the 1~83C~3 injector transistors may comprise resis-tors or, preferably, forward biased Schottky diodes connected between a voltage source and the bases of the switching transistors.
Thus, in accordance with a broad aspect of the invention, there is provided an integrated injection logic circuit comprising: means for providing an injection current;
a switching transistor having a base coupled to said means for providing an injection current and serving as an input node, and having at least one collector serving as an output node, and a collector connected to said base; and additional means coupled to said base for clamping the logic swing at said base to a predetermined range determined by geometric ratios which are independent of process variations.
In accordance with another broad aspect of the invention there is provided an integrated injection logic circuit comprising: means for providing an injection current;
a switching transistor having a base coupled to said means for providing an injection current and serving as an input node, and having at least one collector serving as an output node, and a collector connected to said base; and additional means coupled to said base for causing the logic swing to increase with increasing temperature to substantially prevent degradation of the noise immunity and circuit margins of said logic circuit with increasing thermal noise power.
In accordance with another broad aspect of the invention there is provided an integrated injection logic circuit comprising: means for providing an injection current;
a switching transistor having a base coupled to said means _ g _ 330~

for providing an injection current and serving as an input node, and having at least one collector serving as an output node, and a collector connected to said base; and additional means for controlling the current flowing into and out of said base of said switching transistor in such a way as to cause turn-on time -to substantially equal turn-off time for a similar logic circuit connected to said output node.
In accordance wi-th another broad aspect of the invention there is provided an integrated injection logic circuit comprising: an input node for receiving an input logic signal; an injection means coupled to a first potential for supplying injection current to said input node; a switching -transistor having its base coupled to said input node and having a second collector serving as an output node which has twice the area of said first collector; and a low charge storage diode means coupled between said first potential and said input node for assisting in pulling up the voltage on said input node when said switching transistor is to be turned on.
In accordance with another broad aspect of the invention there is provided a method of operating an integrated injection logic circuit comprising the steps of: injecting a predetermined current into an input node of an integrated injection logic gate from a first potential source; and clamping the logic swing on the input node of said integrated injection logic circuit to a predetermined acceptable value which is determined by geometric ratios of physical characteristics of components of the integrated circuit layout, said logic swing being independent of process variations.

- 9a -~2~30~3 In accordance with ano-ther broad aspec-t of the invention there is provided a method of operating an integrated injection logic circuit comprising the steps of: injecting a predetermined current into an input node of integrated injection logic gate from a first potential source; clamping the logic swing on the input node of said integrated injection logic circuit to a predetermined minimum acceptable value which is determined by ratios of physical factors which ratios are independent of process variations; wherein the step of clamping the logic swing includes the steps of: supplying additional pull up current to said input node through a low charge storage pull up diode from a regulated potential source which includes low charge storage diodes; and regulating said potential source in such a manner that said logic swing is proportional to the ratio of the number of matching low charge storage diodes in the regulated potential source to the number of low charge storage pull up diodes connected to said input of the logic gate.
DETAILEn DESCRIPTION
-Figure 2 shows an integrated injection logic circuit constructed in accordance with this invention. Transistors Tl and T2 are shown as means for providing current to nodes Nl and N2, respectively, although other current sources (such as a resistor or a diode connected to a voltage source) may be utilized.
Schottky diodes Dl and D2 are connected between terminal 13 and nodes Nl and N2, respectively. The collector OO of transistor Ml is con-- 9b -~Z~3~

1 necked to the base of transistor Ml, and the collector P0 2 of transistor M2 is connected to the base of transistor 3 M2. Collectors Ox old P0 form cuxrent mirrors which serve 4 to limit the current flow through collectors l thxough 03 and Pl through ~3, as is more fully described below. It 6 is believed that PN diodes may not be used in place of 7 Schottky diodes D1 and D2 due to excessive minority carrier 8 charge storage within the EN diode during forward bias, 9 resultiag in the rather slow switching speeds of PN diodes.

l As a feature of this invention, a current mirror is 12 formed by connecting one of the plurality of collectors of ~3 each switching transistor to its base fig. 2). For 14 example, collector oO of switching transistor Ml is con-n cted to the base of Ml. Similarly, the collector P0 of 16 switchins transistor M2 is connected to the base of tran-17 sistor M2. Due to the high current gain or Beta of switch-18 ing transistor Ml (typically approximately 10-20), sub-19 stantially all of the injector current supplied by injector transistor Tl flows to the collector O0 of transistor Ml 21 when a logical one (i.e. open circuit) is applied to input 22 terminal 11. The current through collector 00 in turn 23 flows to the emitter of txansistor l which is grounded.
24 This connection between the base of transistor Ml and collector O0 pxovides a relatively constant collector 26 current Io through collector 00. Collectox current Io is 27 determined by the magnitude of VEE (typically 0.8 volts), 28 and the electrical characteristics of transistors Tl and 29 Ml. For a circuit fabricated with transistors of 0.5 microns by 0.5 microns per collector, preferably collector 31 current Io is set at approximately 25 microamps in order 32 to achieve a gate speed, with a fan out of four, of approxi-33 mately 50 picoseconds. The base current, the base-emitter 34 voltage of transistor Ml and the collector area determine the collector current of each of collectors 00 through 03 36 of transistor M1. Because the base current and base-37 emitter voltage are the same with respect to each collector 3~

~133C~

0~ through 03 of transistor l the following equation 2 defines the collector currents:

4 Ia/Io = Aa/A0 7 where Ia = the collector current ox collector 8 &~ where a i5 an integer ranging g from 1 to 3;
Io = the collector current of collector 11 O;
12 Aa = the collector area of collector 13 a; and 14 Ao - the collector area of collector ~0 17 Preferably the areas of collectors l through 03 are 18 constructed to be twice the area of collector 00. In this 19 manner, the collector current capable of being sunk by each of collectors l through 03 is egual to 2Io. In 21 fact, the colle.tor current Io Of collector 00 is equal to 22 slightly less than the current supplied by the collector 23 of injector transistor T2, because a small portion 1/(1+~) 24 of thy current supplied by injector transistor T2 forms the base current of transistor M2. were is the ratio of 26 collector current to base current of transistor T2.
27 however, this difference is negligible and for the purposes 28 of this specificati4n it will be assume that all the 29 injector current supplied by the injector transistors To and T2 form the collector current of the current mirrors 31 (collectors 00 and P0). thus, while injector transistor 32 To supplies a current Io to node N2 to turn transistor M2 33 on, transistor Ml (whey on) sinks a current 2Io from node 34 No, thus causing transistor M2 to turn off. Of this current 2Io sunk by txansistor Ml, half (Io) is provided 36 by injector transistor T2 and half (Io) is provided by 37 Schottky diode D2 Thus Schottky diode D2 conducts, thus 3~

33(~8 1 pausing the voltage VN~ on node N2 to equal Vdd (node 13) 2 minus Vsk, (the voltage drop across a forward biased 3 Schottky diode which is approximat:ety 0.6 volts).
Terminal 13 is connected to a positive voltage supply 6 Vdd, and serves to provide current to Schottky diodes Dl 7 and D2 coDnected to nodes Nl and ~2 respectively. Schottky 8 diodes Dl and Do limit the low voltage on nodes Nl and No 9 by supplying current in additicn to the cuxrent made available by inject3r transistors Tl and T2. Thus, when 11 node N2 is low the voltage on node N2 is equal to V10W, 12 where V10W is egual to the voltage V~d applied to terminal 13 13 minus the forward biased voltage drop vSk of Schottky 14 diode D2. thus, for example, utilizi.ng Schottky diode D2, the lower voltage limit of node N2 is raised from Vsl, the 16 collector-emitter saturation voltage of transistor M1 (as ~7 previously descried in conjunction with the prior art 18 integrated injection logic circuit of Figure 1), to V1OW.
19 In this manner, the voltage swing between a logical one and a logical zero at odes Nl and N2 is substantially 21 reduced a5 compared with 2rior art I2L circuits. The 22 reduced voltage swing between the two logic levels used in 23 a binary logic circuit results it increased switching 24 speed over priol art integrated injection logic circuits.
Additional Schottk~ diodes are connected between Vdc 26 (terminal 13) and all other bass which are used as input 27 terminals of all other switching transistors (e.g. bases 28 to which collectors l and 2 of transistor Ml and 29 collectors Pl and .P2 of transistor My are connected) 3~ although these additional switching transistors and Schottky 31 diodes are not shown in Figure 2. Collector 00 and P0 are 32 not used as output terminals because '~ney are used to form 33 the current mirrors, as previously described. Thus, 34 transistors Ml and My o the circuit of Figure 2 have a 35 fan out of three. Node Nl is connected to VIN, which is 36 typically made available on a switching transistor collector 37 (not shown). Thus, Schottky diode Dl serves to prevent saturation of the switching transistor (not shown) pro-- 2 viding VIM connected to node N .

4 In 'che I 2 L circuit constructed in accordance with S this invention havirlg a fan in of four, the voltage V10W
6 is approximat:ely 0 . 6 volts, and the voltage Vhigh is 7 approximately 0 . 7 volts . Thus, the voltage swing o nodes 8 Nl and N2 ~etweerl a logic~.l one and a logical zero is 9 app~sximately 0.1 volt, as compared with the voltage swing of approximately O.6 volts of the integrated injection 11 logic circuit of Figure l. For circuits constructed in 12 accordance with this invention having fan ins less than 13 four, it i5 advantegeous to use a voltage swing between 14 logical states of as little as 0.05 volts (for a fan in of 15 one ) to further reduce power and increase speed. Con-16 versely, for circuits constructed in accordance with this 17 inventlon hazing fan outs greater than four, it is ad-18 va~tageous to use a voltage swing between logical states 19 which is gxeater thy 0.1 volts to provide increased noise 20 immunity. However this increase in voltage swing need 21 not be great for a fan out of eight, a voltage swing of 22 0.12 volts provides adeguate noise immunity.

24 In one embodiment of this invention, Schottky diodes Dl and`D2 are connected through terminal 13 to VEE that 26 i5 Vdd is replaced by VEE), the positi-~e voltage-supplied 27 to the emitters of injector transistors Tl and I. The 28 connection of terminal 13 to VEE provides an integrated 29 injection logic circuit in accordance with this invention having increased switching speed over the prior art inte-31 grated injection logic circuits. however, connecting 32 Schottky diodes D1 and Do terminal 13) to VEE results in 33 a circuit whose characteristics exhibit an undesirable 34 change over operating temperature. For examplP, as the operating temperature of the device increases, the voltage 36 swing between a logical zero and a logical one decreases.
37 For a sufficiently low voltage swing between logic states, ~LZ~?~
~14~
1 the circuit ceases to function. Fuxthermore, as the 2 operating temperature of the devic:e decreases, the voltage 3 swing between a logical zero and a logical one increases7-4 thus decreasing the speed of the deviee. - -6 In order to eliminate the undesirable temperature 7 characteristics which result when terminal 13 is convected 8 to VEE, a second embodiment of this invention convects 9 terminal 13 to a second positive voltage source other than VEE. For example, many in~egr~ted injection logic circuits 11 derive their power fxom a voltase VcC of approxlmately 5 12 volts. From this 5 volt Vcc supply suikable circuitry is 13 utilized to generate various bias voltages, such as 5 14 volts for transistor-transistor logic (TTL) or approxi-mately 0.8 volts for integrated injection logic (I2L~.
16 This is typically how VEE is generated on a semiconductor ~7 chip, thus allowing -the entire chip to be supplied by a 18 single supply voltage Vcc. In the same manner, a voltage l9 Vdd may be generated from Vcc and applied to terminal 13 to drive Schottky diodes Dl and D2. The voltage of Vdd is 21 typically Nat room tPmpera~ure-~ approximately 1.0 Jo 1.2 22 volts although any voltage capable of providing current to 23 Schot~ky diodes Dl and D2 sufficient to make the voltagP
24 swing on nodes Nl and N2 approximately 0.1 volts between a 2~ logical high and a logical low is sufficient. When the 26 semiconductor device contains a plurality of integrated 27 injection logic gates, each gate will have with it an 28 assoclated Schottky diode connected to Vdd.

Figure 4 is the schematic diagram of a circuit which 31 is used to pxovide voltage Vdd on terminal 13, which 32 corresponds with terminal 13 of Figure 2~ Biasing circuit 33 100 comprises PNP injector transistor 81 having its base 34 connected to ground (V~), its emitter connected to a positive voltage source VEX, and its collector connected 36 to the base of NPN transistor 80. NPN transistor 80 is 37 identical to the switching transistors Ml and M2 of Figure 1 2 in order that the electrical characteristics of transistor 2 80 closely match the electrical characteristics of tran-3 sistors Ml and My. Similarly, PNP injection transistor 81 4 is identical PNP injection transistors Tl and To of Figure 2. PNP injection transistor 81 provides base drive to NPN
6 transisto 80, thus forward biasing the base-emitt~r 7 junction of NPN transistor 80, thereby turning on transistor 8 80. The emitter of transistor 80 is connected to ground 9 ~VGG~. Thus at 25C the voltage VREF on the base of transistor 80 i5 equal to approximately 0.7 volts, the 11 voltage drop across a forward biased PN junction. The 12 collector 80-0 of transistor 80 is connected to the base 13 of transistor 80. Because transistors 81 and Tl and 14 transistors 80 and Ml are well matched, as previously ~5 described, a collector current flows through collector 16 80-0 which is equal to the collector current Io flowing 17 through the collector l forming the current mirror of 18 transistor Ml (Figure 2 ) . Because the area of collector 19 80~1 is twice the area of collector 80-0, collector 80-1 will sink 2Io, as previously described or the cllrrent 21 mirror formed by collector 00 of transistor Mlo 23 Voltage regulator 78 receives VsUpply as an input 24 voltage to-be-regulated, and provides a regulated output voltage Vdd in response to a feedback signal on lead 103 26 from comparator 79. output terminal 13 of voltage regulator 27 78 is connected to the Schottky diodes Dl and D2 of Figure 28 2, as well as to the anodes of 100 Schsttky diodes sl, 29 s2,....Sloo connected it parallel as shown in Figure 4.
The use of 100 5chottky diodes sl through S100 is a simple and inexpensive technique for providing a voltage vdd 32 which results in a voltage swing on the collectors of the 33 switching transistors ~e.g. transistors M1 and M2 f 34 Figure 2) of approximately 0.1 volt between a logical high (O.7 volts and a logical low (O.6 volts), as is more 36 sully explained below. The cathodes of Schottky diodes 37 Sl, S2...... s100 are connected to collector 80-1 of tran-~2(~3308 -l sistor 80. Because collector 80-1 of transistor ao sinks 2 2Io, as previously described, a current equal to 2Io is 3 drawn from voltage regulator 7~ through Schottky diodes 4 S1, 52....... S1Qo, through collect4r 80-1 to ground. The input lead 101 of voltage comparator 79 is connected to 6 the cathodes of Schottky diodes Sl, S2....S100, and the 7 input lead 102 of comparator 79 is connected to the base 8 of tr~n~istor 80 (O.7 volts). The output lead 103 from 9 voltage comparator 79 is connected to voltage regulator 78, thereby providing a feedback signal to voltage regulator 11 78 which in turn controls the voltage Vdd on terminal 13.
12 When the voltage Vx on the cathodes of Schottky diodes Sl, 13 S2 .... S100 exactly equals the voltage on the base of 14 transistor 80 (0.7 volts), the signal on output lead 103 from comparator 79 is effectively equal to zero, and thus, 16 the voltage Vdd remains constant. If the voltage Vx is 17 greater than the voltage VREF on the base of switching 18 transistor 80, a feedback signal is applied from lead 103 19 of comparator 79 to regulator 78, thus causing regulator 78 to decrease the voltage Vdd. On the other hand, if 21 voltage Vx is less Han voltage VREF, a signal will be 22 applied from lead 103 of comparator 79 to regulator 78 23 causing regulator 78 to increase the voltage Vdd. In this 24 manner, the voltage Vx is regulated to be substantially equal to the voltage VREF (O7 volts-27 The current/voltage relationship of a PN junction is 28 defined as:

= Ix~exp(gv/kT)-l] (l) 32 where I = the current through the PN junction;

34 Ix = the thermal current of charge carriers through the PN junction in either 36 direction at zero bias;

383~3 1 q = the charge oi an electron (1.60 x 2 10 19 coulomb);
4 - V - the voltage across the PN junction;

6 k - Boltzma~n's constant (1.38xlO
7 Joules/K);
9 T ~empera~xe, in K.

11 .
12 thus, the voltage Vdd is defined in the following equation: -4 2lo/100 Ix~exp(q(Vdd-Vx)/kT)-l] (2) 16 where }72Io/lO0 = the current flow through each Schottky 18 diode Sl, S2~ S100;

20 Vx. = the voltage on the cathodes of Schottky 21 - .diodes Sl, S2~ S100~ whi 2~ regulated to equal 0.7 volts.

24 Similarly, the voltage/curren~ relationship of a single Schottky diode (e.g. D2 f Figure 2~ connected 26 between Vdd and a collector of a switching transistor, 27 when the switching transistor is turned on is defined as:

29 Io = Ix EeXP(g(Vdd ~low)/X~) ]
~0 31 where X0 the current through the Schot~ky diode 32 D2 which is sunX by the collector of 33 the switching transistor; and slow the (logical zero) voltage on node N2 36 . when swi*ching transistor Ml is con-37 . . ducting.

~2~3~

1 From equations (2) and (3):

3 [exp(q(~ )/kT)~l] - 50[exp(q~Vdd-V )/kT)-l] (4) 5 OR V1OW 0.7 -(kT/q3Qn (5) 7 Vlow 0.6 volts at .25C (6) ~Q Thus, the voltage Vl~w ox the collectors of injector 11 transistors Tl and T2 (Fig. 2) when transistors Ml and M2 12 are conducting is equal to 0.6 volts, as compared with the 13 low voltage of 0.1 volt in prior art I2L circuits. The 14 switching transistoxs Ml and M2 of the I2L circuit con-structed in accordance with this invention do not saturate, 16 and the voltage swing at room temperature between a logical 17 one and a logical zero is reduced rom 0.6 volts in con-18 ven~ional prior art I2L circuits to 0.1 volt in the present ~9 invention. Furthermore, as seen from equation (5), the voltage swing between a logical one and a logical zero is 21 equal to 22 high Ylo~ - (kT/~)~n 4 24 within the range of circuit operating temperatures. Tn this manner, circuit operating margins are preserved over 26 temperature. In the embodiment of this invention shown in 27 Figure 2, close regulation of currents is achieved by 28 basic I2L techniques and by the use of current mirrors.
29 Shunt pull up diodes l and D2 limit the voltage swing between logical states, with the voltage swing being 3~ determined, as shown in equation (7), by the ratio of 2 switching transistor collec~ox current when the swikching 33 transistor is conducting to switching transistor collector 34 current when the switchlng transistor is not conducting.
The relation between the switching transistor currents 36 when conducting and when not conducting therefore set 37 circuit margins. For example, the ratio of the maximum 3~

~2t~830~

switching transistor Ml collector current Io3MAX (approximately 2Io) to the switching current of switching transistor Ml (Io) is equal to approximately 2Io/Io=2 and is the margin by which switching transistor Ml is held on and the voltage on node N2 is held low. Similarly, the ratio of the switching current Io of switching transistor Ml to the minimum current drawn from node N2 through collector 03 by outputs connected to node N2 is the margin by which switching transistor Ml is held off and the vol-tage on node N2 held high. For thf~ circuit ox Figure 2, the ratio of switching current Io to minimum current drawn from collector 03 through node N2 when switching transistor Ml is off is equal to Io/ ~Fln)(.02)(2Io)~ where Fin is equal to the fan in, and (.02)(2Io) represents the current through collector 03 through each input lead connected to node N2 when node Nl is at logical zero and switching transistor Ml is turned substantially off.
T~s current (0.2)(2Io) when switching transistor Ml is turned off is described more fully below. Thus, this ratio is equal to l/0.12 or approximately 8.3 when a fan in of 3 is used. In other words, these margins, expressed in terms of currents, are (2Io-Io) = Io and (Io-0.12Io) - .88Io, respectively, for the high and low states of the voltage on node N2. The temperature behavior of equation (7) exactly corresponds to the temperature behavior not only of thermal (Johnson) noise voltage but also of the dynamic impedances of the connected junctions, thus tend-ing to preserve noise margins over temperature.
Further, the logic swing and margin characteristics of the , .

3~

invention are set by geometric layout factors and are, therefore, process independent. For example from equation (7~ and the de-rivation thereon using equations (2), (3) and (4) it is apparent that the loglc swing in the present invention is fixed by the ratio of current in the other collectors to the current in the collector coupled to the base and by the ratio of the number of Schottky diodes in the voltage regulator of Figure 4 to the num-ber of Schottky pull-up diodes in a single gate. That is, the factor natural logarithm of 50 is a factor which depends upon the relative area of the current mirror collector to the other collectors and upon the number of Schottky diodes in parallel in the regulator circuit versus the number of Schott~y diodes in each logic gate. These factors can be fixed in the geometric-al design and layout of an integrated circuit embodying the invention and will not vary with process variations from one batch of wafers to another.
Equation (7) also reveals that the voltage swing between the logic hiah and logic low levels varies directly with temper-ature~ This is a very good thing because it means that increasing temperatures will not degrade the noise and circuit immunity of the logic gate of this invention. It is well know that Johnson or thermal noise voltage increases with temperature. It is also wellknown that the dynamic impedance of a PN junction increases with temperature as can be seen from equation (1). The temper-ature characteristics of the logic swing defined by Equation (7) compensate for the increase in noise voltage and dynamic impendances of the junctions coupled to the input nodes of the ~U~3~8 gates of the invention because the logic swing increases with increasing temperature in a linear relationship. This fact guarantees that the noise and circuit immunity of the invention is maintained for rising temperatures.
Conversely for falling temperatures, the logic swing of the invention gets even smaller than the normally small swing of approximately 0.1 volts thereby increasing or maintaining the switching speed of the circuit.
In applicant's invention, the voltage Vdd is regulated at a predetermined level such that when, for example, the tran-sistor Ml turns on, the collector to emitter voltage is clamped at approximately 0.6 volts. This results from the fact that Vdd is regulated to be, at all times, exactly one forward biased Schottky diode voltage drop above the desired VLOW voltage by the circuit of figure 4. Thus when Ml turns on, the Schottky pull-up diode D2 becomes forward biased and the voltage on node N2 is allowed to drop only to Vdd minus the forward biased voltage drop across D2. This voltage on N2 with Ml on is, by design, only the desired voltage differential blow the VHIGH voltage on N2 when Ml is on. Because the voltage on N2 is only about 0~1 volts more negative than the voltage on Nl coupled to the base of Ml, Mlls collector base junction is forward biased but only by about 0.1 volts such that it can conduct a current of 2 Io but is not sufficiently forward biased to allow Ml to become significantly saturated. Thus no significant (less than 0.1%) 83~3 minority carrier charge storage occurs in the invention which would slow switching speeds.
The circuit of Figure 4 and the current mirrors and Schottky pull-up diodes Dl and D2 are the apparatus of the inven-tion for causing the logic swing of the gates to be clamped to a specific range wherein the low end of the range is the minimum acceptable value. the matched transistors and diodes of Figure 4 emulate the voltages and currents in the gates for all temperatures when the NPN transistors Ml and M2 in the gates are turned on.
This insures that the voltage desired for VLOW can be accurately obtained and can be set by geometries and ratios which are process independent. That is, the VLOW voltage can be set at any desired number by varying the number of Schottky diodes in the circuit of Figure 4 so as to change the term "ln 50" in Equation 7.
Thus the logic swing is independent of process variations.
If the logic swing and pull-down currents established by the transistors and diodes of the circuits of Figures 2 and 4 were variable with process variations in the characteristics of the transistors and diodes, there would be a problem Process variations result in devices which are inconsistent from batch to batch in switching speed and which vary significantly within a given batch and even within a single die in a given batch; the obvious result is that logic designers using such circuits must plan for the slowest of the circuits which could result from process variations, thereby slowing the effective switching speed of the circuits.

~2~3~3 In the invention, the tl~rn-on time is equal to the -turn-off time for one collector pulling down the input node. This follows because the current charging the input node when the switching transistor M2 is to be turned on is equal to the current being pulled out of the input node when the switching transistor M2 is to be turned off. ThP time to charge the input node to a given voltage therefore equals the time to discharge it. This is an important characteristic of the invention. That is because if the turn-on and turn-off times can vary with process variations,, the logic designer must time his logic such that the slowest possible time of the two times is accounted for in the design.
If this margin for error is not included in the design, some circuits will not function because process variations cause turn-on or turn-off times to exceed the planned-for timing criteria of the design. The necessity to plan for such possible process variations in the performance of individual gates will force logic designers to design logic cicuits which are non-optimal.
That is, they are slower than would be the case if the turn-on and turn-off times were known to be equal and non-process depen-dent.
The current mirror and collector area ratios of the switching transistors in the invention make the turn-on and turn-off times equal and not process dependent. Referring to Figure 2 the above assertion can be visualized best by example. Assuming that trans-istor M2 is turned off and Ml is turned on, then a collector cur-rent of 2Io is flowing out of node M2 and into collector 03 of Ml.

3~
-24;

Of this 2Io current out of node N2, half or Io is supplied by the collector of T2 and the other half is supplied through Schottky diode D2. Current out of the base of M2 is negligible.
The node N2 will be clasped at a voltage of VLOW in this state.
If Ml is then turned off, the current in collector 03 ceases and N2 begins to charge up from VLOW toward VHIGH.
The charging current is Io from T2 plus (initially) another Io through the Schottky diode D2. After the voltage on N2 rises by a few tens of millivolts, the current component through the Schottky diode Do falls off and becomes negligible as the diode's forward bias is decreased. However, the capaci-tance of node N2 is charged by a current of approximately 2Io until such time as the nodal capacitance is charged and the N2 voltage rises sufficently to turn on M2 and turn off D2~
Now suppose Ml turns back on. because of the connection of the collector 00 to the Ml base and the ratio of the area of the collector 00 to the areas of the collector 03, the current in the collector 0-3 is clamped at 2Io. Thus the node N2 capacitance and the excess stored minority carrier charge in the base region of M2 are initially being discharged by a current of 2Io flowing out of N2 and the base region of M2 and into collector 03. This is the same value of current that initially started charging the N2 node to turn on M2 except now N2 is being discharged by 2Io to turn M2 off. When the node N2 voltage falls a few tens of millivolts, M2's excess minority charge has been discharged through collector 03. D2 then turns on to supply a current of Io to match the Io collector current out of T2 to make up the 2Io collector current for Ml~ Of course the regulated ~a830~

voltage Vdd and the forward biased diode drop of D2 prevents the N2 voltage from falling below VLOw or 0.6 volts thereby preventing Ml Erom going heavily into saturation.

Figure 3 is a graphical representation of the current Io3 through collector 03 of transistor Ml for various voltages appearing on node N2. In addition, the "static" components of the collector current Io3 are shown. For example, Ip shows the collector current which flows through collector 03 in the prior art integrated injection logic circuit of Figure 1. The current Ip is limited essentially to the collector current of injection transistor T2. The line ISchottky bution to the collector 3~

current flowing through collector. 03 ox the embodiment of 2 this i~ent.ion shown in Flgure 3 due to the presence of 3 ~chottky diode D2~ The total current due to each of these 4 two components is shown in the line labelled Ito~al. It is this current, I~o~al, which f:lows through collector o 6 up to the limit of 2I~ (approximately 2IpmaX~ a5 discussed 7 px~viously.
8 ?
9 The currents shown in Figure 3 are called "static"
currents because whey do not include curxents which flow 11 in order to change the charge stored in the capacitances 12 of the circuit due to charging voltage levels during 13 switching. For the purposes of this specification, it is 14 to be understood that the currents represented in Figure 3 are these socalled "static" currents. As can be seen by 16 the graphical representatation o Figure 3, at nign voltages 17 (i.e. a logical one) on node N2, the total collector 18 current I~o~al is formed primarily by the contribution due 19 to the presence of prior art integrated injection logic circuit components. However, with a logical one on node 21 My, the current Itota1 is somewhat greater as compared 22 with prior art I2L circuits because the switching tran-23 sistor Ml (Fig. 2) is not turned completely off when node 24 Nl is at a logical zero. A logical zero on node Nl corres~
2S ponds to approximately 0.5 volts, as compared with a 26 logical zero of approximately 0.1 volt in prior art I2L
27 circuits. however, with a logical zero (O.6 volts) on the 28 base of switching transistor Ml, the collector current Ip 29 is equal to only approximately two percent (2%~ of the maximum collector current Isat (i.e. with a logical one 3~ equal to 0.7 volts connected to.the base of switching 32 transistor Ml) per output lead connected to node No. For 33 example, if two output leads are connected to node N2 34 (f.rom two separate logic gate outputs in a "wired NAND"
configuration, previously described), sufficient base 36 cuxrent to node N2 is provided by the logical zero (O.6 37 volts) state of the two driving gates to cause a pull-down 38 current at node N2 which is equal to approximately four 3~3~

_,~
1 percent (4%) of the maximum collector current Isat which 2 flows when transistor Ml is saturated. ~owevex, this 3 small current which flows when the driving gates are "off"
4 does no adversely affect circuit operation.
s 6 Whey the voltage on node Nl is incxeased from the low 7 state Jo the high state, collector current Io3 of tray-8 sistor Ml increases, thus causing voltage Vn2 on node No 9 to decrease. As the voltage Vn2 on node N2 decreases, additional shunt current is supplied by Schottky diode D2, 11 thus increasing the total collector current Itotal as 12 compared with the saturated current Isat of collector 03 13 of transistor Ml which would flow in the circuit of Figure 14 l. In this manner, Schottky diode D2 supplies current which is otherwise unavailabIe in a prior art integrated 16 injection logic circuit, thus preventing the voltage Vn~
17 on node N2 from decreasing to Vsl, the collector-emitter 18 voltage of transistor Ml when transistor.Ml is saturated.
19 This increases the voltage on node N2 whey node No is low level (logical zero) as compared with pxior art I2L circuits.
21 Due to the decrease it the voltage swing bet~ee~ logical 22 one and logical zero, the change of charge stored in the 23 capacitance associated with node N2 due to switching 24 between a logical zero and a logical one is also decreased ~5 thereby providing increased switching speeds of the inte-~6 grated injection logic circuit of this invention as 27 compared with the switchlng speeds of prior art integrated 28 injection logic circuits.

As show in Figure 3, the use of Schottky diodes in 31 accordance with this invention limits the low level voltage 32 excursion of voltage Vn2 on node N2. In prior art inte-33 grated injection logic circuits, when transistor Ml of 34 Figure 1 turns on, current equal to Isat~.flows fxom node N2 through the collector 03, thus resulting in a voltage 36 v5l equal to approximately 0.1 volt on node N2, where V

3~)~

" .

1 is the saturation voltage of the coll~ctor-emitter voltage 2 of Ml. of importance, when Schott~y diodes are utilized 3 it accordance with this invention as in Figure 2, the low 4 level (logical zero) voltage on node N2 is limited (as shown in Figure 3) to 7 slow Vdd V5kr 9 where V10W is the voltage associated with a logical zero, 12 Vdd is the voltage applied to Schottky diodes via 13 terminal 13; and V5~ is the forward bias voltage drop across Schottky 16 diode D2 with a current Io flowing through Schottky diode 17 D2, as previously described.

19 Thus, as previously described, the low level (logical æero~ voltage V10W on node N2 is equal to approximately 21 0.6 volts. The.high level (logical owe) voltage vhigh on 22 node is equal to VEE-Vs2, because, it a similar manner 23 as previously discussed with regard to the prior axt 24 circuit of Figure 1, node N2 is not pulled down by the non-conducting transistor Ml. Thus, with VEE-O.8 volts 26 and Vs2=O.l volts, a logical one on node N2 is equal to ~7 approximately 0.7 volts.

29 The voltage swing on node N2 between a logical high and a logical low is equal to Vhigh minus VOW = V which 31 i5 approximately equal to 0.1 volts It comparison, prior 32 art integrated injection logic circuits provide a voltage 33 swing on.node N2 equal to thigh minus Vvsl whi pp 34 mately equal to 0.6 volts..
36 The .integrated inj.ection logic circuit of this in-37 vention ut1lizing bipolar transistors consumes Gore power .

33~3 ,,, 1 Han prior art integrated inject:Lon logic circuits. The 2 current consumption o an integrated injection logic 3 circuit constructed in accordance with thi5 invention is 4 approximately ~wi~e as great as the current consumption of a prior art integrated inj ectioIl logic gate utilizing 6 approximately the same injector current supplied by the 7 I?NP in; ector trarlsistor having its emitter connected to 8 VEE. the additional current consumption is due to the 9 presence of one Schottky diode per gate. Utilizlng small JO geometry, such as 005 micron line widths, integrated 11 injection logic circuits may be constructed in accordance 12 with this invention having switching speeds of approxi- -13 mately 50 to 100 picoseconds, while utilizing a fan-out of ~4 four, with an injector current of approximately 25 to 50 15 microamps per gate l A circuit constructed in accordance with this in-18 ven~io~, utilizing metal-oxide-silicon (MOS) transistors, 19 is shown in Figure 5. Input terminals 301, 302, 303, and 304 receive input signals Ion Il, I2 and I3, respectively.
21 Terminals 00 through 03 and PO through P3 serve as open 22 source output tenminals which may be connected (as is 23 terminal 03) to other circuitry, as desired. A resistive 24 voltage divider comprising resistors 306 and 307 is con-2~ nected between terminal 305 connected to a voltage Vdd~
26 and ground such that a fraction of the voltage Vdd (denoted 27 as Vhigh) is applied to input node 310. The voltage Vhigh 28 established by the voltage divider ccmprising resistors 29 306 and 307 provides the high level logic signal (arbi-trarily defined as a logical "one") on input node 310.
31 With logical ones applied to input terminals 301 through 32 304, the signal on node 310 is a logical one. On the 33 other hand, if any signals Io through I3 applied to input 34 terminals 301 through 304 is a logical zero tlow voltage), input node 310 is pulled down to that low voltage. In a 36 manner similar to the circuit of Figure 2, Schottky diode 37 309 connected between terminal 308 and input node 310 . . .

3~8 , ~24 limits the voltage ox node 310 corresponding to a logical zero. Input terminal 308 is convected to a voltage supply 3 VsC~ which is utilized to power the SchottXy diodes of the 4 circuit.
S I.
6 The voltage on input node 3:L0 is connected to the 7 gates of MOS switching transistors 311 0 through 311-3, 8 thus pro~idiny open souLce ou.~puts OQ through 03, re 9 spectively. Each output terminal 00 through 03 may be connected to input nods of additional logic gates, as 11 desired. furthermore, the number of switching translstors associated with each logic gate need not be four as shown 13 in Fisure 5, but may be any desired number consistent with 14 good M~S semiconductor design pxactice.
16 Preferably the voltage V10W corresponding to a logical 17 zero is set to approximately 0.9 volts (corresponding to a 18 VsCh of approximately 1.4 volts, and the voltage Vhigh, 19 corresponding to a logical one, is set to approximately l volts by Vdd and resistors 3~6 and 307. This results 21 in a voltage swing between a logical dne and a logical 22 zero ox approximately 0.3 volts. This voltage swing it 23 less than prior art MOS logic circuits designed for 1QW
24 voltage swings in which the-logical one state is typically 1.5 ~ol~s and the logical ~exo state is typically 0 volts.
26 As stated previously with respect to the logic circuit of 27 Figure 2 which is constructed in accordance with the 28 i~ention utilizing bipolar ~ransis~ors, the reduced 29 signal swing between the logical one and the logical zero will result in increased speed due to the reduced amount 31 of time required to change the charge stored in the node 32 capacitances of this circuit. Furthermore, the speed 33 power product of the circuit constructed in accordance 34 with this invention utilizing MOS devices is less than the speed-power product cf a comparable MOS logic circuit of 36 the prior art.

12~3~3 ,., ~,~
1 An improved version of the circuit Figure 5 sub-2 stitutes for resistor 307 an additional Schottky diode 3 having its anode connected to input node 310 and its 4 cathode connected to a second Schottky reference voltage, ~sch2 Similarly, resistor 407 is replaced by a Schottky 6 diode having its anode connected Jo node 410 and its 7 cathode connected to the refexence voltage Vs~h2. In this 8 manner, the additional Schottky diodes establish the 9 voltage Vhigh corresponding to a logical one equal to v5ch2 plus one forward biased Schottky diode voltage drop.
11 For a apical value of v5ch2=o.7 volts, and a forwaxd 12 biased SchotLXy diode voltage is equal to 0.5 volts, Vhigh 13 is equal to 1.2 volts.

The bias voltages Vsch (connected to 5chott~y diodes 16 309 and 409) and Vsch2 (connected to the Schottky diodes 17 replacing resistors 307 and 407 of Flgure 5) can be set 18 and controlled over a wide temperature range by the 19 ~echnigue embodied in Figure 4, previously describea in conjunction with the circuit constructed in accordance 2i with this invention utilizing bipolar transistors.

~3 While several embodiments of this invention have been 24 disclosed in this specification, these embodiments are not limitations of the scope of this invention. Other embodi-26 ments will become apparPnt to those skilled in the art in 27 'ight of this specification.

2g .~

SUPPLEMENTARY DI SCLOSURE

Although the circuit of the present invention has been described as including exemplary voltage pull up means in the form of Schottky diodes, other well-known and available low charge stor-age diode devices may be used. For example, one such device includes a txansistor having a base, an emitter, and at least one collector with the collector coupled to the base. So-called "diode connected transistors," can be used in place of Schottky diodes Dl and D2. The maximum current density of a Schottky deviee is not yet known, but it is known that a diode connected transistor will provide a least the same eurrent density as switching transi-stors Ml and M2. A diode eonneeted transistor will provide greater current density than a diode, and will have by comparison an insignificant stored charge, thereby providing small size and high spied.

Claims (16)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. An integrated injection logic circuit comprising:
means for providing an injection current;
a switching transistor having a base coupled to said means for providing an injection current and serving as an input node, and having at least one collector serving as an output node, and a collector connected to said base; and additional means coupled to said base for clamping the logic swing at said base to a predetermined range determined by geometric ratios which are independent of process variations.

2. An integrated injection logic circuit as in Claim 1 wherein said clamping means includes a diode which minimizes charge storage having its anode connected to a first potential which is independent of a second potential supplying said injection means, said first potential being regulated to guarantee said predetermined logic swing and its cathode coupled to said base of said switching transistor.

3. An integrated logic circuit as in Claim 1 wherein said injection means comprises a bipolar transistor having a base coupled to the same potential as said emitter of said switching transistor, an emitter coupled to an injection potential and a collector coupled to said input node and said clamping means includes a Schottky diode having its anode coupled to a regulated pull up potential and its cathode coupled to said input node where said pull up potential is regulated to cause a predetermined logic swing.

4. An integrated injection logic circuit as in Claim 1 wherein said clamping means causes the logic swing to be clamped to approximatively 0.1 volts.

5. An integrated injection logic circuit as in Claim 1 wherein said clamping means includes a voltage regulator and a Schottky diode having its cathode coupled to said base, where said voltage regulator regulates the voltage on the anode of said diode to be one forward biased Schottky diode voltage drop above the desired logic low voltage.

6. An integrated injection logic circuit comprising :

means for providing an injection current:

a switching transistor having a base coupled to said means for providing an injection current and serving as an input node, and having at least one collector serving as an output node, and a collector connected to said base ; and additional means coupled to said base for causing the logic swing to increase with increasing temperature to substantially prevent degradation of the noise immunity and circuit margins of said logic circuit with increasing thermal noise power.

7. An integrated injection logic circuit comprising :

means for providing an injection current;

a switching transistor having a base coupled to said means for providing an injection current and serving as an input node, and having at least one collector serving as an output node, and a collector connected to said base ; and additional means for controlling the current flowing into and out of said base of said switching transistor in such a way as to cause turn-on time to substantially equal turn-off time for a similar logic circuit connected to said output node.

8. An integrated injection logic circuit as in Claim 7 wherein said means for controlling the current flowing in and out of said input node includes means for causing the collector current in the collector coupled to said base to be one half the collector current of the other collectors of said switching transistor for the same base to emitter voltage.

9. An integrated injection logic circuit comprising :

an input node for receiving an input logic signal ;

an injection means coupled to a first potential for supplying injection current to said input node ;

a switching transistor having its base coupled to said input node and having a second collector serving as an output node which has twice the area of said first collector ; and a low charge storage diode means coupled between said firs potential and said input node for assisting in pulling up the voltage on said input node when said switching transistor is to be turned on.

10. An integrated injection logic circuit as in Claim 9 wherein said low charge storage diode means is a Schottky diode.

11. A method of operating an integrated injection logic circuit comprising the steps of :

injecting a predetermined current into an input node of an integrated injection logic gate from a first potential source : and clamping the logic swing on the input node of said integrated injection logic circuit to a predetermined acceptable value which is determined by geometric ratios of physical characteristics of components of the integrated circuit layout, said logic swing being independent of process variations.

12. The method of Claim 11 wherein said integrated injection logic gate has an input node coupled to the base of a switching transistor, an injection circuit for injecting pull up current into said input node, and an output node connected to a collector of the switching transistor, and wherein said output node is coupled to the input node of a next integrated injection logic gate of the same structure further comprising the step of controlling the current gain of said switching transistor in said integrated injection logic circuit such that the current which is sunk by the collector of said switching transistor when it is pulling down the input node of said next integrated injection logic gate is equal to about twice the injection current to the input node of said next gate supplied by the injection circuit of the succeeding gate.

13. The method of Claim 12 wherein the clamping step includes the steps of :

supplying a predetermined value of pull up current to said input node through a low charge storage diode means connecting a regulated potential source to said input node :

controlling the current gain of said switching transistor such that the pull down current from any input node of said next logic circuit is substantially equal to the pull up current injected into said input node of said next logic circuit by said injection circuit and through said low charge storage diode.

14. The method of Claim 11 wherein the clamping step includes the steps of :

supplying additional pull up current to said input node through a low charge storage diode means from a regulated potential source ; and regulating said potential source in such a manner that said logic swing is clamped to a predetermined value.

15. The method of Claim 14 wherein the regulating step includes the step of regulating the potential source such that the logic swing increases with increasing temperature.

16. A method of operating an integrated injection logic circuit comprising the steps of :

injecting a predetermined current into an input node of integrated injection logic gate from a first potential source ;

clamping the logic swing on the input node of said integrated injection logic circuit to a predetermined minimum acceptable value which is determined by ratios of physical factors which ratios are independent of process variations ;

wherein the step of clamping the logic swing includes the steps of :

supplying additional pull up current to said input node through a low charge storage pull up diode from a regulated potential source which includes low charge storage diodes ; and regulating said potential source in such a manner that said logic swing is proportional to the ratio of the number of matching low charge storage diodes in the regulated potential source to the number of low charge storage pull up diodes connected to said input of the logic gate.