JPH0666290B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming an electrode.

[Conventional technology]

In recent years, along with the miniaturization and high integration of semiconductor devices, miniaturization of wiring has been rapidly progressing. Therefore, due to the miniaturization of wiring, reliability issues such as migration resistance have been highlighted. In this regard, an Au electrode structure having a large allowable current density and a high reliability is renewed attention as compared with the conventional Al or Al-based alloy.

An example of the formal method of the Au electrode structure is shown in FIG. First, for example, a Ti-Pt film 33 is formed on the insulating film 32 on the wafer substrate 31, and a resist 34 is applied (FIG. 3 (a)). A resist is applied and developed to open an electrode pattern (FIG. 3 (b)). Next, using the resist 34 as a mask and the Ti-Pt layer 33 as a conductive path, an Au plating layer 35 is formed (FIG. 3C). After that, the resist 34 is removed, and the Ti-Pt layer 33 is etched by an ion milling method or the like to complete the electrode (FIG. 3 (d)).

[Problems to be solved by the invention]

However, the conventional Au electrode forming method has the following drawbacks. That is, as shown in FIG. 3 (b),
For the desired electrode width W ₁ and electrode spacing S ₁ , the actual Au electrode production is W ₂ and S ₂ , respectively, as shown in FIG. 3 (d), and the electrode width widens and the spacing narrows. It will be. Therefore, in metal etching, the thickness of the Au plating layer should be h
Then, the design value of the aspect ratio (ratio of depth and width) h /
In practice, since h / S ₂ increases with respect to S ₁ , etching becomes difficult in general, and metal residue is likely to occur, resulting in a short circuit between electrodes. This means that as the miniaturization progresses and the electrode width W and the interval S become smaller, the aspect ratio h / S becomes even larger because the Au plating thickness needs to be made larger in order to maintain the current density, which makes etching more difficult. It will be increased.

Further, in the conventional method, when applied to a two-layer wiring as shown in FIG. 4, since the electrode 44 has an inverse taper shape, the coverage (step coverage) of the interlayer insulating film 45 is deteriorated and the second layer metal is formed. When 46 is laminated, it becomes thin as shown by the arrow, which eventually causes disconnection of wiring, which is a serious problem in reliability.

[Means for solving problems]

A method of manufacturing a semiconductor device according to the present invention comprises a step of forming at least one layer of a metal film on a semiconductor substrate, a step of forming a resist pattern on the metal film having a cross-sectional shape in which an upper side is longer than a lower side, and the resist Masking the pattern to form a plated electrode having a cross-sectional shape in which the lower side is longer than the upper side.

〔Example〕

An embodiment of the present invention will be described with reference to FIG. For example, a Ti-Pt film 3 is grown on the insulating film 2 on the wafer substrate 1 by sputtering or the like, and then a positive resist 4 is applied. It is desirable that the thickness of the positive resist is thicker in consideration of the Au plating thickness, but if it is too thick, it is difficult to form a fine pattern, so 1 to 1.5 μ is preferable (FIG. 1 (a)). ). Next, the pattern 5 on the mask (or reticle) is transferred to the resist by ultraviolet light (FIG. 1 (b)).
After that, for example, after baking in an atmosphere containing ammonia gas, the whole surface is irradiated with far-ultraviolet light (FIG. 1 (c)). When the resist is developed with an ordinary positive resist developer, the cross section of the resist becomes an inverse taper shape, and when Au plating is performed, a gold pattern 6 which is the reverse of the resist pattern is obtained (FIG. 1 (d)). After removing the resist 4, the underlying Ti-Pt layer is etched by ion milling or the like to obtain a desired electrode pattern 6 '(FIG. 1 (e)).

When the interlayer insulating film 8 is grown on the electrode 7 formed by this method, an overhang does not occur because the taper in the positive direction different from the conventional one is attached. Therefore, even if the metal of the second layer is laminated, cracks and the like do not occur, and stable and highly reliable multilayer wiring can be realized (FIG. 1 (f)).

In this embodiment, the case where a positive resist having high sensitivity to ultraviolet light is used is shown, but of course, the present invention is not limited to this, and a positive resist having high sensitivity from far ultraviolet light to X-rays is also used. Will be sufficient.

Next, another embodiment will be described with reference to FIG. For example, a Ti-Pt film 13 is laminated on the insulating film 12 on the wafer substrate 11, and a negative resist 14 having a large absorption is applied. Resist here 14
Is still preferably 1 to 1.5 μm thick (FIG. 2 (a)). After that, ultraviolet light is irradiated to transfer the mask pattern 15 (second
Figure (b)). Further, develop with a negative resist developer,
After forming the mask pattern 15, Au plating is performed to form an Au plating pattern 16 (FIG. 2 (c)). After that,
The resist 14 is removed, and the Ti-Pt layer 13 is formed by an ion silling method or the like.
By etching, the desired electrode pattern 16 'can be realized. (FIG. 2 (d)).

Also in this embodiment, similar to the above-described embodiments, a tapered electrode pattern can be formed, so that the same effect can be expected in a multilayer wiring.

〔The invention's effect〕

As described above, according to the present invention, the Au plating layer having a taper can be formed by using the reverse development processing (image reversal process) for the positive type resist or the use of the negative type resist having large absorption. (I) Design dimension electrode width W ₁ of, relative spacing S _1, each W ₂ the finished size, S ₂ to the the conventional S ₂ <the present invention whereas a S ₁ S _2> from the S ₁ Au plating layer h Since the aspect ratio h / S ₂ is relaxed, defects such as metal residue in dry etching can be eliminated, and miniaturization can be easily dealt with.

(Ii) In addition, since the cross-sectional shape is tapered, the coverage of the interlayer insulating film can be maintained well even in the multilayer wiring structure, so that the wiring metal in the upper layer also has a good shape, and the wiring has no reliability such as wiring disconnection. The structure can be realized.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of the present invention, FIG. 2 is a sectional view showing another embodiment, FIG. 3 is a sectional view of a conventional manufacturing method, and FIG. 4 shows the process of FIG. It is sectional drawing which shows the two-layer wiring used. 1,11,31,41 …… Wafer substrate, 2,12,32,42 …… Insulating layer,
3,13,33,43 ... Base metal such as Ti-Pt layer, 4,34 ...
… Positive resist, 14 …… Negative resist, 15 …… Opening part,
5,17 …… Exposure part, 6,6 ′, 7,16,16 ′, 35,44 …… Au plating layer, 8,45 …… Interlayer insulating film, 9,46 …… Second layer wiring metal .

Claims (1)

[Claims] 1. A step of forming at least one layer of a metal film on a semiconductor substrate, a step of forming a resist pattern having a cross-sectional shape in which an upper side is longer than a lower side on the metal film, and the resist pattern is masked. And a step of forming a plated electrode having a cross-sectional shape in which the lower side is longer than the upper side.