JPH0664518B2 - Method of receiving data from successive approximation A / D converter - Google Patents

Description

TECHNICAL FIELD The present invention relates to a data receiving method for receiving serial reception interrupt of conversion data of a successive approximation A / D converter.

[Conventional technology]

When the A / D conversion start command is issued from the CPU and the successive approximation A / D converter (hereinafter abbreviated as ADC) that receives the command outputs the conversion data serially, the serial reception register on the CPU side has a predetermined number of bits. CPU when conversion data is captured
Serial interrupt occurs on. The CPU takes in the conversion data with this interrupt and completes one A / D conversion.

FIG. 3 is a block diagram of this type of system, in which 1 is a CPU, 2 is a successive approximation ADC, 3 is a serial data line, and 4 is a serial reception register. An analog input CH (channel) selection signal, an AD start signal, and a clock signal are output from the CPU1 to the ADC2. The ADC2 holds the 3-bit CH selection signal in the address latch 21, and the corresponding analog input (CH
0 to one of CH7) is selected by the multiplexer 22. When the successive approximation register (SAR) 23 receives the AD start signal, it first applies 1/2 of the maximum reference voltage REF to the D / A converter (DAC) 24, and the analog conversion value is compared with the analog input by the comparator 25. Let Then, through the multiplexer 22, the comparison result (1,0 depending on the size) of the corresponding channel is the SAR.
When input to 23, SAR23 gives the next comparison value 2 ^-2 REF to DAC 24, and then 2 ^-3 REF, 2 ^-4 REF, ...
And change the comparison value. Then, when the comparison result for the final comparison value 2 ^-8 REF is obtained, ⁸ for 2 ^-1 REF to 2 ^-8 REF is obtained.
A start bit and a stop bit are added to the bit A / D converted data, which are serially transmitted from the shift register 26 to the data line 3 and transferred to the serial reception register 4 on the CPU side.

FIG. 4 is a time chart when an analog input is AD-converted into 8 bits with a clock frequency of 250 KHz. 1
Since the clock cycle is 4 μs, 8 × 4 μs = 32 μs is required for 8-bit AD conversion, and (8 + 2) × to add 1 bit for each of start and stop for data transmission.
4 μs = 40 μs is required. Therefore, after a certain time (= 72 μs) from the rise of the AD start signal, the CPU 1 receives a reception interrupt.

FIG. 5A shows the relationship between the clock and the serial transfer data. In this example, the serial reception register 4 can take in the data at the falling edge of the clock.

[Problems to be solved by the invention]

By the way, in the electronic control device for controlling the internal combustion engine, as the control content becomes more complicated, a demand for higher speed A / D conversion is generated, and the number of cases in which the successive approximation type ADC as described above is used is increasing. However, since serial reception as described with reference to FIG. 3 is vulnerable to noise, there is a strong possibility of receiving erroneous data. For example, as shown in FIG. 5 (b), noise (especially ignition noise) is mixed in the data line 3 and A / D
When the level of the data line 3 temporarily changes even when the converted data is not transmitted, this is read as a start bit, and as a result, erroneous data due to noise is received.

In general, the ADC2 side takes a protective measure to pull-apple the data line 3 so that the output does not change when it does not receive the AD start signal. And from the viewpoint that the conversion data will not be sent unless the CPU1 also issues an AD start,
It is always ready to receive reception interrupts. Therefore, in the case shown in FIG. 5 (b), all 1's are erroneously received.

In order to improve this point, conventionally, a filter is provided on the receiving end side of the data line 3 to remove the noise. However, if a filter is used, high-speed transmission cannot be performed due to its time constant, and there is a drawback that the control response cannot be sufficiently improved. Further, a filter using an analog circuit is not preferable because it increases the amount of hardware.

The present invention seeks to reduce the probability of such erroneous reception without using a filter.

[Means for solving problems]

According to the present invention, a conversion start command is issued from a CPU to a successive approximation A / D converter, and the converter which receives the command sequentially compares an analog input with a reference value and converts the analog input into digital data having a predetermined number of bits, Further, in the data receiving method from the successive approximation type A / D converter in which the CPU receives a reception interrupt when the data is transferred to the serial reception register on the CPU side by serial communication, the reception interrupt at the time of outputting the start command Is provided, a step of prohibiting the reception interrupt at the end of the processing by the reception interrupt, and a step of prohibiting the reception interrupt when a predetermined time has elapsed after the conversion start command is output. It is also characterized in that the reception of the reception interrupt is limited to a certain period after the conversion start command is transmitted.

[Action]

If the reception interrupt reception by the CPU is limited to a certain period after the conversion start command is sent, even if incorrect data is input to the serial reception register due to noise during other periods, a reception interrupt request is generated. Since the CPU does not accept, the probability of false reception due to noise is significantly reduced. Moreover, since the CPU does not perform unnecessary interrupt processing, the processing time can be kept constant regardless of the presence or absence of noise. Moreover, since no filter is used, the baud rate does not decrease.

〔Example〕

FIG. 1 is a flowchart showing an embodiment of the present invention, and shows a part of the processing of the CPU 1 in FIG. COMP1 is an interrupt routine that occurs every 2 ms. "Conversion CH set" corresponds to CH selection signal transmission in FIG. 3, and "AD conversion start" corresponds to AD start signal transmission. In this example, the serial reception interrupt is permitted at the same time as this AD start (conversion start command). FIG. 2 is this time chart.

As shown in FIG. 4, when the transmission of the converted data is completed 72 μs after the start of conversion, a serial reception interrupt occurs at that time. In the serial reception interrupt routine of FIG. 1, processing is performed according to the AD conversion result, and then the serial reception interrupt is prohibited. Therefore, in this example, the time from the serial reception interrupt permission of the interrupt routine COMP1 to the serial reception interrupt prohibition of the serial reception interrupt routine (about 100 μs) is the time allowed for the reception interrupt, and the other period (2 ms -100μs)
Is prohibited from receiving interrupts.

However, if a reception interrupt does not occur within 200 μs after AD start considering the failure of ADC2, the serial reception interrupt is forcibly prohibited by COMP2 so that the main routine is not affected. This is the broken line part in FIG. This 20
0 μs is a length that takes into account the delay in jumping to the serial interrupt routine due to another interrupt, and if it is not present,
72 μs + several μs is sufficient.

〔The invention's effect〕

As described above, according to the present invention, when the conversion data of the successive-approximation-type ADC is received by serial communication, the reception interrupt permission period is limited by the program, so that erroneous reception due to noise can be achieved without reducing the baud rate. Can be reduced, and erroneous A / D conversion data will not be used.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a flow chart showing an embodiment of the present invention, FIG. 2 is an operation explanatory diagram thereof, and FIG. 3 is a configuration diagram of a system for receiving data from a successive approximation A / D converter, FIG. 4 is a time chart of A / D conversion operation, and FIG. 5 is an explanatory diagram of A / D conversion data. In the figure, 1 is a CPU, 2 is a successive approximation A / D converter, 3 is a serial data line, and 4 is a serial reception register.

Claims (1)

[Claims] 1. A conversion start command is issued from a CPU to a successive approximation A / D converter, and the converter which receives the command sequentially compares an analog input with a reference value and converts the analog input into digital data of a predetermined number of bits. Further, in the data receiving method from the successive approximation type A / D converter in which a reception interrupt is given to the CPU when the data is further transferred to the serial reception register on the CPU side by serial communication, the reception interrupt at the time of outputting the start command Is provided, a step of prohibiting the reception interrupt at the end of the processing by the reception interrupt, and a step of prohibiting the reception interrupt when a predetermined time has elapsed after the conversion start command is output, A method for receiving data from a successive approximation A / D converter, characterized in that acceptance of an interrupt is limited to a certain period after sending a conversion start command.