JPH0638235B2 - Information processing equipment - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a pipeline-controlled information processing apparatus that operates by a microprogram, and more particularly to an information processing apparatus that enables debug interrupts.

[Conventional technology]

Conventionally, in the above-described information processing apparatus, since there is little time difference between the debug factor detection timing and the debug interrupt timing, it is not necessary to be aware of the microprogram corresponding to the instruction regarding the debug interrupt.
With the increase in clock speed, the number of pipeline stages in the pipeline has increased, and the time difference between the debug factor detection timing and the debug interrupt timing has increased. I have to be aware of it.

[Problems to be solved by the invention]

As described above, when the microprogram operating in response to the instruction is aware of the debug interrupt, there arises a problem that the number of microprogram steps is increased and the instruction execution performance is deteriorated.

Therefore, the present invention is intended to provide an information processing apparatus that does not need to be aware of a debug interrupt even when the number of pipeline stages is large.

[Means for solving problems]

An information processing apparatus according to the present invention, which is a pipeline-controlled information processing apparatus that operates according to a microprogram method, includes a debug state display unit that indicates that the system is in a debug state when a series of software instructions are sequentially executed, and software. Debug factor detecting means for detecting a debug factor related to an instruction, debug interrupt masking means corresponding to a debug factor for enabling a debug interrupt when the system is in a debug state, the debug status display means, the debug factor detecting means and the Debug information buffer means capable of buffering the debug information of the upper stage of the pipeline obtained from the debug interrupt mask means for a plurality of the soft instructions, and responding to the debug information held by the debug information buffer means in the lower stage of the pipeline To generate a debug interrupt. It is.

With the above configuration, the debug interrupt factor detected in the upper stage of the pipeline is buffered, and the instruction execution can be stopped in the lower stage of the pipeline based on the debug interrupt factor information in the buffer. .

〔Example〕

 Next, the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing an outline of an information processing apparatus according to an embodiment of the present invention.

The debug status display register 1 is a register that holds a signal indicating that the system is in a debug state, the debug factor detection circuit 2 is a debug factor detection circuit that detects a debug factor, and the debug interrupt mask register 3 is the debug factor. It is a register consisting of a plurality of bits that holds a mask signal that determines the validity of the debug factor detected by the detection circuit.

The debug information buffer register file 4 stores the debug information obtained from the signal held by the debug status display register 1, the debug factor detected by the debug factor detection circuit 2, and the mask signal held by the debug interrupt mask register 3. It is a register file consisting of multiple words to be buffered. The debug interrupt circuit 5 is a control circuit for generating a debug interrupt based on the debug information held by the debug information buffer register file 4.

FIG. 1 is a block diagram of an embodiment of the present invention showing the information processing apparatus shown in FIG. 2 in more detail. Particularly, the debug information buffer register file 4 and the debug interrupt circuit 5 in FIG. 2 will be described in detail. It is the one described. Further, in FIG. 1, it is expressed by being divided into functional units. The debug status display register 1, the debug factor detecting means 2, the debug interrupt mask register 3, and the debug information buffer register file 4 in FIG. 1 correspond to those shown in FIG. 2, respectively. The debug information buffer register file 4 and the debug interrupt circuit 5 form a debug interrupt control unit.

In FIG. 1, an instruction unit 10 fetches a target instruction from a main memory (not shown) that stores a series of software instructions and its operands, decodes the instruction, and fetches the operand. The instruction unit 10 is also called a preceding control unit that performs an instruction prefetch operation, and includes a debug status display register 1 that indicates the debug status of the system and a debug factor detection circuit that detects a debug factor related to instruction fetch, operand fetch, operand store, etc. 2, a debug interrupt mask register 3 composed of a plurality of bits for holding a debug interrupt mask signal, and an instruction activation circuit for generating a start signal st for generating a start address of a microprogram corresponding to a software instruction and starting the microprogram. 11 and 11.

The debug status signal de held in the debug status register 1 is output via the signal line 101. The debug factor signals d ₀ , d ₁ and d ₂ detected by the debug factor detection circuit 2 are output via signal lines 102, 103 and 104, respectively.
The debug masks m ₀ , m ₁ , m ₂ held by the register 3 are output via the signal lines 106, 107, 108, respectively.

Start address I _a of the microprogram corresponding to the generated instruction of the instruction starting circuit 11 is output via the signal line 111, the start signal St is output via a signal line 109. Here, it is assumed that the debug factor signals d ₀ , d ₁ and d ₂ detected by the debug factor detection circuit 2 are synchronized with the activation signal St. The signals held by the Lesbians 1 and 3 are loaded by the microprogram.

The control storage unit 20 can store a plurality of microinstruction words and sequentially execute a series of microprograms. Further, the control storage unit 20 is the instruction unit 1
Even from 0, the address of the first step of the microprogram corresponding to the soft instruction is given, and the sequential arithmetic processing can be controlled.

The address circuit 21 is a circuit for selecting an input signal of the address register 22, and the start address I of the microprogram corresponding to the instruction output from the instruction unit 2 at the time of instruction activation.
_a and select the address register 22 via the signal line 203.
Give to. The address register 22 is a register that gives an address to the control memory 23, and the held address ad is given to the control memory 23 via the signal line 203.

The control memory 23 is a memory for storing a plurality of microinstruction words, and stores the microinstruction word corresponding to the address ad in the signal line 2
It outputs via 01 and 204. The signal output via the signal line 201 is the address N _a of the microinstruction word executed next to the current microinstruction word. The signal output via 204 is output to the control register 24. The control signals held by the control register 24 are signal lines 205 and 206.
The debug interrupt circuit 5 and the execution unit 30 are controlled via the.

The execution unit 30 is a pipelined arithmetic unit having a plurality of arithmetic stages, and its arithmetic operation is controlled by the control storage unit 20. This execution unit 30
The execution of the arithmetic operation in 1 is completed by the end of the last arithmetic stage of the arithmetic pipeline.

The debug information buffer register file 4 in the debug interrupt control unit includes a register file 41 composed of a plurality of words, a write address register 42 for designating a write address of the debug information D ₀ , D ₁ , D ₂ and a debug information D _0. , D ₁ , D ₂ and a read address register 43 for designating read addresses. The write address register 42 and the read address register 43 have a function of adding 1 to the value currently held when the hold signal is released. Buffer register file 41
The debug information D ₀ , D ₁ and D ₂ stored by the debug state signal de stored in the debug state display register 1 and the debug factor signals d ₀ , d ₁ and d detected by the debug factor detection circuit.
₂ and the debug interrupt mask signals m ₀ , m ₁ and m ₂ held by the debug interrupt mask register 3 and are given to the buffer register file 41 via the signal lines 405, 406 and 407. Here, the debug information D ₀ ,
D ₁ and D ₂ , the debug state signal de, the debug factor signals d ₀ , d ₁ and d ₂ , the debug interrupt mask signal m ₀ ,
The relationship with m ₁ and m ₂ is as follows.

D ₀ = de · d ₀ · m ₀ D ₁ = de · d ₁ · m ₁ D ₂ = de · d ₂ · m ₂ The write address WP of the write address register 42 is stored in the buffer register file 41 via the signal line 401. The address given and adding 1 to WP is given to the write address register 42 via the signal line 402. The read address RP of the read address register 43 is the signal line 403.
Is given to the buffer register file 41 via
The address obtained by adding 1 to is supplied to the read address register 43 via the signal line 404.

In the debug interrupt circuit 5 in the debug interrupt control unit, the registers 51 and 52 are 1-bit registers that hold and propagate control signals. The signal E _b of the control register 24 output via the signal line 205 is a signal instructing the end of execution of the instruction issued by the last microprogram word of the microprogram corresponding to the instruction. Signal E _b
The register 51 receiving the signal receives the signal E _c via the signal line 411.
To the register 52. The signal held by the register 52 is E _d . Time history register 54 is debugging interrupt occurs, holding the debug factor in registers history, input signal D _a, D _b, D _c is the signal lines 414, 415, and 416
Given through. D _a , D _b , D _c and signal lines 408, 4
Signals d ₀ ′,
The relationship with d ₁ ′, d ₂ ′ and E _d ′ is as follows.

D _a = E _d ′ · d ₀ ′ D _b = E _d ′ · d ₁ ′ D _c = E _d ′ · d ₂ ′ where d ₀ ′ = the signal d ₀ d ₁ ′ buffered in the buffer register file 41 = Signal d ₁ d ₂ ′ buffered in the buffer register file 41 = Signal d ₂ E _d ′ = E _d buffered in the buffer register file 41.

The debug interrupt factor history H ₀ , H ₁ , and H ₂ held by the history register 54 are sent to the execution unit 3 via the signal line 424.
It is given to 0 and can be referenced by microprograms. The input signal D _abc of the register 55 is the signal line 4
The relation between D _abc and D _a , D _b , D _c is given by the following equation.

The D _abc = D _a + D _b + D _c register 55 is a 1-bit register for pulsing the debug interrupt signal. The signal held by the register 55 is D _d .

Registers 56 and 57 are 1-bit registers that hold and propagate control signals. Input signal D _e of the register 56 is supplied through the signal line 418. Control signal D _e is pulsed by D _d holding of the register 55.

D _e = D _d · (D _a + D _b + D _c ) The control signal D _e held by the register 56 is given to the register 57 via the signal line 420. The control signal held by the register 57 is D _f . Flip-flop (FF) 5
The signal V held by 3 indicates the valid state of the control signal held by the control storage register 24. The set and reset conditions of the flip-flop 53 are as follows.

Set (SET) = D _f Reset (RST) = D _e = D _d · (D _a + D _b + D _c ) The control storage unit 20 and the debug interrupt control unit (4
The holding conditions of the registers in 5 and 5) are as follows.

(1) Address register 22: (2) Control register 24: (3) Register 51: (4) Register 52: “θ” (5) Register 54: D _d (6) Register 55: D _d (7) Register 56: “θ” (8) Register 57: “θ” “ .theta. "indicates that there is no hold condition. The address circuit 21 in the control unit 20 receives the instruction unit 1 via the signal line 111.
The start address I _a of the microprogram corresponding to the instruction is given from the instruction starting circuit 11 in 0, and the signal line 201
The address N _a of the microinstruction word to be executed next to the current microinstruction word is given from the control memory 23 via. The address circuit 21 is the signal supplied through the signal line 110,420 St, the output signal by D _e is determined. The truth table of the address circuit 21 is shown below.

In this table, P _a is generated by the address circuit 21. The output signal A _a of the address circuit 21 is given to the address register 22 via the signal line 202.

The abbreviations attached to the condition signals of the registers and flip-flops in FIG. 1 have the following meanings.

HLD: Hold RST: Reset SET: Set Next, the operation of the information processing apparatus of the present embodiment configured as described above will be described using the time chart of FIG. In FIG. 3, it is assumed that the clock cycle progresses from t ₁ to t ₁₂ . The number of pipeline stages including the control storage unit 20 and the execution unit 30 of this information processing apparatus is 6, and the stage names are S1, S2, and S, respectively.
3, S4, S5 and S6. The soft instruction A is composed of a micro instruction word a, and the soft instruction B is a micro instruction word b.
It is assumed that the program is composed of a microprogram composed of ₁ , b ₂ , b ₃ , b ₄ , b ₅ .

At clock cycle t ₀ , the microinstruction word a corresponding to the soft instruction A is the signals I _a and St of the instruction activation circuit 11.
Is started by. It is assumed that the debug factor relating to the instruction A has not been detected by the debug detection circuit 2. The control signal of the micro instruction word a is sequentially supplied to the stages S1, S2,
By executing S3, S4, S5 and S6, the operation as the instruction A is completed.

At clock cycle t ₁ , the start address b ₁ of the microprogram corresponding to the soft instruction B is activated. At this time, the debug state signal de held in the register 1 indicates the debug state, and the debug mask m held in the register 3
_It is assumed that ₀ , m ₁ and m ₂ indicate that the debug factor is effective. Further, at this time, the debug factor relating to the instruction B is detected by the debug factor detection circuit 11, and it is assumed that the debug information D ₀ , D ₁ , D ₂ is D ₀ , D ₁ , D ₂ = 0, ₀ , ₁ 0, 0, 1 is stored in the word P + 1 of 41. It is assumed that the write register 42 is incremented by +1 by the instruction activation signal St, the debug information regarding the instruction A is stored in the word P of the buffer 41, and the debug information regarding the instruction B is stored in the word P + 1 of the buffer 41. The read register 43 is the control signal E of the register 52 of the S4 stage.
+1 is added by _d . Microinstruction words b ₁ , b ₂ , b ₃ , b ₄ and b ₅ forming a microprogram corresponding to the instruction B activated at the clock cycle t ₁ sequentially execute each stage of the pipeline.

The micro instruction word b ₅ exists in the stage S4 at the clock cycle t ₉ , and the instruction B held by the register 52 at this time
Control signal E _d indicating the last microinstruction word of
By the debug information D ₀ ′, D ₁ ′ of the buffer 41,
D ₂ ′ is read out, a debug interrupt timing is generated, the flip-flop 53 is reset, and debug interrupt control is started. At this time, the debug interrupt factor is recorded in the register 54.

Start address P _a series of micro-program the clock cycle t ₁₀ performs debugging interrupt process is set in the address register 22, the microinstruction word corresponding to the address P _a is set in the control register 24 at the clock cycle t ₁₁ At the same time, the flip-flop 53 is set, and a series of microprograms for performing debug interrupt processing starts from clock cycle t ₁₂ onward.

〔The invention's effect〕

As described above, according to the present invention, the debug information is stored in the debug buffer at the start of execution of the soft instruction, and the debug interrupt control is performed by using the contents of the debug buffer. Even with an instruction that changes the debug mask or the debug mask, there is an effect that the execution operation of the instruction to be originally processed can be performed without considering the debug state at the start of the instruction, the debug factor, and the debug mask.

[Brief description of drawings]

FIG. 1 is a block diagram of an information processing apparatus showing an embodiment of the present invention, FIG. 2 is a block diagram showing an outline of the information processing apparatus shown in FIG. 1, and FIG. 3 is information shown in FIG. It is a time chart which shows the operation timing of a processor. Description of symbols: 1 is a debug status display register, 2 is a debug factor detection circuit, 3 is a debug interrupt mask register, 4 is a debug information buffer register file, 5 is a debug interrupt circuit, 10 is an instruction unit, 11 is an instruction activation circuit, Two
0 is a control memory unit, 21 is an address circuit, 22 is an address register, 23 is a control memory, 24 is a control register, 30 is an execution unit, 41 is a buffer register file, 42 is a write address register, 43 is a read address register, 51 , 52, 55, 56 and 57 are registers, 53 is a flip-flop (FF), and 54 is a history register.

Claims (1)

[Claims] 1. In a pipeline-controlled information processing apparatus that operates in a microprogram system and enables a debug interrupt, a debug status display means for indicating that the system is in a debug status when sequentially executing a series of soft instructions. ,
Debug factor detecting means for detecting a debug factor relating to the soft instruction, debug interrupt masking means corresponding to a debug factor for enabling a debug interrupt when the system is in a debug state, the debug state displaying means, the debug factor detecting means And debug information buffer means capable of buffering the debug information of the upper stage of the pipeline obtained from the debug interrupt mask means for a plurality of the soft instructions, and holding the debug information buffer means in the lower stage of the pipeline. An information processing apparatus having debug interrupt means for generating a debug interrupt in response to debug information.