JPH0635473Y2 - Protective sheet for semiconductor - Google Patents
Protective sheet for semiconductorInfo
- Publication number
- JPH0635473Y2 JPH0635473Y2 JP1989127268U JP12726889U JPH0635473Y2 JP H0635473 Y2 JPH0635473 Y2 JP H0635473Y2 JP 1989127268 U JP1989127268 U JP 1989127268U JP 12726889 U JP12726889 U JP 12726889U JP H0635473 Y2 JPH0635473 Y2 JP H0635473Y2
- Authority
- JP
- Japan
- Prior art keywords
- protective sheet
- chip
- sheet
- adhesive
- dicing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000001681 protective effect Effects 0.000 title claims description 60
- 239000004065 semiconductor Substances 0.000 title claims description 21
- 239000010410 layer Substances 0.000 claims description 29
- 239000000853 adhesive Substances 0.000 claims description 28
- 230000001070 adhesive effect Effects 0.000 claims description 27
- 239000012790 adhesive layer Substances 0.000 claims description 17
- 239000000428 dust Substances 0.000 claims description 9
- 230000006355 external stress Effects 0.000 claims description 7
- 230000003287 optical effect Effects 0.000 claims description 7
- 239000004820 Pressure-sensitive adhesive Substances 0.000 claims 1
- 239000012634 fragment Substances 0.000 description 9
- 239000000463 material Substances 0.000 description 5
- 238000000034 method Methods 0.000 description 3
- 229920000915 polyvinyl chloride Polymers 0.000 description 3
- 239000004800 polyvinyl chloride Substances 0.000 description 3
- 229920000298 Cellophane Polymers 0.000 description 2
- -1 acrylic ester Chemical class 0.000 description 2
- 239000006185 dispersion Substances 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920000728 polyester Polymers 0.000 description 2
- 239000004925 Acrylic resin Substances 0.000 description 1
- 229920000178 Acrylic resin Polymers 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 238000007664 blowing Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000002654 heat shrinkable material Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
- H01L2221/68322—Auxiliary support including means facilitating the selective separation of some of a plurality of devices from the auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
Landscapes
- Dicing (AREA)
- Laminated Bodies (AREA)
- Adhesive Tapes (AREA)
Description
【考案の詳細な説明】 （イ）産業上の利用分野 この考案は半導体用保護シートに関し、更に詳しくは半
導体装置の製造時におけるダイシングによる汚れを防止
するためにホログラム素子などの半導体素子や、微小光
学部品の表面を保護する保護シートに関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application This invention relates to a protective sheet for semiconductors, and more particularly, to a semiconductor element such as a hologram element or a minute element to prevent contamination due to dicing during manufacturing of a semiconductor device. The present invention relates to a protective sheet that protects the surface of an optical component.
（ロ）従来の技術 一般に、ウエハに形成された、半導体素子や微小光学部
品の複数の個々のチップは、ウエハ裏面に裏面保護シー
トを粘着剤を介して貼り付けてウエハを固定した状態で
ダイシングすることにより得られる。(B) Conventional technology In general, for a plurality of individual chips of semiconductor elements and micro optical components formed on a wafer, a back surface protection sheet is attached to the back surface of the wafer with an adhesive, and the wafer is fixed by dicing. It is obtained by doing.
従来、複数のホログラム素子を有するウエハをダイシン
グするには、 まず、PVC（ポリ塩化ビニル）フィルムなどのウエハ固
定用粘着剤１を有するウエハ固定用裏面保護シート（以
下、単に台シートという）２をウエハ裏面に貼り付けた
ものをセットしてダイシングにかける。Conventionally, in order to dice a wafer having a plurality of hologram elements, first, a wafer fixing back surface protection sheet (hereinafter simply referred to as a base sheet) 2 having a wafer fixing adhesive 1 such as a PVC (polyvinyl chloride) film is used. The one attached to the back surface of the wafer is set and subjected to dicing.
続いて、ダイシングをおこない、ダイシングの溝４を介
して各ホログラム素子３に分離する［第４図参照］。こ
の際、ホログラム素子の表面3aに上記粘着剤１の一部が
多量に飛び散るおそれがある。Then, dicing is performed to separate each hologram element 3 through the dicing groove 4 [see FIG. 4]. At this time, a part of the adhesive 1 may be scattered in large amounts on the surface 3a of the hologram element.
次に、ホログラム素子の表面3aに飛び散った粘着剤（以
下ダストという）1aを除去するとともにダイシング時の
外部応力によるホログラム素子の変形を矯正するため
に、ダスト・ハクリ用粘着層を全面に有するセロハン等
の表面保護シート（以下、単に表シートという）（図示
せず）を、ウエハの表面全面を覆うようホログラム素子
表面3aにダスト・ハクリ用粘着層を介して貼り付ける。Next, in order to remove the adhesive agent (hereinafter referred to as dust) 1a scattered on the surface 3a of the hologram element and to correct the deformation of the hologram element due to external stress at the time of dicing, a cellophane having an adhesive layer for dust and peeling is formed. A surface protection sheet (hereinafter, simply referred to as a front sheet) (not shown) such as the above is attached to the hologram element surface 3a so as to cover the entire surface of the wafer through the dust / adhesive adhesive layer.
しかる後、上記表シートを熱を加えて熱収縮させた後ホ
ログラム素子表面3aから除去する。この際、ダスト・ハ
クリ用粘着層の粘着力がウエハ固定用粘着剤のそれより
も弱い場合には、ピンセットなどのハクリ手段にて表シ
ートをウエハからハクリする。また、粘着力がウエハ固
定用粘着剤の粘着力と同程度かそれ以上の強いものであ
れば、UV光の照射によって粘着力を弱めた後上記と同様
にピンセットを用いてハクリする。Then, the front sheet is heat-shrinked to remove it from the hologram element surface 3a. At this time, when the adhesive force of the dust / peeling adhesive layer is weaker than that of the wafer fixing adhesive, the front sheet is peeled from the wafer by a peeling means such as tweezers. If the adhesive strength is the same as or higher than the adhesive strength of the wafer fixing adhesive, the adhesive strength is weakened by UV light irradiation, and then peeling is performed using tweezers as described above.
このようにして、各ホログラム素子３の表面の汚れを防
止していた。In this way, the surface of each hologram element 3 was prevented from being soiled.
その後は、台シート２上の各ホログラム素子３を洗浄・
乾燥させ、最後に台シート２からホログラム素子３をハ
クリしていた。After that, wash each hologram element 3 on the base sheet 2
It was dried, and finally the hologram element 3 was peeled from the base sheet 2.
また、従来の他のダイシング方法としては、上記ダスト
がチップ表面に付着しないようにするとともに、ダイシ
ング時の外部応力によりチップが変形するのを保護する
ために、ウエハのダイシング前に、あらかじめウエハの
表面全面に表シートを貼り付けて、しかる後ダイシング
をおこなうようにしていた。Further, as another conventional dicing method, in order to prevent the dust from adhering to the chip surface and to protect the chip from being deformed due to external stress at the time of dicing, before dicing the wafer, the A front sheet was attached to the entire surface, and then dicing was performed.
（ハ）考案が解決しようとする課題 しかし、前者の場合、表シートのセロハンを取り除く際
に、表シートの粘着層の粘着力を弱めたり、粘着層自体
弱い粘着力のものを用いたりするとともに、さらに取り
除きを容易にするために、表シートが熱収縮材であるの
で、熱収縮をおこなっても表シートがホログラム素子上
面3aに接着した状態で単に収縮するだけで、ホログラム
素子３と表シート間の接着面積は熱収縮前と略同じ大き
さに維持されるから、表シートの取外しが容易ではな
く、ダストとしての粘着散1aが表シートを取り除いても
依然ホログラム素子上面3aに残留するおそれがある。(C) Problems to be solved by the invention However, in the former case, when removing the cellophane of the front sheet, the adhesive layer of the front sheet may be weakened or the adhesive layer itself may be weak. Further, since the front sheet is a heat-shrinkable material for easier removal, even if heat-shrinking is performed, the front sheet simply shrinks in a state of being adhered to the hologram element upper surface 3a. Since the adhesive area between the two is maintained at about the same size as before the heat shrinkage, it is not easy to remove the front sheet, and the adhesive dispersion 1a as dust may remain on the hologram element upper surface 3a even if the front sheet is removed. There is.
また、後者の場合にも、ダイシング後の個々のチップ表
面より表シートの断片を取り除くのは、上記前者の場合
と同様にチップと断片間の接着面積が熱を加えても依然
として小さくならないから、容易ではない。Also in the latter case, removing the fragments of the surface sheet from the surface of each chip after dicing is the same as in the former case, because the bonding area between the chip and the fragments does not become small even if heat is applied, It's not easy.
この考案は、半導体ウエハや微小光学部品をダイシング
した後に得られる個々のチップの上面に貼り付けられる
表シートあるいはその各断片をいずれも取り除き易く
（ハクリし易く）できる半導体用保護シートを提供する
ことを目的とするものである。The present invention provides a protective sheet for semiconductors that can easily remove (easily peel off) a front sheet or individual fragments attached to the upper surface of individual chips obtained after dicing a semiconductor wafer or micro optical component. The purpose is.
（ニ）課題を解決するための手段 この考案は、半導体ウエハや微小光学部品をダイシング
して得られる複数のチップをダイシング時に発生するダ
ストによる汚れや外部応力による変形から保護するため
に、チップ上面に保護シート用粘着層を介して貼り付け
られるチップ上面保護シートからなる半導体用保護シー
トであって、 そのチップ上面保護シートが、熱収縮率の異なる少なく
とも２つの保護シート層を有し、それによって熱付与に
より上記保護シート用粘着層の粘着力に打ち勝ってチッ
プ上面の接着面積を減少する方向に変形しうる保護シー
ト層積層構造からなる半導体用保護シートである。(D) Means for Solving the Problem This invention is to protect a plurality of chips obtained by dicing a semiconductor wafer or a micro optical component from dirt caused by dust generated during dicing and deformation due to external stress. A protective sheet for a semiconductor, which comprises a chip upper surface protective sheet that is attached to a substrate through an adhesive layer for a protective sheet, wherein the chip upper surface protective sheet has at least two protective sheet layers having different heat shrinkage rates. It is a semiconductor protective sheet having a laminated structure of a protective sheet layer that can be deformed in the direction of reducing the adhesive area of the upper surface of the chip by overcoming the adhesive force of the adhesive layer for a protective sheet by applying heat.
すなわち、この考案は、半導体用保護シートのチップ上
面保護シートを熱収縮率の異なる少なくとも２つの保護
シート層からなる積層構造にしたものである。That is, the present invention provides a chip upper surface protective sheet of a semiconductor protective sheet having a laminated structure including at least two protective sheet layers having different heat shrinkage rates.
この考案における半導体保護シート12の積層構造として
は、例えば第１図に示すように、２つの保護シート層12
aおよび12bが積層されてなる場合が挙げられる。この
際、各保護シート層としては、互いに熱収縮率の著しく
異なる材質のものを用いるのが好ましい。例えば、一方
の保護シート層12aとしてPFA（フッ素樹脂）やFEPなど
の非常に大きな熱収縮率を有する材料のものと、他方の
保護シート12bとしてポリ塩化ビニルやポリエステルな
どの非常に小さな熱収縮率を有する材料のものを用い
る。しかも両者12aおよび12bを熱収縮率の小さな他方の
保護シート層12bの一方面13に、エポキシ系樹脂やアク
リル系樹脂などの保護シート層用接着剤14を介して熱収
縮率の大きな一方の保護シート層12aを貼り合わせ、上
記他方の保護シート層12bの他方面15にはアクリル酸エ
ステル系などの材料からなる保護シート用粘着層11を設
けるのが好ましい。As a laminated structure of the semiconductor protective sheet 12 in this invention, for example, as shown in FIG.
An example is a case where a and 12b are laminated. At this time, it is preferable to use, as the respective protective sheet layers, those made of materials having significantly different heat shrinkage rates. For example, one protective sheet layer 12a is made of a material having a very large heat shrinkage such as PFA (fluorine resin) or FEP, and the other protective sheet 12b is made of a very small heat shrinkage such as polyvinyl chloride or polyester. A material having Moreover, both 12a and 12b are protected on one surface 13 of the other protective sheet layer 12b having a small heat shrinkage rate through the adhesive 14 for a protective sheet layer such as an epoxy resin or an acrylic resin and having a large heat shrinkage rate. It is preferable that the sheet layer 12a is bonded to the other protective sheet layer 12b and the protective sheet adhesive layer 11 made of a material such as an acrylic ester is provided on the other surface 15 of the other protective sheet layer 12b.
（ホ）作用 チップ上面保護シートを熱収縮率の異なる少なくとも２
つの保護シート層の積層構造にしたことから、半導体ウ
エハや微小光学部品をダイシングして得られる複数のチ
ップの各上面に保護シート用粘着層を介して貼り付けら
れたチップ上面保護シートは、熱が加えられると、熱収
縮率の大きな保護シート層が大きな熱収縮を引き起こす
ことによって熱収縮率の小さな保護シート層を伴ってチ
ップ上面にチップ上面保護シートを貼り付けるための保
護シート用粘着層の粘着力に打ち勝ってチップ上面から
ハクリされて行く。この際、チップ上面保護シートのチ
ップ上面との接着面積がチップ上面保護シートのハクリ
力によって熱を加える前に比して減少して行き、最終的
にはチップ上面保護シートはチップ上面に湾曲された状
態で、しかも該上面とはわずかな接着面積を有して載置
され、この状態のチップ上面保護シートにN2ガスや空気
を吹き付けることにより、湾曲したチップ上面保護シー
トが、その形状を保持しながら容易にチップ上面から取
り除かれる。(E) Action At least 2 chips with different heat shrinkage should be used for the chip top surface protection sheet.
Due to the laminated structure of the two protective sheet layers, the chip upper surface protective sheet attached to each upper surface of the multiple chips obtained by dicing the semiconductor wafer or the micro optical component via the protective sheet adhesive layer is Is added, the protective sheet layer having a large heat shrinkage causes a large heat shrinkage, so that the adhesive layer for the protective sheet for attaching the chip upper surface protective sheet to the chip upper surface is accompanied by the protective sheet layer having a small heat shrinkage. It overcomes the adhesive strength and is peeled off from the top surface of the chip. At this time, the adhesion area of the chip upper surface protection sheet with the chip upper surface decreases compared to before the heat is applied by the chipping force of the chip upper surface protection sheet, and finally the chip upper surface protection sheet is curved to the chip upper surface. In this state, the curved top surface of the chip is protected by blowing N 2 gas or air onto the chip top surface protection sheet in this state. It can be easily removed from the top surface of the chip while holding it.
（ヘ）実施例 以下図に示す実施例に基づいてこの考案を詳述する。な
お、これによってこの考案は限定を受けるものではな
い。(F) Embodiment This invention will be described in detail based on the embodiment shown in the drawings. However, the present invention is not limited to this.
第１図において、半導体用保護シート（表シート）は、
半導体ウエハをダイシングして得られる複数のホログラ
ム素子（以下、チップという）３をダイシング時に発生
するダストによる汚れや外部応力による変形から保護す
るために、チップ上面3aにアクリル酸エステル系の材料
からなる保護シート用粘着層（以下、単に粘着層とい
う）11を介して貼り付けられるチップ上面保護シート12
から主としてなり、 そのチップ上面保護シートが、熱収縮率の非常に大きな
フッ素樹脂PFAを材料とする第１保護シート層12aと、熱
収縮率のほとんど無いポリエステルを材料とする第２保
護シート層12bを有し、それによって熱付与あるいはUV
光照射により粘着層11の粘着力に打ち勝ってチップ上面
の接着面積を減少する方向（第３図における図示、A,B
で示す矢印方向）に湾形しうる積層構造からなる。In FIG. 1, the semiconductor protective sheet (front sheet) is
In order to protect a plurality of hologram elements (hereinafter referred to as chips) 3 obtained by dicing a semiconductor wafer from dirt caused by dust generated during dicing and deformation due to external stress, an acrylic ester-based material is formed on the chip upper surface 3a. Chip top surface protective sheet 12 attached via a protective sheet adhesive layer (hereinafter, simply referred to as an adhesive layer) 11
The chip top surface protective sheet comprises a first protective sheet layer 12a made of a fluororesin PFA having a very large heat shrinkage rate and a second protective sheet layer 12b made of a polyester having almost no heat shrinkage rate. Have a heat applied or UV
A direction in which the adhesive area of the chip top surface is reduced by overcoming the adhesive force of the adhesive layer 11 by light irradiation (illustration in FIG. 3, A, B
It has a laminated structure that can form a bay in the direction of the arrow).
更に、この積層構造は、第２保護シート層12bの上面13
に、エポキシ系樹脂を材料とする保護シート層用接着剤
14を介して全面に、第１保護シート層12aが貼り合わさ
れ、一方、第２保護シート層12bの下面15には、全面
に、粘着層11が形成されてなる。Further, this laminated structure has an upper surface 13 of the second protective sheet layer 12b.
Adhesive for protective sheet layer made of epoxy resin
The first protective sheet layer 12a is adhered to the entire surface via 14 while the adhesive layer 11 is formed on the entire lower surface 15 of the second protective sheet layer 12b.
この実施例のものは上記構成を有するから、チップを保
護するには、まず、第２図（ａ）に示すように、ウエハ
16を、台シート（裏シート）２に粘着剤１を介して載置
し、さらにウエハ上面16aを粘着層11を介してチップ上
面保護シート12で覆う。Since the structure of this embodiment has the above-described structure, in order to protect the chip, first, as shown in FIG.
16 is placed on the base sheet (back sheet) 2 via the adhesive 1, and the upper surface 16a of the wafer is covered with the chip upper surface protection sheet 12 via the adhesive layer 11.
次に、ダイシングをおこなって複数のチップ３をダイシ
ングの溝４を介して分離形成する［第２図（ｂ）参
照］。この際、保護シート12の断片17の上面に、粘着剤
１の１部が飛び散って付着する。Next, dicing is performed to form a plurality of chips 3 separately through the dicing grooves 4 [see FIG. 2 (b)]. At this time, a part of the adhesive 1 scatters and adheres to the upper surface of the fragment 17 of the protective sheet 12.
続いて、飛び散った粘着剤1aが上面に付着した状態で断
片17に加熱を施して断片17を湾曲させる［第２図（ｃ）
および第３図参照］。この際、断片17において、熱収縮
率の大きい上側の第１保護シート層12aの断片部分18が
熱収縮を引き起こし、それにより断片17が上側に凹状に
湾曲した形状になる。Then, the fragment 17 is heated with the scattered adhesive 1a attached to the upper surface to bend the fragment 17 [FIG. 2 (c)].
And FIG. 3]. At this time, in the piece 17, the piece portion 18 of the upper first protective sheet layer 12a having a large heat shrinkage factor causes heat shrinkage, whereby the piece 17 has a shape curved upward in a concave shape.
従って、チップ３と断片17間の接着面積がほとんど無く
なることから、N2ガス（あるいは空気）18を吹き付ける
ことによって断片部分18の上面に粘着散1aを付けたまま
断片17を簡単に取り除くことができる。Therefore, since the bonding area between the chip 3 and the fragment 17 is almost eliminated, the fragment 17 can be easily removed by spraying N 2 gas (or air) 18 with the adhesive dispersion 1a attached to the upper surface of the fragment portion 18. it can.
なお、ダイシング前にあらかじめ保護シート12でウエハ
16を覆うことで、該シート12がダイシング時の外部応力
を軽減する緩衝物としての役目を有するから、ダイシン
グ時に発生する外部応力によるチップ17の変形を抑制で
きる。Before dicing, use the protective sheet 12
By covering the sheet 16, the sheet 12 has a role as a buffer for reducing external stress at the time of dicing, so that the deformation of the chip 17 due to the external stress generated at the time of dicing can be suppressed.
（ト）考案の効果 以上のようにこの考案によれば、半導体用保護シートの
チップ上面保護シートを熱収縮率の異なる少なくとも２
つの保護シート層からなる積層構造にしたので、半導体
ウエハや微小光学部品をダイシングして得られる複数の
チップの表面上にチップ上面保護シートを貼った後熱を
加えると、熱収縮の大きい保護シート層が熱収縮を起こ
し、該シート層側にチップ上面保護シートが変形する。
これによりチップとチップ上面保護シート間の接着面積
がほとんど無くなり、チップからチップ上面保護シート
を取り除くのを容易にできる効果がある。(G) Effect of the Invention As described above, according to the invention, the chip upper surface protection sheet of the semiconductor protection sheet has at least 2 different heat shrinkage rates.
Since it has a laminated structure consisting of two protective sheet layers, when a chip top surface protective sheet is pasted on the surface of multiple chips obtained by dicing a semiconductor wafer or micro optical components, heat is applied to the protective sheet, which causes large thermal contraction. The layer causes heat shrinkage, and the chip upper surface protection sheet is deformed toward the sheet layer side.
As a result, the adhesive area between the chip and the chip upper surface protection sheet is almost eliminated, and the chip upper surface protection sheet can be easily removed from the chip.
第１図はこの考案の一実施例を示す構成説明図、第２図
（ａ）（ｂ）および（ｃ）はそれぞれ上記実施例を用い
てチップの保護手順を説明するための工程説明図、第３
図は上記実施例における動作を説明するための構成説明
図、第４図は従来例のダイシング時の状態を示す構成説
明図である。 11……保護シート用粘着層、 12……チップ上面保護シート、 12a……熱収縮率の大きな保護シート層、 12b……熱収縮率の小さな保護シート層、 14……保護シート層用接着剤、 16……半導体ウエハ、17……チップ。FIG. 1 is a structural explanatory view showing an embodiment of the present invention, and FIGS. 2 (a), (b) and (c) are process explanatory views for explaining a chip protecting procedure using the above embodiment, respectively. Third
FIG. 4 is a structural explanatory view for explaining the operation in the above embodiment, and FIG. 4 is a structural explanatory view showing a state during dicing in the conventional example. 11 …… Adhesive layer for protective sheet, 12 …… Chip top protective sheet, 12a …… Protective sheet layer with high heat shrinkage, 12b …… Protective sheet layer with low heat shrinkage, 14 …… Adhesive for protective sheet layer , 16 …… Semiconductor wafer, 17 …… Chip.
Claims (1)
して得られる複数のチップをダイシング時に発生するダ
ストによる汚れや外部応力による変形から保護するため
に、チップ上面に保護シート用粘着層を介して貼り付け
られるチップ上面保護シートからなる半導体用保護シー
トであって、 そのチップ上面保護シートが、熱収縮率の異なる少なく
とも２つの保護シート層を有し、それによって熱付与に
より上記保護シート用粘着層の粘着力に打ち勝ってチッ
プ上面の接着面積を減少する方向に変形しうる保護シー
ト層積層構造からなる半導体用保護シート。1. In order to protect a plurality of chips obtained by dicing a semiconductor wafer or micro optical components from dirt due to dust generated during dicing and deformation due to external stress, an adhesive layer for a protective sheet is provided on the upper surface of the chip. A protective sheet for a semiconductor, which comprises a chip upper surface protective sheet to be stuck, wherein the chip upper surface protective sheet has at least two protective sheet layers having different heat shrinkage rates, whereby the pressure-sensitive adhesive layer for protective sheet is provided by applying heat. A protective sheet for a semiconductor having a laminated structure of a protective sheet layer which can be deformed in such a direction as to overcome the adhesive force of the above and to reduce the adhesive area on the upper surface of the chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989127268U JPH0635473Y2 (en) | 1989-10-30 | 1989-10-30 | Protective sheet for semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989127268U JPH0635473Y2 (en) | 1989-10-30 | 1989-10-30 | Protective sheet for semiconductor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0365249U JPH0365249U (en) | 1991-06-25 |
| JPH0635473Y2 true JPH0635473Y2 (en) | 1994-09-14 |
Family
ID=31675032
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989127268U Expired - Lifetime JPH0635473Y2 (en) | 1989-10-30 | 1989-10-30 | Protective sheet for semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0635473Y2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010129607A (en) * | 2008-11-25 | 2010-06-10 | Nitto Denko Corp | Surface protecting tape for dicing and peel-off and removal method of the surface protecting tape for dicing |
| JP5451107B2 (en) * | 2009-02-24 | 2014-03-26 | 日東電工株式会社 | Self-winding laminated sheet and self-winding adhesive sheet |
| JP2011054641A (en) * | 2009-08-31 | 2011-03-17 | Nitto Denko Corp | Method for separating and removing dicing surface protection tape from object to be cut |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS604579A (en) * | 1983-06-22 | 1985-01-11 | Nitto Electric Ind Co Ltd | Pressure-sensitive adhesive tape or sheet for masking |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6461208A (en) * | 1987-09-01 | 1989-03-08 | Fsk Kk | Cutting method of wafer |
-
1989
- 1989-10-30 JP JP1989127268U patent/JPH0635473Y2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS604579A (en) * | 1983-06-22 | 1985-01-11 | Nitto Electric Ind Co Ltd | Pressure-sensitive adhesive tape or sheet for masking |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0365249U (en) | 1991-06-25 |
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