JPH0634591B2 - Overcurrent protection circuit for inverter device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an improvement of an overcurrent protection circuit for preventing an electric valve used in an inverter section of an inverter device from being damaged by an overcurrent at the time of output short circuit or the like. It is a thing.

[Conventional technology]

FIG. 4 is a block diagram showing an overcurrent protection circuit of an inverter device and its peripheral circuits used in a conventional general-purpose inverter (voltage type). This configuration is used as an overcurrent protection circuit of the current inverter device. It is extremely common.
In the figure, (1) is a DC power supply, (2-1) is connected in series with the transistor (2-4), the intermediate point U is connected to the load (5), and both ends are connected to the DC power supply (1). The transistor (2-3) is connected in series with the transistor (2-6), the intermediate point V is connected to the load (5), and both ends are connected to the DC power supply (1), (2-5)
Is a transistor connected in series with the transistor (2-2), the intermediate point W is connected to the load (5), and both ends are connected to the DC power source (1), and (3-1) is a transistor (2-
The diode (3-2) is connected in antiparallel so that the conduction direction of (1) is opposite to that of the conduction direction, and the diode (3-2) is connected in antiparallel with the transistor (2-2).
-3) is a diode connected in antiparallel with the transistor (2-3), (3-4) is a transistor (2-4)
And (3-5) is a diode connected in antiparallel with the transistor (2-5), (3-6) is a diode connected in antiparallel with the transistor (2-6), (4-1) is the intermediate point U between the transistor (2-1) and the transistor (2-4) and the load
A current detector inserted between (5) and (4-2) is a midpoint V between the transistor (2-3) and the transistor (2-6).
And a current detector inserted between the load (5) and (4-3) is a current inserted between the intermediate point W between the transistor (2-5) and the transistor (2-2) and the load (5). The detector, (8), takes the output of the current detector (4-1), the current detector (4-2), and the current detector (4-3) as input, and takes the absolute value of each output value and has the largest value. High priority circuit that outputs the output value, (9)
Is an overcurrent determination circuit that inputs the output of the high priority circuit (8) and determines overcurrent, (10) is a cutoff signal corresponding to the determination output from this overcurrent determination circuit (9), and (7) is a short circuit The output of the prevention circuit (11) and the cutoff signal (10) are input, and the transistor (2-
1), transistor (2-2), transistor (2-
3), transistor (2-4), transistor (2-
5), a cut-off circuit that outputs a signal to the base of the transistor (2-6), and (6) is a base signal generator that is an input to the short-circuit prevention circuit (11).

Next, the operation of what is shown in FIG. 4 will be described. First, the operation during normal operation will be described. Now, when the output frequency of the inverter is set by a frequency setter (not shown) and is input to the base signal generator (6) as a frequency command signal, the base signal generator (6) outputs a so-called 180-degree signal as shown in FIG. A control signal is generated for each of the current-carrying type (6 steps) transistors. In the figure, T indicates the period, and I
/ T is the output frequency. However, in reality, since there is a switching delay of the transistors, transistors above and below each arm, for example, transistors (2-1) and (2-
4), (2-3) and (2-6), or (2-5) and (2
-2) passes the output of the base signal generator (6) through the short-circuit prevention circuit (11) to prevent a short-circuit condition in which both are simultaneously turned on, and the dead time (td) is added to the base signals (firing signals) of the upper and lower transistors. It is provided. FIG. 6 shows a circuit diagram of one circuit of the short circuit prevention circuit (11). Needless to say, six circuits for six transistors are actually prepared. Also, since the operation is a delay timer, the details are omitted, but the transistor control signal as shown in FIG.
Input from (6), delay by the time constant determined by resistor R and capacitor C, delay the rise by dead time (td), and output the waveform as shown in Fig. 7 to the cutoff circuit as the transistor base signal. There is. In FIG. 6, D is a diode and B is a buffer. Cutoff circuit
(7) supplies the transistor base signal, which is the output of the short circuit prevention circuit (11), to the base of each transistor when the cutoff signal (10) is not output. Each transistor (2-
1) to (2-6) responds to this and switches and loads
Supply AC power to (5). Here, the diode (3-
1) to (3-6) play the role of a freewheeling diode used for processing the reactive energy of the load (5).

Now, the operation when the overcurrent protection circuit operates will be described. The current detector (4-1) detects the U-phase current, the current detector (4-2) detects the V-phase current, and the current detector (4-3) detects the W-phase current, and the voltage is proportional to the current. It is converted to a signal and sent to the high priority circuit (8). The high priority circuit (8) takes the absolute value of those voltage signals and outputs the largest voltage. This operation is shown in FIG. The overcurrent discrimination circuit (9) receives the output signal from this high priority circuit, and if the load increases for some reason and the current increases, the transistor (2-1)
~ (2-6), diode (3-1) ~ (3-6) at a level sufficiently lower than the current value leading to damage, the cutoff signal (10) to cut off the power supply to the load (5) Breaking circuit (7)
Send to. The cutoff circuit (7) responds to the cutoff signal (10) and cuts off the base signal to each of the transistors (2-1) to (2-6).
-6) switches off and the output is cut off.

All the transistors (2-1) to (2-
6) is protected from damage due to overcurrent.

Next, in the operation of the overcurrent protection circuit, the output short-circuit protection that most stresses the transistor will be described. Here, the output short circuit means that any two or three of the U, V, and W phases are in a short circuit state. here,
Consider the case where all three U, V, and W phases are short-circuited. According to FIG. 7 described above, if the dead time td period and the switching time of the transistors are ignored, the ignition signals applied to the transistors (2-1) to (2-6) are 6 as shown in Table 1. It is classified into modes.

Here, in Table 1, 1 is a state in which the transistor is on, 0
Indicates that the transistor is off. If you look closely at this, you can see that the transistor is in the following two states. That is, the upper transistor is on (two phases) on, the lower transistor is on (one phase) on, the upper transistor is on (one phase) on, and the lower transistor is on (two phases) on. Are relative, mode 6 in the representative example, that is, outputs U, V and W phases are short-circuited when the transistor (2-1), transistor (2-3) and transistor (2-2) are on. Think about when you're in a state.

This state is shown in FIG. Further, FIG. 10 shows the collector current and collector-emitter voltage that flow in each transistor when a short circuit occurs. The description of FIG. 10 will be given below. When a short circuit occurs at time t ₁ , the collector current of each transistor rapidly rises because the output impedance decreases. Transistor (2-2) is given base current and current amplification factor hFE unique to that transistor.
The collector current i (2-2) is increased to the current limited by and clamped. On the other hand, assuming that the electrical characteristics of each transistor are almost the same, each transistor (2-
The currents flowing through 1) and (2-3) are roughly as follows according to Kirchhoff's law.

Therefore, the collector-emitter voltage of the transistors (2-1), (2-3) and (2-2) has a non-linear relationship between the ic-V _CE (collector current-collector-emitter voltage) characteristics. Therefore, generally, as shown in FIG. 10, the transistor (2-2) having a large collector current mostly shares the voltage, while the transistors (2-1) and (2-3) do not share much voltage. In other words, the transistor (2-2) is the transistor (2-
1), it operates in a more active area than the transistor (2-3) and is exposed to severe stress.

Here, the current i (2-2) i.e. W-phase current at a time t ₂ exceeds the overcurrent determination level, as shown in FIG, it has started blocking starting to time t _3. This is the response delay of the current detector (4-3), the high priority circuit (8), the overcurrent determination circuit (9), the cutoff circuit (7), the response delay of the base drive circuit (not shown), and the storage of the transistor. It is a response delay due to time etc. Therefore, the transistor
Use those that have been designed so as not to be damaged even if exposed to these currents and voltages during a short circuit for this response delay time.

Now, at time t ₃ , the current starts to cut off. This interruption has the shortest storage time because the transistor (2-2) is in the deepest active area as described above,
It starts the cutoff fastest among the two transistors. The transistor to start the interrupted slave connexion time t ₃ (2-
2), the transistor (2-1) and the transistor (2-3) are externally collector currents i (2-1), i (2-3) because the transistor (2-2) is cut off. Is decreasing. Now, it takes a fall time from time t ₃ to time t ₄ , the transistor (2-2) reduces the current to 0 at the current decay rate di / dt and completes the interruption, but at this time, the spike due to the wiring inductance L occurs. Voltage V _p However, the voltage between the collector and emitter of the transistor V _CE (2-
2), the transistor (2-2) is exposed to severe stress. This is the R. B.
S. O. A. (Reverse Bias Safety Operation Area)
In order to keep it inside, suppress it with a snubber circuit, etc. B.
S. O. A. I am choosing a large transistor. As described above, in any case, it can be seen that a transistor that is isolated is exposed to the most severe stress when a short circuit occurs.

[Problems to be solved by the invention]

Since the conventional overcurrent protection circuit of the inverter device is configured as described above, when the output is short-circuited, the transistor that is individually called is exposed to extremely severe stress. As described above, the stress in the state from time t ₁ to t _{3 in} FIG. 10 is the current detector (4-3), the high priority circuit (8), the overcurrent determination circuit (9), and the cutoff circuit (7 ), Etc., and the response delay of a base drive circuit (not shown) can be shortened to reduce the stress of the transistor in a short-circuited state. On the other hand, from time t ₃ to t ₄
As described above, the stress applied to the isolated transistor at the time of turn-off is due to the wiring inductance. Therefore, to reduce the stress, either reduce the wiring inductance or suppress the spike voltage by strengthening the snubber circuit. The method such as is possible. However, all of them impede the miniaturization of equipment, such as structural considerations and the snubber circuit becoming larger, and when miniaturization is required, the R.V. B. S. O. A. It was necessary to use a large and expensive transistor.

The present invention has been made in order to solve the above problems, and significantly reduces the stress of the isolated transistor when the output is short-circuited and the transistor is turned off by the operation of the overcurrent protection circuit. ， It was necessary to prevent the conventional transistor from being damaged at this time. Strengthening the snubber circuit that accompanies the enlargement of equipment, B.
S. O. A. It is an object of the present invention to obtain an overcurrent protection circuit of an inverter device capable of protecting a transistor without using a large and expensive transistor.

[Means for solving problems]

The overcurrent protection circuit of the inverter device according to the present invention is provided with a majority circuit for receiving the opening / closing signal of the electric valve and making a majority decision of the closing signal of the upper electric valve of the three arms and the closing signal of the lower electric valve of the three arms. At the time of current protection operation, the closing signal of the electric valve on the side judged to be majority by the judgment of the majority circuit is first set to the open signal
After a certain time limit, the closing signal of the electric valve on the side judged to be a small number is opened.

[Action]

The overcurrent protection circuit according to the present invention is an electrical valve that is subjected to the second stress when opening the electric valve to release the electric valve from the first stress due to excessive stress applied to the electric valve when the output is short-circuited. Detects the valve and controls the opening sequence of the electric valve to reduce the stress on the electric valve,
Protects the electric valve from damage due to excessive stress applied to it when the output is short-circuited.

Example of Invention

An embodiment of the present invention will be described below with reference to the drawings. First
In the figure, (1) is a DC power supply, (2-1) is connected in series with a transistor (2-4), the midpoint U is connected to a load (5), and both ends are connected to a DC power supply (1). The transistor (2-3) is connected in series with the transistor (2-6), the intermediate point V is connected to the load (5), and both ends are connected to the DC power supply (1), (2-
5) is connected in series with the transistor (2-2) and is connected to the intermediate point W.
Is connected to the load (5) and both ends are connected to the DC power supply (1). The transistor (3-1) is antiparallel so that the conduction direction of the transistor (2-1) is opposite to that of the conduction direction of the transistor (2-1). Is connected to the transistor (2-2) in antiparallel to the transistor (2-2), (3-3) is connected to the transistor (2-3) in antiparallel to the diode, (3 -4) is a diode (3) connected in antiparallel to the transistor (2-4).
-5) is a diode connected in antiparallel to the transistor (2-5), (3-6) is a transistor (2-6)
And a diode (4-1) connected in antiparallel with the current detector (4-) connected between the load (5) and the intermediate point U between the transistor (2-1) and the transistor (2-4).
2) is a transistor (2-3) and a transistor (2-
The current detector inserted between the intermediate point V of 6) and the load (5), (4-3) is the intermediate point W of the transistor (2-5) and the transistor (2-2) and the load (5). The current detector inserted between (8) inputs the output of the current detector (4-1), the current detector (4-2), and the current detector (4-3), respectively, and A large-priority circuit that takes the absolute value and outputs the largest output value, (9) is an overcurrent judgment circuit that judges the overcurrent by using the output of the large-priority circuit (9) as input, and (10) is this overcurrent judgment circuit Cutoff signal corresponding to the judgment output from (9), (6)
Is a base signal generator that is an input to the short-circuit prevention circuit (10),
(12) is the output of the short circuit prevention circuit (11) and the majority decision circuit which receives the cutoff signal (10) as input, (13) is the majority decision result signal which is the output of the majority decision circuit, (7) is the output of the majority decision circuit and the interruption signal With (10) as input, transistor (2-1), transistor (2-
2), transistor (2-3), transistor (2-
4), transistor (2-5), transistor (2-6)
It is a cutoff circuit that outputs a signal to the base.

The operation of what is shown in FIG. 1 will be described below.
First, during normal operation, that is, when the cutoff signal (10) is not output, the majority circuit (12) and the cutoff circuit (7) output the short circuit prevention circuit (11) as it is, the transistor (2-1), Since the circuit is used as the base signal of the transistor (2-2), the transistor (2-3), the transistor (2-4), the transistor (2-5), and the transistor (2-6), it is completely different from the conventional example. The operation is the same, and the description thereof is omitted here.

Next, the overcurrent operation will be described. The current detector (4-
1), current detector (4-2), current detector (4-3),
The operations of the high-priority circuit (8), the overcurrent determination circuit (9), and the cutoff signal (10) are also the same as those in the conventional example, and therefore the description thereof is omitted here. Here, the operations of the majority decision circuit (12), the majority decision result signal (13), and the interruption circuit (7) when the interruption signal (10) is output will be described in detail.

In the majority circuit (12), the upper arm transistor (2-
1), (2-3) and (2-5) base signals (ON signals), and lower arm transistors (2-2) and (2-).
4), a majority decision of the base signal (ON signal) to (2-6) is taken. Using Table 1 used in the description of the conventional example, Table 2 shows the majority decision result signal (13) which is the result of each majority decision from mode 1 to mode 6. Here, 1 in the transistor column is a state where the base signal (ON signal) is output, 0 is not output, 1 in the majority decision result signal (13) column is a large number of upper arm transistors, 0 is The lower arm transitions are numerous. Also the majority result signal (13)
Is latched by the shut-off signal (10).

When the cutoff signal (10) is output due to the occurrence of an output short circuit or the like, the cutoff circuit (7) receives the majority decision result signal (13) and the cutoff signal (10), and in the sequence described below, the transistor (2- The base signals 1) to (2-6) are cut off. When 1 is output from the majority result signal (13), first, the base signal of the upper arm transistor is output. (ON signal) is changed from 1 to 0, that is, cut off (OFF), and after a certain time (tx), the base signal (ON signal) of the transistor of the lower arm is changed from 1 to 0, that is, cut off (OFF).
On the contrary, when 0 is output from the majority result signal (13), the base signal (ON signal) of the transistor in the lower arm is changed from 1 to 0, that is, cut off (OFF), and after a certain time (tx), the upper arm is turned off. The base signal (ON signal) of the transistor is changed from 1 to 0, that is, cut off (OFF). Mode as an example
FIG. 2 shows the time chart for shutting off the base signal of each transistor when the shutoff signal (10) is output at (6).

Further, FIG. 3 shows the collector current and collector-emitter voltage which flow through each transistor when a short circuit occurs in mode 6. (See FIG. 9 for the short-circuit state diagram of mode 6) When a short-circuit state occurs at time t ₁ , the collector current of each transistor sharply rises because the output impedance decreases. At time t ₂ , current i (2-2)
Exceeds the overcurrent determination level L _S , but due to the response delay, the cutoff signal (10) starts to be output at time t ₃ and the cutoff sequence cutoff operation shown in FIG. 2 described above is performed. Therefore, first, the transistor (2-1) and the transistor (2-3) having a small collector current and close to the saturation region are shut off. However, compared with FIG. 10 of the conventional example, a small current is cut at a slow speed (since it is close to a saturation state, it is cut at a slower speed than the conventional example in which a transistor in an active region is cut off by a single firing). Surge voltage hardly occurs though it depends on the snubber circuit.
The stress (second stress) is extremely smaller than that of.

Here, the majority decision circuit (1
An example of 2) will be described with reference to FIG. FIG. 11 shows a configuration in which a plurality of AND circuits and OR circuits are simply combined with the binary logic of Table 2 described above, and each transistor (2-
When the control signal of 1) to (2-6) is 1 (Hlevel), each transistor is turned on, and when it is 0 (Llevel), each transistor is OF.
As shown in Table 2, the majority decision result signal (13) shows that the upper arm transistors (2-1), (2-3), (2-5)
When the two are in the ON state, 1 (H level) is set, and the transistors (2-2), (2-4) and (2-6) in the lower arm are set to 2
It becomes 0 (L level) in the individual ON state.

Further, FIG. 12 shows an example of the breaking circuit (7) shown in the first embodiment of the present invention. Simply, in order to obtain the binary logic timer chart shown in FIG. AND circuit,
NOR circuit, resistor R ₀ for generating a time limit (predetermined time) t _x
A timing circuit comprising a capacitor C _0, and is constructed by combining a plurality of the buffer B for shaping the waveform of the output of the timing circuit.

Further, FIG. 13 shows a multi-decision circuit (1) of the first embodiment of the present invention.
2 shows an example of a circuit in which the circuit 2) and the cutoff circuit 7 are collectively configured. These circuits 12 and 7 can be easily configured by those skilled in the art in any case. The configuration is not limited at all.

Although a transistor is used as the electric valve in the above-mentioned embodiment, it is needless to say that the same effect can be obtained even if the electric valve is another electric valve.

Further, in the above embodiment, the so-called 180-degree conduction type (6 steps) is taken as an example of the control signal (base signal) of the electric valve of the inverter, but other electric valve control signal systems such as sine wave PWM may be used. By configuring an overcurrent protection circuit according to the gist of the present invention, the same effect can be obtained.

Further, in the above-described embodiment, since the output of the base signal generator (6) is not latched at the same time as the generation of the cutoff signal, the base signal may be switched during the cutoff operation, which may cause an inconvenience. To avoid this, the base signal generator
(6) Alternatively, the cutoff signal (10) should be given to the short circuit prevention circuit (11) as shown by the broken line in Fig. 1, and the output state of the base signal should be fixed by latching with this signal (10). .

〔The invention's effect〕

As described above, according to the present invention, the closing signal of the electric valve on the side judged to be majority by the judgment of the majority circuit during the overcurrent protection operation is first made the open signal, and the electric valve on the side judged to be the minority after a certain time limit. Since it is configured to open the closed signal of, the stress of the isolated electric valve when turning off the electric valve by the operation of the overcurrent protection circuit is remarkably reduced, and the snubber can be downsized, It is possible to reduce the size and cost of equipment. In addition, the withstand capability of the electric valve at turn-off can be reduced, and the price can be reduced.

[Brief description of drawings]

1 is an inverter device according to an embodiment of the present invention and its overcurrent protection circuit, FIG. 2 is a time chart when the circuit of FIG. 1 is cut off, and FIG. 3 is a case of using the circuit of FIG. The figure which shows the collector current and collector emitter voltage which flow into each transistor when the output short circuit occurs, FIG. 4 is the conventional inverter device and its overcurrent protection circuit, and FIG. 5 is the output of the base signal generator (6). FIG. 6 shows a control signal to each transistor, FIG. 6 is a circuit diagram of one circuit of a short circuit prevention circuit, FIG. 7 is a diagram showing a base signal of each transistor which is an output of the short circuit prevention circuit, and FIG. Operation explanatory diagram of the priority circuit (8), Fig. 9 is a diagram showing output short circuit in mode 6,
FIG. 10 is a diagram showing the collector current and collector-emitter voltage of each transistor when the output is short-circuited in mode S, FIG. 11 is a circuit diagram showing an example of the majority circuit (12), and FIG. 12 is a cutoff circuit. A circuit diagram showing an example of the circuit (7), FIG. 13 is a circuit diagram in which a majority circuit (12) and a cutoff circuit (7) are integrated.
It is a circuit diagram which shows an example. 1 to 3 and 11 to 13 are drawings relating to the present invention, and FIGS. 4 to 10 are partially related to the present invention, but in principle, they are drawings relating to a conventional example. is there. In the figure, (1) is a DC power supply, (2-1) is a transistor, (2-2) is a transistor, (2-3) is a transistor, (2-4) is a transistor, (2-5) is a transistor, (2-6) is a transistor, (4-1) is a current detector, (4-2) is a current detector, (4-3) is a current detector, (6) is a base signal generator, and (7). Is a cutoff circuit, (9) is an overcurrent determination circuit, and (12) is a majority decision circuit. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (4)

[Claims] 1. An electric valve arm having three arms vertically connected in series and having both ends connected to a DC power source and an intermediate connection point connected to a load, which is operated in response to an electric valve opening / closing signal from a control circuit. In an inverter device that supplies three-phase AC power to a load by sequentially opening and closing the valves, a current detector that directly or indirectly monitors the current flowing through the electric valve and a constant current that responds to the output of the current detector An overcurrent detection circuit that outputs an overcurrent signal when a current more than the current flows, a majority signal of the closing signal of the upper arm electric valve of 3 arms and the closing signal of the lower arm 3 arm in response to the opening and closing signals of the electric valve. Has a majority circuit, and the closing signal of the electric valve on the side judged to be majority by the judgment of the majority circuit when an overcurrent signal is generated is first set to an open signal, and after a certain period of time, the electric valve on the side judged to be minor is closed. A feature characterized by opening the signal Overcurrent protection circuit of the inverter device. 2. A majority decision circuit is a circuit for taking a majority decision of an open signal of an upper electric valve of three arms and an open signal of a lower electric valve of three arms, and it is judged as a small number by the judgment of the majority circuit when an overcurrent occurs. 3. The inverter device according to claim 1, wherein the closing signal of the electric valve on the side is first set to an opening signal, and after a certain time period, the closing signal of the electric valve on the side determined to be a large number is opened. Overcurrent protection circuit. 3. The majority decision circuit is latched by the generation of an overcurrent signal.
An overcurrent protection circuit for an inverter device according to any one of the items. 4. An inverter device according to claim 1, wherein the electric valve opening / closing signal from the control circuit is latched by the generation of an overcurrent signal. Overcurrent protection circuit.