JPH06338510A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device manufacturing method by which the capacitance between a base and an emitter can be made small and the base-emitter junction can be obtained in a highly precise manner. CONSTITUTION:An SiGe base layer 15-S and an N-type silicon emitter layer 17 are continuously formed, the silicon layer 17 is removed using the SiGe layer 15-S as a stopper, and an emitter structure 23 is obtained. A spacer region 25 is formed on the side wall of the structure 23, a P-type polysilicon layer 27, which is connected to the SiGe layer 15-S, is formed, a base wiring 33-B, which is connected to the polysilicon layer 27, is formed and an emitter wiring 33-E, which is connected to the silicon layer 17, is formed. By this constitution, as the width of base-emitter junction and the size of the emitter can be determined by obtaining the structure 23, the margin of matching can be decreased substantially, and the capacitance between the base and the emitter can also be made small. Besides, as the SiGe layer 15-S and the silicon layer 17 are continuously formed, a base-emitter junction can be obtained in a highly precise manner without exposing the SiGe layer 15-S.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a self-aligned bipolar transistor.

[0002]

2. Description of the Related Art A base layer formed by an epitaxial growth method (hereinafter referred to as an
(Also referred to as a device), for example, Thom
There is a method proposed by the group of as J Watson Research Center.

(Reference: IEEE Electron Device Lette
rs, Vol.10, No4, April 1989) FIGS. 13 to 20 show predicted manufacturing processes of an integrated circuit including a transistor manufactured by the above method. Figure 13
FIG. 14 is a cross-sectional view showing the final shape of the transistor.
20 to 20 are cross-sectional views showing respective main manufacturing stages.

The manufacturing method will be described below with reference to FIGS. 13 to 20. First, the N-type buried region 102 is formed in the surface region of the P-type semiconductor substrate 100. Then, silicon is grown on the substrate 100 to obtain the N-type epitaxial layer 104. Then epitaxial 104
An element isolation region 106 that penetrates the layer and the buried region 102 and reaches the inside of the substrate 100 is formed. Then
In order to reduce the stray capacitance in the peripheral portion of the device, the insulating region 108 is formed so as to surround the device active region. Then
In the future, an N-type impurity is introduced into a portion where a collector region will be formed to form a low resistance collector region 110 (FIG.
14).

Next, Si and G are deposited on the entire surface of the substrate 100.
The compound with e is epitaxially grown. As a result, the single crystal SiGe layer 112-S is formed on the element forming portion (epitaxial layer 104) and the collector region (low resistance collector region 110), and the polycrystalline SiGe layer 112-P is formed on the insulating region 108 and the element isolation region. It is formed on 106 (FIG. 15).

Next, an unnecessary portion of the SiGe layer 112-S,
And unnecessary portions of the SiGe layer 112-P are removed. As a result, the SiGe layers 112-S and Si are formed only on the element formation portion (epitaxial layer 104) and its peripheral portion.
The Ge layers 112-P respectively remain (FIG. 16). In addition, SiGe connected on the element formation portion (epitaxial layer 104)
The layer 112-S and the SiGe layer 112-P function as a base (epibase).

Next, a silicon oxide film 114 is obtained by depositing SiO ₂ on the entire surface of the substrate 100 by the CVD method (FIG. 17). Next, the silicon oxide film 114
Of these, the emitter formation region is removed. Then, on the entire surface of the substrate 100, the N-type polycrystalline silicon layer 116, the silicon oxide film (SiO ₂ ) 118, the silicon nitride film (Si
N _X ) 120 is sequentially and continuously formed (FIG. 18).

Next, the unnecessary portion of the polycrystalline silicon layer 116, the unnecessary portion of the oxide film 118, and the unnecessary portion of the nitride film 120 are removed. As a result, the polycrystalline silicon layer 1 is formed only in the emitter formation region and its periphery.
16, the oxide film 118 and the nitride film 120 remain, and the emitter structure 122 is obtained. Next, silicon dioxide is deposited on the entire surface of the substrate 100 by the CVD method to obtain a silicon oxide film 124 (FIG. 19).

Next, the entire surface of the oxide film 122 is etched by anisotropic etching. This leaves the oxide film 124 only on the sidewalls of the emitter structure 122 (see FIG.
20).

Next, a metal layer is formed on the entire surface of the substrate 100, and this metal layer is patterned. This allows S
A base wiring 126-B connected to the iGe layer 112-S and the SiGe layer 112-P and a collector wiring 126-C connected to the low resistance collector region 110 are obtained (FIG. 13).
Although the emitter wiring connected to the polycrystalline silicon layer 116 is also formed at the same time, it is not shown in the cross section shown in FIG.

[0011]

According to the manufacturing method described with reference to FIGS. 13 to 20, the base and the emitter cannot be formed in a self-aligned manner. That is, as in the step described with reference to FIG. 18, the emitter forming region is removed from the oxide film 114 to obtain a region for joining the base and the emitter. If the base and the emitter cannot be formed in a self-aligned manner, the capacitance between the base and the emitter unnecessarily increases, which hinders the operation speed from increasing.

Further, in the transistor structure shown in FIG. 13, since the base wiring 126-B overlaps the emitter, that is, the polycrystalline silicon layer 116, the capacitance between the base and the emitter is large.

When a compound of Si and Ge is used as the base material, the oxide film 11 is formed on the SiGe layers 112-S and 112-P which are relatively crystallographically unstable.
4 is attached, the SiGe layer 112-P is exposed when the opening is formed as in the process described with reference to FIG. 18, and the SiGe layer 112-P is exposed to an etchant or the like. Therefore, it is difficult to obtain the junction between the base and the emitter with high accuracy.

The present invention has been made in view of the above points, and an object thereof is a semiconductor device in which the capacitance between the base and the emitter can be reduced and the junction between the base and the emitter can be obtained with high accuracy. It is to provide a manufacturing method of.

[0015]

According to a method of manufacturing a semiconductor device of the present invention, a first semiconductor made of a first semiconductor is formed on a semiconductor substrate.
And a second semiconductor layer made of a second semiconductor different from the first semiconductor are continuously formed, and an unnecessary portion of the second semiconductor layer is replaced by the first semiconductor layer. It is used as an etching stopper and removed to obtain an emitter structure,
A spacer layer made of an insulating film is formed on the sidewall of the emitter structure. Then, a conductive layer electrically connected to the first semiconductor layer is formed, a base wiring layer electrically connected to the conductive layer is formed, and an electrically conductive layer is electrically connected to the second semiconductor layer. It is characterized in that a connected emitter wiring layer is formed.

[0016]

According to the method of manufacturing a semiconductor device having the above structure, an unnecessary portion of the second semiconductor layer is removed by using the first semiconductor layer as an etching stopper to obtain an emitter structure. By obtaining the emitter structure, the base (first
Width of the junction between the semiconductor layer) and the emitter (second semiconductor layer), and the size of the emitter are both determined. In this way, the width of the junction between the base and the emitter, which usually requires two steps, and the size of the emitter can be determined in a single step. The region can be omitted as much as possible, and the capacitance between the base and the emitter can be prevented from unnecessarily increasing.

Further, since the base wiring layer is drawn out by the conductive layer connected to the first semiconductor layer, the base wiring layer does not overlap the emitter (second semiconductor layer), Also from the viewpoint, the capacitance between the base and the emitter can be reduced.

Further, in order to continuously form the first semiconductor layer made of the first semiconductor and the second semiconductor layer made of the second semiconductor different from the first semiconductor, the first semiconductor layer is formed. A bond between the layer and the second semiconductor layer can be obtained without exposing the first semiconductor layer. Therefore, the junction between the base (first semiconductor layer) and the emitter (second semiconductor layer) can be obtained with high accuracy.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings. In this description, common parts are denoted by common reference symbols throughout the drawings to avoid redundant description.

FIG. 1 is a sectional view showing the final shape of a transistor obtained by the method for manufacturing a semiconductor device according to one embodiment of the present invention. FIGS. It is the sectional view shown.

First, P with the main surface being the (100) plane
N-type impurities are introduced into the surface region of the type silicon substrate 1 to form the N-type buried region 3. At this time, arsenic (As) or antimony (Sb) is used as an impurity added to the buried region 3. Then, the impurity concentration of the buried region 3 is set to 1 × 10 ¹⁹ cm ⁻³ . Then, silicon is epitaxially grown on the substrate 1 to obtain the N-type epitaxial layer 5. The thickness of the epitaxial layer 5 is determined by the breakdown voltage of the transistor. In this embodiment, the thickness of the epitaxial layer 5 is 600 nm. Further, phosphorus (P) was used as an impurity added to the epitaxial layer 5, and the impurity concentration was set to 1 × 10 ¹⁶ cm ⁻³ . Next, an element isolation region 7 that penetrates the epitaxial layer 5 and the buried region 3 and reaches the inside of the substrate 1 is formed, and then, in order to reduce the stray capacitance in the peripheral portion of the device, the device active region is surrounded. , The insulating region 9 is formed. For the element isolation region 7, a technique generally called trench isolation is adopted. Further, a silicon oxide film (SiO ₂ ) is used as an insulating material in the insulating region 9. Next, in the future, an N-type impurity is introduced into the portion where the collector region will be formed to form the low resistance collector region 11. In order to avoid thermal stress, the low resistance collector region 11 is actually obtained by ion-implanting phosphorus into a portion where the collector region is formed before forming the element isolation region 7. The ion implantation conditions are ³¹ P ⁺ , and the acceleration voltage is 40
The keV and dose amount are set to 5 × 10 ¹⁵ cm ⁻² (FIG. 2).

Next, a silicon nitride film (SiN _x ) 13 is formed on the entire surface of the substrate 1. Then, unnecessary portions of the nitride film 13 are removed. As a result, the nitride film 13 remains only on the low resistance collector region 11 and its periphery. This nitride film 13 is a mask material for preventing epitaxial growth on the collector when forming the base and the emitter. In this example, the thickness of the nitride film 13 was set to 50 nm (FIG. 3).

Next, only on the epitaxial layer 5, S
A compound of i and Ge is epitaxially grown. As a result, the single crystal SiGe layer 15-S is formed on the element forming portion (epitaxial layer 5). Then the SiGe layer 1
The N-type silicon layer 17 and the SiGe layer 1 are formed on the surface of 5-S.
Epitaxially grow continuously with 5-S. Further, a high concentration N ⁺ type silicon layer 19 is formed on the surface of the silicon layer 17.
Are continuously epitaxially grown with the silicon layer 17. The germanium (Ge) content of the SiGe layer 15-S is 10%, the impurity added is boron (B), and its concentration is 1
It is × 10 ¹⁹ cm ^-3 . The thickness of the SiGe layer 15-S was set to 50 nm. In the SiGe layer 15-S, the germanium concentration and the impurity concentration may be graded if necessary. That is, the impurity concentration is set to the SiGe layer 1
For example, the concentration is not uniform over the entire 5-S, the concentration is low at the interface with the epitaxial layer 5, and the concentration is gradually increased as it grows. Alternatively, conversely, the concentration may be increased at the interface with the epitaxial layer 5 and gradually decreased as it grows. Moreover, the thickness of the SiGe layer 15-S is appropriately set according to the breakdown voltage of the transistor.
In this embodiment, the added impurity in the silicon layer 17 is phosphorus (P) and its concentration is 1 × 10 ¹⁷ cm ⁻³ . The thickness of the silicon layer 17 was 200 nm. Since the high-concentration silicon layer 19 functions as an electrode of the emitter, it is preferable that the high-concentration silicon layer 19 has a sufficiently low resistance. In this embodiment, the impurity added to the high-concentration silicon layer 19 is phosphorus (P), and its concentration is 1 × 10 ¹⁹ cm ⁻³ . The thickness of the high concentration silicon layer 19 was 400 nm.
After the SiGe layer 15-S, the silicon layer 17, and the high-concentration silicon layer 19 are continuously epitaxially grown, silicon dioxide is deposited on the entire surface of the substrate 1 by the CVD method to obtain a silicon oxide film 21 ( (Fig. 4).

Next, the oxide film 21 and the high-concentration silicon layer 1
9 and the unnecessary portions of the silicon layer 17 are removed. As a result, the oxide film 21, the high-concentration silicon layer 19, and the silicon layer 17 remain only in the emitter formation region and its periphery. At this time, the silicon layer 17 is not completely removed but some remains on the SiGe layer 15-S. The silicon layer 17 is intentionally left in order to remove the damage of the SiGe layer 15-S, the emitter region, and the interface side wall portions thereof. Incidentally, in this embodiment, the oxide film 21, the high-concentration silicon layer 19, and the silicon layer 17 are removed by using anisotropic etching such as RIE (FIG. 5).

Next, the part of the silicon layer 17 that has been intentionally left is completely removed to obtain an emitter structure 23 composed of the silicon layer 17 and the high-concentration silicon layer 19. Wet etching is used for removal at this time.
In wet etching, an etching solution in which hydrofluoric acid and nitric acid are mixed is usually used. However, since an etching selection ratio of Si and SiGe cannot be obtained with this type of etching solution, in the present embodiment, the propanol is used. And an etching solution containing potassium dichromate was used. As a result, even if the required over etching is performed, the SiGe layer 15
-S does not disappear. Further, by this wet etching, the damages of the SiGe layer 15-S, the emitter region, and the interface side wall portion of these generated by the anisotropic etching in the step described with reference to FIG. 5 are removed (FIG. 6). ).

Next, silicon dioxide is deposited on the entire surface of the substrate 1 by the CVD method to obtain a silicon oxide film 25. In this embodiment, the thickness of the oxide film 25 is set to 300 nm. The oxide film 25 serves as a spacer for separating the emitter region and the base region when the electrode is completed (FIG. 7).

Next, the entire surface of the oxide film 25 is etched by anisotropic etching such as RIE. This allows
The oxide film 25 remains only on the side wall of the emitter structure 23. The remaining oxide film 25 functions as a spacer for separating the emitter region and the base region. By the etching at this time, the oxide film 21 left on the emitter structure 23 and the nitride film 13 left on the low resistance collector region 11 are also removed (FIG. 8).

Next, silicon is deposited on the entire surface of the substrate 1 by the CVD method to obtain a P-type polysilicon layer 27,
A silicon nitride film (Si
N _X ) 29 is obtained. The polysilicon layer 27 may be doped with P-type impurities such as boron at the time of deposition, or may be doped with P-type impurities such as boron after being formed by an ion implantation method or the like. In this embodiment, the polysilicon layer 27 has a thickness of 2
00 nm, the added impurity is boron, and the concentration is 1 ×
It was set to 10 ²⁰ cm ^-3 . The nitride film 29 functions as an etching mask in an etching process performed later. Further, in this embodiment, the film thickness of the nitride film 29 is set to 50 n.
It was set to m (Fig. 9).

Next, an unnecessary portion of the nitride film 29 is removed,
Only the nitride film 29 corresponding to the portion of the polysilicon layer 27 that will be the base extraction region is left (FIG. 10). Next, using the nitride film 29 as an etching mask, a selected portion of the polysilicon layer 27 is removed by an etching solution containing propanol and potassium dichromate. As a result, the base lead-out region constituted by the remaining polysilicon layer 27 is obtained (FIG. 11).

Next, the nitride film 29 is removed. Then, silicon dioxide is deposited on the entire surface of the substrate 1 by the CVD method to obtain a silicon oxide film 31. Then, the oxide film 31
The stepped portion that has occurred is buried with a resist. Next, the oxide film 31 and the resist are etched back under the condition that there is no difference in the etching rate between the embedded resist and silicon dioxide. Then, this etch back is performed until the surface of the emitter, that is, the surface of the high-concentration silicon layer 19 of the emitter structure 23 is exposed.
At this time, the oxide film 25 remaining on the side wall of the emitter structure 23 is also etched back, so that there is no step between the surface of the oxide film 25 and the surface of the oxide film 31. Therefore, the surface of the substrate 1 is covered with the interlayer insulating film which is composed of the oxide film 25 and the oxide film 31 and whose surface is flattened (FIG. 12).

Next, the polysilicon film 27 is formed on the oxide film 31.
To the base opening and the low resistance collector region 11
To form a collector opening reaching. Next, an aluminum (Al) layer is formed on the entire surface of the substrate 1, and this aluminum layer is patterned. As a result, the emitter wiring 33-E connected to the high-concentration silicon layer 19, the base wiring 33-B connected to the polysilicon layer 27 via the base opening, and the collector opening are provided. A collector wiring 33-C connected to the low resistance collector region 11 is obtained (FIG. 1).

According to the method of manufacturing the semiconductor device described in the above embodiment, the base and the emitter can be formed in a self-aligned manner. In particular, as in the steps described with reference to FIGS. 5 to 6, by etching unnecessary portions of the high-concentration silicon layer 19 and unnecessary portions of the silicon layer 17, high-concentration only in the emitter formation region portion. Silicon layer 19
And leaving the silicon layer 17. The remaining high-concentration silicon layer 19 and silicon layer 17 are the emitter structure 23.
Becomes That is, the emitter structure 23 is formed by one lithography process, and the width of the junction between the emitter and the base is determined by forming the emitter structure 23.
Also, the size of the emitter region is determined. As described above, since the width of the junction between the emitter and the base and the size of the emitter region are determined by one-time lithography, the capacitance between the base and the emitter is not unnecessarily increased.

Further, unlike the transistor structure shown in FIG. 1, since the base wiring 33-B does not overlap the emitter, that is, the high-concentration silicon layer 19 or the silicon layer 17, the capacitance between the base and the emitter is reduced. Can be made smaller.

As described above, the capacitance between the base and the emitter is reduced, which can contribute to speeding up of transistor operation. Although a compound of Si and Ge is used as a base material, SiGe which is relatively unstable crystallographically, as in the step described with reference to FIG.
On the layer 15-S, a silicon layer 17 and a high-concentration silicon layer 19 which will be emitter materials are successively formed. Therefore, the junction between the base and the emitter is not exposed, and the base
The junction between the emitter and the emitter can be obtained with high accuracy.

Further, as in the step described with reference to FIG. 6 in particular, the SiGe layer 15-S formed by the anisotropic etching in the step described with reference to FIG. Since the damage on the side wall is removed, the accuracy is further enhanced.

[0036]

As described above, according to the present invention, there is provided a method of manufacturing a semiconductor device in which the capacitance between the base and the emitter can be reduced and the junction between the base and the emitter can be obtained with high accuracy. it can.

[Brief description of drawings]

FIG. 1 is a sectional view showing a final shape of a transistor obtained by a method of manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a sectional view of a transistor in a main step of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a sectional view of a transistor in a main step of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a sectional view of a transistor in a main step of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 5 is a sectional view of a transistor in a main step of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 6 is a sectional view of a transistor in a main step of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 7 is a sectional view of a transistor in a main step of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 8 is a sectional view of a transistor in a main step of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 9 is a sectional view of a transistor in a main step of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 10 is a sectional view of a transistor in a main step of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 11 is a sectional view of a transistor in a main step of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 12 is a sectional view of a transistor in a main step of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 13 is a cross-sectional view showing a final shape of a transistor obtained by a conventional method for manufacturing a semiconductor device.

FIG. 14 is a sectional view of a transistor in a main step of a conventional method for manufacturing a semiconductor device.

FIG. 15 is a sectional view of a transistor in a main step of a conventional method for manufacturing a semiconductor device.

FIG. 16 is a sectional view of a transistor in a main step of a conventional method for manufacturing a semiconductor device.

FIG. 17 is a sectional view of a transistor in a main step of a conventional method for manufacturing a semiconductor device.

FIG. 18 is a cross-sectional view of a transistor in a main step of a conventional method for manufacturing a semiconductor device.

FIG. 19 is a sectional view of a transistor in a main step of a conventional method for manufacturing a semiconductor device.

FIG. 20 is a sectional view of a transistor in a main step of a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

1 ... P-type silicon substrate, 3 ... N-type buried region, 5 ... N-type epitaxial region, 7 ... Element isolation region, 9 ... Insulating region, 11
… Low resistance collector region, 13… Silicon nitride film, 15-S
... single crystal SiGe layer, 17 ... N-type silicon layer, 19 ... high-concentration N ⁺ silicon layer, 21 ... silicon oxide film, 23 ... emitter structure, 25 ... silicon oxide film, 27 ... P-type polysilicon layer, 29 ... Silicon nitride film, 31 ... Silicon oxide film, 33-B ... Base wiring, 33-E ... Emitter wiring, 3
3-C ... Collector wiring.

Claims (1)

[Claims] 1. A step of continuously forming, on a semiconductor substrate, a first semiconductor layer made of a first semiconductor and a second semiconductor layer made of a second semiconductor different from the first semiconductor. An unnecessary portion of the second semiconductor layer is removed by using the first semiconductor layer as an etching stopper to obtain an emitter structure, and a spacer formed on the sidewall of the emitter structure is an insulating film. Forming a conductive layer electrically connected to the first semiconductor layer; forming a base wiring layer electrically connected to the conductive layer; A step of forming an emitter wiring layer electrically connected to the second semiconductor layer.