JPH06337782A - Processor and method for data processing - Google Patents

Abstract

PURPOSE:To simplify a program by the use of M-bit instantaneous value data when data in an address space whose MS is '1' in a memory is accessed. CONSTITUTION:The data processor is equipped with a data register group 105a with N-bit width, an address register group 105b with N-bit width, a code expander 109 which expands M(M<N)-bit data into N-bit data, a zero expander 110 which expands M-bit data into N-bit data, a computing element which performs arithmetic processes according to instructions, an instruction decoding part 103 which decodes the instructions, and a control signal generation part 103a which sends a control signal for outputting the instantaneous value data to the zero expander 110 when an instruction includes the M-bit instantaneous value data and is data to access the address register group 105b and to the code expander 109 when the data is data to access the data register group 105a.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device and a data processing method for executing a process in accordance with a program instruction, and particularly to immediate data (immediate address) for designating an address in an address space for accessing a memory. The present invention relates to a data processing device and a data processing method capable of optimizing designation processing or arithmetic processing.

[0002]

2. Description of the Related Art Generally, a data processing device such as a microcomputer is configured to process data having various data widths. For example, for immediate data whose numerical value is directly designated by a program instruction, a predetermined arithmetic process is performed after the data width is adjusted by the sign extension process.

The structure and operation of the data processing apparatus which involves sign extension processing for this immediate data will be described below. An example of a conventional data processing device having a sign extension function for immediate data is "Microcomputer Series 14".
68000 microcomputer "Yuda Kida et al., Maruzen, March 1983". Fig. 7 is a block diagram showing the configuration of this conventional data processing apparatus.
In FIG. 11, 11 is an N (integer) bit width data register group that mainly stores data, 12 is an N bit width address register group that mainly stores addresses, and 13 is a sign extension of the most significant bit of 16 bit data. A code extender for outputting as 32-bit data, 14 is an instruction decoding unit for decoding an instruction, and 15 is an arithmetic unit for executing an operation based on the decoding result of the instruction decoding unit 14.

The general operation of this conventional data processing apparatus will be described below. First, the instruction decoding unit 14 decodes an instruction given from the outside. Then, the following operation is performed depending on the content of the instruction. (1) When the instruction is “to store data between the data registers 11 or the address registers 12 or to operate”.

Two N-bit wide data are input to the arithmetic unit 15, a predetermined arithmetic operation is performed, and the data is stored in a designated register. (2) When the instruction is "store M-bit immediate data in the data register 11 or the address register 12 or perform an operation". The M-bit immediate data is code extender 13
Is expanded to N bits and becomes one input of the arithmetic unit 15 to perform a predetermined arithmetic operation and then output to a designated register.

Now, the operation of the code extender 13 will be described with reference to FIG. First, in FIG. 5A, when the most significant bit of the numerical value represented by M bits is 0, 0 is copied to N bits up to the upper side to expand the data width. Further, in FIG. 5B, if the most significant bit of the numerical value represented by M bits is 1, then up to N bits are incremented by 1
To extend the data width.

Further, in this conventional data processing apparatus, the operation of processing immediate data will be specifically described, particularly when the bit width of immediate data is shorter than the bit width of the register to be stored or operated. As an example, the operation of executing the program shown in FIG. 8 will be described. The program shown in FIG. 8 is a memory stored in H'10 (H 'indicates hexadecimal notation) to H'8100 in H'10 units in the entire space addressed by 32 bits. The process of sequentially adding the above 16 data and writing the sum to the address H'10000000 is shown. FIG. 9 shows a processing flow of the program represented by the mnemonic notation in FIG. Further, FIG. 10 schematically shows the address space of the memory. Hereinafter, description will be made with reference to FIGS. 7 to 10. In addition,
In the following description, the sign extension process of the immediate data shows a case where the normal extension process is performed, and the problem in the actual sign extension process will be described later. Instruction (1): Clear the data register D0. Instruction (2): 32-bit immediate data H'8000 is set in the address register A0.

The notation of this instruction uses 16-bit immediate data H'8000. Therefore, this immediate data H'8000 is sign-extended to 32-bit data by the sign extender 13 and then stored in the address register A0. Instruction (3): The content of the address specified by the address register A0 is read from the memory and stored in the data register D1. Instruction (4): The content of the data register D1 is added to the content of the data register D0, and the result is added to the data register D0.
To store. Instruction (5): Immediate value H'0010 in the address register A0
Is added and stored in the address register A0.

The 16-bit immediate data H'0010 is converted into 32-bit data H'00000 by the code extender 13.
Extended to 010. After that, the address data H ′ stored in the address register A0 in the arithmetic unit 15
Expanded data H'000000 with 00008000
10 is added to calculate H'00008010. This calculated data is stored in the address register A0. Command (6): Above calculated data and immediate data H'810
Compare with 0.

Immediate data H'8100 is code extender 13
The data is sign-extended to 32-bit data by and output to the calculator 15. Then, in the arithmetic unit 15, the address data H ′ read from the address register A0
Compared with 00008010. Command (7): Label A if smaller based on the comparison result
Return to the instruction (3) indicated by, and if equal or larger, it is determined to proceed to the instruction (8).

In the loop processing described by the instructions (3) to (7), the value of the address register A0 is H'0000.
Since it starts from 8000 and is updated by H'00000010 and is repeated until H'00008100, 1
After the addition result of 6 times is stored in the data register D0,
Go to instruction (8). Instruction (8): The contents of data register D0 are stored in memory H '
Store at address 10000000.

[0012]

However, in the above conventional data processor, the address register 1 is used.
The sign extension performed on the immediate data accessed for 2 may result in data different from the content of the specified immediate data. Explaining such a state with the example shown in FIG. 8, the immediate data to be sign-extended is H'8000 in the instruction (2), H'0010 in the instruction (5), and H'8100 in the instruction (6). Is.

First, the immediate data H'in the instruction (2)
When the code extension of 8000 is performed, the most significant bit “1” is copied to the high-order side, and therefore it is extended to H′FFFF8000 instead of H′00008000. Therefore,
The data stored in the address register A0 in the above instruction (2) is not H'00008000, but H'00008000.
It becomes FFFF8000. Therefore, as shown in FIG. 10, in the next instruction (3), the data read from the memory is not the data at the address H'00080000 but the data at the address H'FFFF8000. Therefore, erroneous data is read.

Also in the instruction (6), if the immediate data H'8100 is sign-extended, H'0000810
It is extended to H'FFFF8100 instead of 0. Therefore, incorrect calculation is performed. Such an erroneous extension of immediate data causes the immediate data to have an MSB (most significant bit) value of "in the entire address space of the memory" as shown in FIG.
It occurs when an address of 1 "is specified.

In order to eliminate such a situation, it is considered that the designation of immediate data is represented by 32 bits.
For example, in the instruction (2), the immediate data is H'00.
It may be specified as 008000. However, such a designation method is not preferable because it requires a 32-bit notation even when 16-bit data is specified, resulting in a long instruction notation and object code.

In order to solve such a problem, 16
A method of rewriting the program shown in FIG. 8 using bit immediate data is shown in FIG. In FIG.
The instruction corresponding to the instruction (2) shown in FIG. 8 is executed in two steps of the instructions (2-1) and (2-2). First, the immediate data H'8000 given by the instruction (2-1) is sign-extended to H'FFFF8000. Then, in the instruction (2-2), the upper 16 bits of the extension data are set to 0.
Extension data H'0000FFFF to clear
And H'0000FFFF are ANDed and converted into 32-bit data H'00008000.

The instruction corresponding to the instruction (6) in FIG. 8 is the instruction (6-1), (6-2), (6) in FIG.
-It is done in 3 steps of 3). The immediate data H'8100 given by the instruction (6-1) is sign-extended to H '
It becomes FFFF8100 and is stored in the address register A1. Next, in the instruction (6-2), the upper 1 of the extension data
In order to clear 6 bits to 0, the extension data H'F
The logical product of FFF8100 and H'0000FFFF is obtained and converted into 32-bit data H'00008100.
After that, in the instruction (6-3), the address register A
0 is compared with A1.

However, although this method can use 16-bit immediate data, it has a new problem that the number of steps of the program is increased as compared with the method shown in FIG. As described above, the two conventional examples efficiently execute the program instruction for accurately accessing the data in the address space of the memory by using the immediate data shorter than the data width of the address register. It had a problem that it could not.

Therefore, the present invention has been made to solve the above-mentioned problems, and when accessing data in an address space within a range of 2 M from the head of the entire address space, the address An object of the present invention is to provide a data processing device and a data processing method capable of giving data shorter than the data width of a register as immediate data.

[0020]

According to a first aspect of the present invention, there is provided a data processing device including a first register having an integer N-bit width, a second register having an N-bit width, and M (integer) bits smaller than N. A sign extender that extends the data width of M-bit data to N bits by copying the most significant bit of the data to the upper side, and a data width of M-bit data by generating a zero value on the upper side of the M-bit data. Is extended to N bits, an arithmetic unit for performing arithmetic processing in accordance with a given instruction, an instruction is decoded, and the instruction includes M-bit immediate data, and has a storage processing for the first register, When the immediate data is output to the zero extender, the instruction includes the M-bit immediate data, and the storing process for the second register is performed, the immediate data is output to the sign extender. First register to force, and a command control means for controlling the second register and arithmetic unit.

A data processing apparatus according to the invention of claim 2 is
According to the first aspect of the invention, the first register is an address register that stores the address data of the memory, and the second register is a data register that stores the data operand of the instruction. In the data processor according to the invention of claim 3, in addition to the invention of claim 1, the instruction control means decodes immediate data of a power of 2.

The data processing method according to the invention of claim 4 is
A method of performing a predetermined operation according to an instruction specifying immediate data having an integer M-bit width smaller than N, which accesses the first and second registers having an integer N-bit width, by decoding the instruction and designating the instruction When the instruction decoding step of determining the access destination register and the storage processing for the first register are performed, the immediate data of the M-bit width is zero-extended to be extended to the N-bit width of the data, and the instruction is transmitted to the second register. In the case of having a storage process, the data expansion step of expanding the immediate data of M bit width to the data of N bit width by sign expansion and the immediate data expanded to N bit width are used to perform a predetermined arithmetic process according to the instruction. And a calculation step to be performed.

The data processing method according to the invention of claim 5 is
According to the fourth aspect of the invention, the first register is an address register that stores the address data of the memory, and the second register is a data register that stores the data operand of the instruction. The data processing method according to the invention of claim 6 is the same as that of the invention of claim 4, in which the bit width M of immediate data is M.
Is specified by a power of 2.

[0024]

In the inventions of claims 1 to 6, the instruction control means decodes an instruction including immediate data. And
If the immediate data is the data accessed to the first register, the immediate data is output to the zero extender. If the immediate data is the data accessed to the second register, the immediate data is output to the code extender. The zero extender and the sign extender perform zero extension and sign extension processing on the given immediate data, respectively,
Immediate data having an M-bit width is expanded to data having an N-bit width. After that, the arithmetic unit uses the expanded immediate data to perform a predetermined arithmetic process.

[0025]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of a data processing device according to an embodiment of the present invention, and FIG. 2 is a detailed block diagram thereof. 1 and 2, the data processing device includes a bus transfer control unit 101 that controls external instruction and data transfer, an instruction fetch unit 102 that controls an instruction read operation, and an instruction decoding unit 103 that decodes an instruction. , Arithmetic unit 10 for performing 32-bit wide data operation
4, a register 105 that stores data used by the arithmetic unit 104, a program state word 106 that stores a flag group set based on the arithmetic result of the arithmetic unit 104,
In the case of a branch instruction, a branch determination unit 107 that determines whether the condition is met or not, a program counter 108 that stores the instruction address being executed, and the most significant bit of 16-bit input data are sign-extended and output as 32-bit data. Sign extender 109 and upper side 1 of 16-bit input data
A zero extender 110 that generates a value of zero for 6 bits and extends the value to 32 bits is provided.

The register 105 includes a data register group 105a composed of eight registers D0 to D7 each having a 32-bit width for mainly storing data, and seven registers A0 to A6 each having a 32-bit width for mainly storing address data. Address register group 105b. The operation of the data processing device configured as described above will be described. Note that FIG. 3 mainly shows the processing flow of the instruction decoding unit 103.

First, the instruction fetch unit 102 activates the bus transfer control unit 101 to sequentially read the instructions of the program stored in the external ROM or the like. The instruction of the read program is output to the instruction decoding unit 103 via the instruction fetch unit 102. Referring to FIG. 3, the instruction decoding unit 10
3 decodes the read instruction (step S1)
0). In the instruction decoding operation, arithmetic operation, logical operation,
The operation code and data indicating the type of instruction such as transfer between registers, memory, and branch, immediate data, register number, operation number (operand) such as memory address are decoded. According to the result of the decoding, it is determined whether or not this instruction specifies immediate data having a bit width shorter than 32 bits (step S20). If immediate data having a short bit width is designated, the process proceeds to the next step S30, and if not, the process proceeds to step S40.

When immediate data having a short data width is detected, it is determined whether the access destination register (destination register) designated by this instruction is in the data register group 105a or the address register group 105b (step S30). . Further, the control signal generator 103a
Outputs a control signal to the arithmetic unit 104, the code extender 109, and the zero extender 110 according to the content of the decoded instruction and the type of the register of the access destination (step S40).

Here, the processing operation of the data processing device will be described for each instruction content. (1) In the case of a "data transfer between registers belonging to data register group 105a or address register group 105b or operation of data stored in these registers" instruction. (For example, "MOVE D0, D1" or "AD
In the former case, the N-bit width data read from the source register is stored in the designated register (destination register).

In the latter case, the two data of N-bit width read from the predetermined register are input to the arithmetic unit 104, and after the predetermined arithmetic operation is performed, the data are stored in the designated register. (2) “M-bit immediate data is transferred to the data register group 10
5a, store or operate ”. (For example, "MOVI # H'0010, D0" or "ADDI
# H'0010, D0 ", etc.) In the former case, the instruction decoding unit 103 decodes that the instruction specifies immediate data having an M-bit width, and the destination register is the data register group 105a. The M-bit width immediate data is expanded to an N-bit width by the sign extender 109 and stored in the designated data register.

In the latter case, similarly to the above, the M-bit width immediate data is expanded to the N-bit width by the sign extender 109 and input to one of the arithmetic units 104. Then, after a predetermined calculation is performed, the data is output to the designated data register. (3) “M-bit immediate data is transferred to address register group 1
Command stored in 05b or operated ". (For example, "MOVI # H'0010, A0" or "ADD
I # H'0010, A0 ") In the former case, the instruction decoding unit 103 decodes that the instruction specifies M-bit immediate data and the destination register is the address register group 105b. The immediate data of M-bit width is expanded to N-bit width by the zero extender 110 and output to the designated address register.

In the latter case, similarly, immediate data of M-bit width is zero-extended to N-bit width by the zero extender 110 and input to one of the arithmetic units 104. Then, after a predetermined calculation is performed, it is output to the designated address register group 105b. Here, the operation of the zero extender 110 will be described with reference to FIG. The zero extender 110 generates and extends 0 to N bits to the upper side regardless of whether the most significant bit of the numerical value represented by M bits is 0 or 1.

Further, the data processing apparatus according to this embodiment will be described in particular with reference to a specific example of the processing operation of M-bit width immediate data. As an example, the operation of executing a program having the same content as that used to describe the conventional apparatus will be described. FIG. 6 is a conventional example shown in FIG. 8 and FIG.
The program corresponding to 1 is shown. When the contents of this program are rewritten, as shown in FIG. 10, from the address H'8000 (H 'indicates hexadecimal notation) to the address H'8100 in the entire address space of the memory addressed by 32 bits. Up to 16 data in the memory stored at every H'10 address are sequentially added, and the sum is written to the H'10000000 address. Hereinafter, description will be given with reference to FIGS. 1 to 5 according to FIG. Instruction (1): Clear the data register D0. Instruction (2): Set 32-bit immediate data H'00008000 in the address register A0.

Referring to FIG. 3, the instruction decoding unit 103 decodes this instruction (step S10). Then, it is determined that the immediate data H'8000 in 16-bit notation is used (step S20). Further, it is determined that the instruction is a data storage instruction to the address register group 105b (step S30). Therefore, the instruction decoding unit 103
Is generated by the control signal generator 103a.
A control signal is issued to 0 (step S40). The zero extender 110 converts the 16-bit immediate data H'8000 into 32-bit data H'00008000 according to the control signal.
Zero-extend to and load address register A0. Instruction (3): Store the contents of the memory specified by the address register A0 in the data register D1. Instruction (4): Add the data stored in the data register D1 to the data stored in the data register D0, and store in the data register D0. Instruction (5): Immediate data H'0010 is added to the data stored in the address register A0 and the result is stored in the address register A0.

This instruction is 16-bit immediate data H'0.
I am using 010. Then, the address register A0
To store data in. Therefore, the instruction decoding unit 103 first issues a control signal to the zero extender 110 by the control signal generation unit 103a. Zero extender 110
Is 16-bit immediate data H'00 according to the control signal.
10 is zero-extended to 32-bit data H'00000010 and output to one of the arithmetic units 104.

Upon receiving the control signal from the control signal generator 103a, the address register A0 reads the stored data H'00008000 and outputs it to the other of the arithmetic units 104. Further, the arithmetic unit 104 receives the two input 32-bit data (H'00008000, H ').
00000010) is added and the addition result is stored in the address register A0. Command (6): Above calculated data and immediate data H'810
Compare with 0.

This instruction is 16-bit immediate data H '.
I am using 8100. And the address register A
Instructed to compare with 0 data. Therefore, the control signal generator 103a first issues a control signal to the zero extender 110. The zero extender 110 outputs 1 according to the control signal.
The 6-bit immediate data H'8100 is zero-extended to the 32-bit data H'00008100 and output to one of the arithmetic units 104.

The address register 105b receives the control signal from the control signal generator 103a, and stores the data (H'00008010) stored in the address register A0.
Is read out and output to the other side of the arithmetic unit 104. The arithmetic unit 104 compares the two input 32-bit data. Command (7): Label A if smaller based on the comparison result
Return to the instruction (3) indicated by, and if equal or larger, it is determined to proceed to the instruction (8).

In the loop processing described by the instructions (3) to (7), the value of the address register A0 is H'0000.
It starts from 8000, is updated by H'00000010, and is repeated until it becomes H'00008100. For this reason, after the addition result of 16 times is stored in the data register D0, the operation proceeds to the instruction (8). Instruction (8): The contents of data register D0 are stored in memory H '
Store at address 10000000.

As described above, the immediate data used in the instruction (2) and the instruction (6) are the address data in the address space of 2 16 to the 1st power of the memory shown in FIG.
It can be specified in 6-bit notation. Because of this, 3
Compared with the conventional example which requires 2-bit notation, the description of immediate data in each of the two steps of instructions (2) and (6) is shortened by 2 bytes (16 bits). As a result, in the case of the program of the above example, the program size can be reduced by 4 bytes as compared with the conventional example.

Further, in a data processing device having a structure in which instructions and data are accessed on the same bus, the program size is reduced by bus access for instruction acquisition and bus access for data access accompanying instruction execution. Contention is reduced, which can contribute to improvement in execution speed. In the above embodiment, the processing of 16-bit immediate data is described with respect to the data processing device having the 32-bit address register, but the present invention is not limited to this example, and N of 16, 32, etc.
For an address register capable of storing bit data, it can be applied to processing of immediate data of M (M <N) bits such as 4, 8, and 16 bits.

[0042]

As described above, according to the present invention, when an instruction including immediate data is given, either zero extension or sign extension is discriminated according to the type of the register to be accessed by the immediate data. Since it is configured to perform predetermined arithmetic processing after data expansion by means of data expansion, as immediate data for accessing data in the MSB of the entire address space represented by N bits in the address space of "1", N
It is possible to specify smaller M-bit immediate data. This simplifies the notation of immediate data and reduces the program size.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a data processing device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a main part of the data processing device shown in FIG.

FIG. 3 is an instruction decoding unit 103 of the data processing apparatus of this embodiment.
It is a processing flow diagram showing the processing of.

FIG. 4 is an explanatory diagram conceptually showing the operation of the zero extender.

FIG. 5 is an explanatory diagram conceptually showing the operation of the code extender.

FIG. 6 is an explanatory diagram showing an example of a program used in the data processing device of this embodiment.

FIG. 7 is a block diagram showing a configuration of a conventional data processing device in a first example.

8 is an explanatory diagram showing an example of a program used in the conventional data processing device shown in FIG.

9 is a flowchart illustrating the operation of the program shown in FIG.

FIG. 10 is an explanatory diagram schematically showing a memory space used by the data processing device.

FIG. 11 is an explanatory diagram showing a program example according to a second conventional example.

[Explanation of symbols]

 103 Instruction Decoding Unit 103a Control Signal Generating Unit 104 Arithmetic Unit 105 Register 105a Data Register Group 105b Address Register Group 109 Code Extender 110 Zero Extender

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Claims (6)

[Claims] 1. A data processing device for performing a predetermined data operation according to an instruction designating immediate data, comprising: a first register having an integer N-bit width, a second register having an N-bit width, and M smaller than N. A sign extender for extending the data width of the M-bit data to N bits by copying the most significant bit of the (integer) bit data to the upper side; and a zero extender for generating a zero value on the upper side of the M-bit data. A zero extender that extends the data width of M-bit data to N bits; an arithmetic unit that performs arithmetic processing according to a given instruction; an instruction that decodes the instruction, and the instruction includes M-bit immediate data; In the case of having a storage process for a register, the immediate data is output to the zero extender, the instruction includes M-bit immediate data, and the second register A data processing device comprising: instruction storing means for controlling the first register, the second register, and the arithmetic unit so as to output the immediate data to the sign extender when the data processing is performed. 2. The data processing apparatus according to claim 1, wherein the first register is an address register that stores address data of a memory, and the second register is a data register that stores a data operand of the instruction. . 3. The data processing device according to claim 1, wherein the instruction control means decodes immediate data of a power of two. 4. A data processing method for performing a predetermined operation according to an instruction designating immediate data having an integer M bit width smaller than N, which accesses the first and second registers having an integer N bit width. An instruction decoding step of decoding and discriminating an access destination register designated by the instruction; and, if the instruction has a storing process for the first register, N-bit wide data by zero-extending the immediate data of M-bit width And the instruction has a storing process for the second register, the data expansion step of expanding the immediate data of M bit width to data of N bit width by sign extension, and expanding to N bit width. And a calculation step of performing a predetermined calculation process according to the instruction using the immediate data. 5. The data processing method according to claim 5, wherein the first register is an address register that stores address data of a memory, and the second register is a data register that stores a data operand of the instruction. . 6. The data processing method according to claim 4, wherein the bit width M of the immediate data is designated by a power of 2.