JPS5951070B2 - address translation device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a device that converts a logical address into a real address using a segment table that allows indirect specification.

In a system that performs segmentation, the translation from a logical address to a real address is, for example, the first
This is done using an algorithm as shown in the figure.

In other words, using the J table pointer defined in the system, the J table (JTP+
The task description block θ is obtained by indexing the P table (PTP+P×4 address) and the P table (PTP+P×4 address).

The task description block describes all the operating environments of the corresponding task, and one entry therein stores an STO, that is, a segment table orilink that defines the logical space and real space of the task. Here, logical address within the task! 5 is given, the STWAP (segment table word array pointer) in the segment table orilink and the upper 4 bits of the logical address
(S part), one entry of the segment word array is obtained (STWAP+S×4 address). Next, one entry in the segment table is obtained using the STP (segment table pointer) in the entry and the E part of the logical address (STP+E x 8 addresses). Information BASE (segment base) in this entry is the base address of the segment corresponding to the desired logical address, and the desired real address is BASE+D address. There are various joining points for such segmentation, including "segment sharing" and "segment combination."

Both of these are tetanic, which allows the same segment to be referenced between multiple different tasks, and the former prepares a shared segment table as shown in Figure 2, and S0=
The segment table word array is configured so that the same segment base BASEo is obtained when S1 and tile=E1 are given.

The latter, as shown in Figure 3, configures a completely independent segment table word array and segment table for each task, and specifies other segment table entries to be combined with a specific segment table entry, so-called indirect specification. In this case, generally different S and E can access the same segment. In devices that use the so-called virtual memory method that requires conversion from logical addresses to real addresses, three devices are generally used to reduce the overhead of accessing the storage device for the conversion. It has an address translation register inside.

The address conversion register holds a large number of pairs of logical addresses and corresponding real addresses, and when given a logical address, outputs a real address paired with a matching logical address. An example of the logical configuration of this address 3 conversion table in the prior art is shown in FIG. In a device having an address conversion register as described above, for example, an instruction having a segment table rewriting function of the type shown in Table 1 below, provided that the first segment table entry specified by the contents of 1GRγ2 (indirect specification) Consider the case where an instruction is executed to rewrite the

In this case, if the corresponding segment is registered in the address translation register, it must be invalidated. However, for completely independent segments (not shared or combined), the G specified by the instruction
J, P of the contents of R(γ2). S. E and the logic parts J, P.E of the address translation register. S. For the shared segment shown in FIG. 2, all fields of S. It is sufficient to invalidate all entries whose E fields match each other. but,
When the entry of the directly specified segment (tasks J1, P1, space in FIG. 3) of the combined type segment shown in FIG. 3 is rewritten, the address translation register in the J1P1 space in FIG. Those registered in Task J can be invalidated in the same way as the independent or shared segments. Since it is not possible to know the pairs registered in the Po space, you can either invalidate all pairs, or create a management table for shared and combined segments by a program, and use a separate address translation register to invalidate the pairs. was carrying out orders. An object of the present invention is to change the segment table entry specified by the indirect specification segment without invalidating all entries in the address translation register, and without requiring the management of shared/combined segments by a program. The present invention provides a device that can reduce the overhead in terms of hardware performance and software design by invalidating the minimum necessary entries in the address translation register. In the address translation device according to the present invention, an indirect specification segment table entry is used in the address translation process for the pair of the logical address held by the address translation register and the real address, for example, as shown in FIG. The indirect display bit I that indicates whether the indirectly specified segment table entry has been used multiple times, the multiple display bit U that indicates whether the indirectly specified segment table entry has been used multiple times, and the real address LOC of the directly specified segment table entry are held. When an instruction (for example, Table 1) that changes the contents of a segment table entry in the format is executed, it invalidates the corresponding segment pair in the address translation register, and also invalidates the above indirection for all entries in the address translation register. Checks the display bit, the display multiple bit, and the real address of the segment table entry, and determines whether indirect specification is used multiple times,
In addition, the above-mentioned drawbacks are solved by indirectly specifying once and by invalidating all pairs in which the real address of the specified segment table entry matches according to the real address of the segment table entry and the command.

The device of the present invention includes a segment table having a plurality of pairs of segment table entries each having at least a pair of control information indicating direct or indirect specification and a real address in one storage location indicated corresponding to a logical address; If the control information in the segment table entry specified by the logical address indicates indirect designation, the real address in the segment table entry specifies a further segment table entry, and the real address in the segment table entry specifies a further segment table entry. address conversion means for repeatedly reading until the control information indicates direct specification, and outputting the real address of the segment table entry and the real address in the segment table entry when the control information indicates direct specification; It has a plurality of conversion pairs with real addresses corresponding to the logical addresses converted by the address conversion means, and it is determined whether or not indirect designation was used in the conversion process by the address conversion means for each of the conversion pairs. an indirect display bit to display, a multiple display bit to display whether the indirect designation has been used more than once, and a real address of the directly designated segment table entry that is an output of the address conversion means;
and a validity indicator bit indicating the validity of each translation pair specified by an instruction when executing an instruction to update the segment table entry specified by the logical address. At the same time, the validity display bit of the address translation register corresponding to the logical address is updated, and the indirect display bit indicates indirect designation for all entries in the address translation register. , and invalidate all validity display bits of translation registers whose multiple display bit indicates multiple times or where the real address of the segment table entry matches the real address of the segment table entry specified by the instruction. It is characterized by

Next, one embodiment of the present invention will be described using FIG. 6. However, the segment table entry rewriting instruction shown in Table 1 is set in the instruction register ISR2 in the figure, and the logic part 12 and real part 13 of the address translation register 11 have the same configuration as shown in FIG. can be,
Furthermore, the address conversion circuit 14 uses the register (TSR) 1 that holds the task name JP to convert a logical address into a real address according to the algorithms shown in FIGS. 1, 2, and 3.

First, a case in which the normal storage device 19 is referred to will be explained.

In this case, specify the operation such as read/write to the storage device as request information in the request register 7, the logical address attached to the request in the logical address register 9, and if the request specifies a write operation, write the attached write data. Set in write data register 10,
The task register 1 is selected by the task name switching gate 8, the address conversion circuit 14 and the logic section 12 of the address conversion register 11 are indexed, and the logical and logical address items J.
P. S. If there is an entry matching BASE.E, BASE.E in the corresponding entry in the real part 13. CONT.
At the same time as reading SIZE, the adder 15 adds the value of logical address D and the above BASE, sets the result in the real address register 17, and also reads CONT and S.
IZE is checked in the address conversion circuit 14. However, this CONT. Checking SIZE is essentially unrelated to the present invention, so its explanation will be omitted. Further, if there is no matching entry in the address translation register 12, the address translation circuit 14 performs the steps shown in FIG.
The directly specified segment table entry corresponding to the specified logical address is obtained by performing address conversion according to FIGS. 2 and 3, and for one entry of the address conversion register 12 that is uniquely determined by a certain algorithm, Information J shown in FIG. P. S. E. V=1
,■,U. The logic part of LOC and BASE. JCONT.
Register the real part of SIZE. However, as mentioned above, information
．． P. S and E are given by task register 1 and logical address register 9, V is a valid indication bit that indicates the validity of the entry and is set to 1, and I is an indirect specification bit in the above address conversion process. The value is 1 when a segment is referenced, U is 1 when the indirectly specified segment is referenced multiple times, LOC is given as the real address of the directly specified segment table entry that was last referenced, and BASE. SIZE is given the value of the corresponding field in the final directly specified segment table entry, and CONT is given the value that is a combination of the control information fields in the segment table entries referenced throughout the process.

When a pair of a corresponding logical address and a real address is registered in the address conversion register 11 in this manner, the real address is determined in the same manner as in the case where a matching entry exists as described above. When the real address is stored in the real address register 17 as described above, the contents of the write-est register 7 are stored in the memory write-est register 16, and the contents of the write data register 10 are transferred to the memory write data register 18.
are set respectively, and an access request is sent to the storage device 19.

Next, the operation when the instruction to rewrite the segment table entry shown in Table 1 is executed will be described.

When an instruction word is read into the instruction register 2, the instruction code (0P field) is first decoded by the decoder 3, and a request code for rewriting the segment table entry is set in the request register.

Next, the first word of the segment table entry storage data is read out from the general-purpose register 6 through the switching circuit 5 and set in the write data register 10 according to the value of the γ1 field. If the write data register 10 is two words long, the value of the γ1 field is further incremented by 1 by the adder 4, and the second word of the segment table entry stored data is read out from the general-purpose register 6 by the switching circuit 5. Set to 1 word. Next, from the γ2 field of the instruction register 2, one word specifying the segment table entry is read from the general-purpose register 6 through the switching circuit 5, and its S and E fields are set to the corresponding fields of the logical address register 9, and the other fields are set to O. do. The request prepared in this way is sent to the address translation circuit 14 and the address translation register 11, but at this time, the JP field designated by the segment table entry, which has been read out from the general-purpose register 6, is sent to the address translation circuit 8 through the switching circuit 8. The signal is sent to circuit 14. Upon receiving the above request, the address translation circuit 14 first indexes all the entries in the address translation register 11 and sets the validity indicating bit (2) of the matching entry in the S and E fields to O.

This includes the shared cement, and the specified logical item S
This is to invalidate the pair corresponding to ,E. Next, the validity display bit V of the entry whose indirect display bit I is 1 and whose multiple display bit U is 1 is set to O. This is a segment in which indirect designation has been used multiple times, and since any segment table entry may be changed by this command, it is invalidated. Next, the segment designation S. is sent from the logical address register 9 and the general-purpose register 6 via the switching circuit 8. E and task name JP
Then, the address conversion circuit 14 calculates the real address of the segment table entry (the segment table entry sought first, which can be either a directly designated segment or an indirectly designated segment) according to the algorithm shown in FIG. The result is set in the real address register 17, and all entries in the address translation register 1 are indexed 5, and the content of the LOC1 field of the entry where the indirect display bit I is 1 and the multiple display bit U is O, and the above calculation is performed. The real address of the segment table entry entered is compared with the real address of the segment table entry, and the validity indicator bit V of the matched entry is set to O. This is to invalidate the corresponding pair since the contents of the segment table entry specified by the indirectly specified segment have been changed. Next, the write instruction information of the request register 7 is set in the memory write request register 16, the contents of the write data register 10 are set in the memory write data register 18, and a write request is sent to the storage device 19.

By implementing the above configuration, it is possible to invalidate indirectly specified segments without any contradiction, and ``For segments that are indirectly specified only once, only the minimum number of corresponding pairs can be invalidated.'' .

As explained above, the present invention provides indirect display bits for each entry of the address translation register, so that
There is no need to uniformly invalidate all entries in the address translation register when changing a segment table entry, and by having multiple specification display bits and the segment table entry real address of the directly specified segment, it is possible to change the address for only one indirectly specified segment. Only the relevant entry can be invalidated, which has the effect of reducing unnecessary invalidation of address translation registers.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the correspondence between logical addresses and real addresses (including task names) in the information processing device according to the present invention, and Figure 2 shows how segments are shared between two different tasks. FIG. 3 shows a case where segments are combined between two tasks. Further, FIG. 4 shows the configuration of an address translation register in the prior art, FIG. 5 shows an address translation register configured according to the technology of the present invention, and FIG. 6 shows an embodiment of the present invention. An example is shown in partial block diagram form. ]...Task register, 2...
Instruction register, 3... Decoder, 4...
・Adder, 5...Switching circuit, 6...
General-purpose register, 7...Request register, 8
...Switching circuit, 9...Logical address register, 10...Write data register, 1
1...Address conversion register, 12...
・Logic part, 13... Real part, 14... Address conversion circuit, 15... Adder, 16...
...Memory request register, 17...Real address register, 18...Memory write data register, 19...Storage device, 20...
...J table pointer, 21...Task name,
22, 31, 33... logical address, 23...
...J table, 24...Segment array, 25", 25"", 25""...P table, 26...Segment table, 27,
43, 44...control information, 28...
Task description block, 29, 37, 38, 41,
42... Real address, 30, 32...
- Segment table array, 34... Segment table word array O, 35... Segment table word array 1, 36, 40...
- Segment table, 39... Indirectly specified segment, 40... Directly specified segment, 45,
47...Logic part (key part), 46, 48.
...Real part (data part).

Claims (1)

[Claims] 1. A segment table having a plurality of pairs of segment table entries each having at least a pair of control information indicating direct or indirect specification and a real address in one storage location indicated corresponding to a logical address; If the control information in a specified segment table entry indicates an indirect specification, then the real address in that segment table entry specifies a further segment table entry, and the control information in the segment table entry indicates an indirect specification. address conversion means for repeatedly reading until designation is indicated, and outputting the real address of the segment table entry and the real address within the segment table entry when the control information indicates direct designation; and the logical address and the address translation means. an indirect display that has a plurality of conversion pairs with real addresses corresponding to the logical address converted by the address conversion means, and displays for each of the conversion pairs whether or not indirect designation was used in the conversion process by the address conversion means; bit, a multiple indication bit indicating whether the indirect specification has been used more than once, the real address of the directly specified segment table entry that is the output of the address translation means, and the validity of each translation pair. and an address translation register stored therein including a validity indicator bit, and when executing an instruction to update the segment table entry specified by the logical address, update the segment table entry specified by the instruction, and also update the segment table entry specified by the instruction. , the validity indication bit of the address translation register corresponding to the logical address is invalidated, and furthermore, the indirect indication bit indicates indirect designation for all entries in the address translation register, and the indication bit multiple times is 1. An address translation device characterized by invalidating all validity indicating bits of a translation register that is displayed multiple times or where a real address of a segment table entry and a real address of a segment table entry specified by an instruction match.