JPH06323798A - Blasting method - Google Patents

Abstract

PURPOSE:To enhance blasting effect by using electronically delayed detonator caps, setting the delay time of a delay circuit so that a minimum explosion time interval becomes a particular unit and successively exploding powder at explosion delay time intervals which are a multiple of a minimum explosion delay time interval. CONSTITUTION:Electric energy supplied by a blasting device 1 is stored by a capacitor 15, a constant voltage circuit 19 is started to operate by the stored electric energy to output constant voltage. The constant voltage is applied to a capacitor 22, and the voltage is elevated. When the voltage exceeds a voltage determined by voltage dividers 44, 46, the output level of a comparator 42 changes, and a main counter 50, a frequency divider 52 and a counter 72 are reset. The frequency divider 52 outputs a series of pulses in such a manner that a minimum priming time interval is in a unit of 1ms. At the same time the counter 72 starts to count clock pulses, and powder is successively exploded in explosion delay time intervals which are a multiple of the minimum explosion delay time interval. Therefore, crushing effect of rock is enhanced.

Description

Detailed Description of the Invention

[0001]

[Field of Industrial Application] A blasting method for detonating a plurality of explosives with a predetermined time accuracy.

[0002]

2. Description of the Related Art Generally, in a blasting method of detonating a plurality of explosives with a predetermined time accuracy, a delay device for determining the detonation time interval is carried out by using a detonator comprising a combustion composition or a detonator consisting of the detonator. It was

[0003]

In the blasting method in which a plurality of explosives are detonated with a predetermined time accuracy, ground vibration and noise generated in the blasting work are reduced, or the grain size of rock produced by the blasting work is reduced or By arranging the blast time on the crushed surface, it could be expected to have an effect such as a smooth finish.

In the blasting method in which the delay device for determining the detonation time interval uses a detonator comprising a combustion composition or a detonator consisting of a deferral, for example, in the case of an electric detonator, Japanese Industrial Standard JIS K4807-1981 (see Table 1 below). ), The reference detonation time is fixed, and the detonation time accuracy is about 10 times the reference detonation time.
% To 20%, and it was difficult to obtain an accurate detonation time interval as the detonation time became longer, so there was a limit to the blasting design.

[0005]

[Table 1]

Further, as a blasting method using an electronic delay detonator having a high initiation time accuracy, Japanese Patent Laid-Open No. 62-261900
Japanese Patent Laid-Open No. 1-285800 has been proposed.

However, in the above-mentioned technique, the accuracy of the explosive detonation time interval required to obtain these blasting effects was not clear.

Therefore, in the blasting method of detonating a plurality of explosives at a predetermined time interval, the present invention clarifies the accuracy of the detonation time interval of the explosive and sequentially detonates at a predetermined time interval satisfying the accuracy of the detonation time interval. The purpose is to provide a blasting method that improves the blasting effect.

[0009]

In the present invention, in order to achieve the above object, storage means for storing electric energy supplied from a blasting device, and operation start by the electric energy stored in the storage means, A delay circuit which outputs an ignition signal after a preset delay time and which can change the delay time, and the ignition circuit which is closed by the ignition signal output from the delay circuit to close the electric energy accumulated in the accumulating means to an ignition resistor. An electronic delay detonator having a switching circuit for energizing the line is used, and the delay time of the delay circuit is set so that the minimum detonation time interval is a unit of 1 ms, and the detonation is an integral multiple of the minimum detonation delay time interval. It is characterized in that explosives are sequentially initiated at delay time intervals.

Preferably, in order to achieve the above object,
The delay circuit starts operation by the electric energy charged in the storage means and oscillates a clock pulse, and the count value can be changed and set, and the output of the oscillating means after a reset time within 10 ms. Counting means for counting clock pulses, output means for outputting the ignition signal when the counting means counts the clock pulses by a preset count value, and frequency of the clock pulses within the reset time. Means for over-exciting the oscillating means so as to reach the natural frequency of the oscillating means.

[0011]

According to the present invention, by setting the initiation time interval at a minimum of 1 ms and arbitrarily controlling the initiation time interval of explosive, it is possible to perform controlled blasting suitable for the properties of the ground or rock to be crushed. Further, in the electronic delay detonator used in the blasting method of the present invention, the output frequency of the oscillating means reaches the steady frequency in an extremely short time due to overexcitation, and the counting means operates after the output frequency of the oscillating means enters the steady state. Since counting is started, a highly accurate and reliable delay time can be obtained.

[0012]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 shows an embodiment of an electronic delay detonator used in the present invention.

In the figure, input terminals 11 and 12
Is connected to the electric blaster 1 of FIG. 1 via a lead wire 6. The resistor 13 and the rectifier 14 are connected to the input terminal 11
And 12 are connected. The capacitor 15 and the resistor 16 are connected in parallel between the output terminals of the rectifier 14. Resistor 13 prevents stray currents, which often occur at the blast site, from charging capacitor 15 to a voltage that would ignite the detonator. Furthermore, the resistor 13 is
In a multi-stage blasting system, when a plurality of detonators are connected in series, it acts as a voltage divider so that almost equal voltage is applied to each rectifier 14. Rectifier 14 is a capacitor 1
It allows 5 to be charged in one direction, regardless of the polarity of the input voltage supplied to terminals 11 and 12. In this embodiment, the resistance value of the resistor 13 is 15Ω and the capacity of the capacitor 15 is 1,000 microfarads.
In this case, the capacitor 15 is charged by the electric energy supplied from the electric blaster 1 to a maximum voltage of 15V in 5 to 10 ms.

A series circuit of a thyristor (switching element) 17 and an ignition resistor 18 is connected to both ends of the capacitor. Further, the input terminal of the constant voltage circuit 19 is connected to both ends of the capacitor 15. Capacitor 20
A series circuit of a resistor 21 and a capacitor 22 is connected in parallel between the output terminals of the constant voltage circuit 19. Resistance 2
1 and capacitor 22 are counter reset time circuit 23
Are configured. Further, the digital timer 30 is connected to the output terminal of the constant voltage circuit 19.

The digital timer 30 includes a reset circuit 4
0, a main counter 50 that counts the delay time to ignite the detonator, a preset circuit 60 that presets the initial value of the main counter, and an over-excitation circuit that over-excites the oscillator 90 so that the oscillator 90 enters a steady state in an extremely short time. It is composed of 70.

The reset circuit 40 comprises a comparator 42 and a voltage divider composed of resistors 44 and 46. The inverting input terminal of the comparator 42 has a resistor 21 and a capacitor 22.
The non-inverting input terminal of the comparator 42 is connected to the connection point of the resistors 44 and 46.
Therefore, the output of the comparator 42 changes from the high level to the low level after a predetermined time T1 defined by the time constants of the resistor 21 and the capacitor 22. The predetermined time T1 is defined as, for example, 5 ms, which corresponds to the counter reset time of the present invention.

The main counter 50 is a 13-bit preset type counter to which the pulse train is supplied from the frequency divider 52. The frequency divider 52 is a 12-bit frequency divider. That is, the output frequency of the frequency divider 52 is 1/4096 of the frequency of the clock pulse train Se supplied from the oscillator 90.

The main counter 50 is connected to a preset circuit 60 which presets the initial value of the main counter 50. The preset circuit 60 is driven by the flip-flop 56. This flip-flop 56 outputs the signal S
It is reset at the rising edge of R. On the other hand, the main counter 50
The frequency divider 52 is reset at the falling edge of the signal SR.

FIG. 2A shows a plurality of switching circuits 62.
1 shows a preset circuit 60. Each switching circuit 62 is connected to a p-
It is composed of a channel FET 64 and an n-channel FET 66. The gates of the two FETs are connected to the Q output of flip-flop 56. When the flip-flop 56 is in the set state, that is, when the gate voltage is higher than the threshold voltage, the p-channel FET 64 is turned off and the n-channel FET is turned on. Therefore, the output level of each switching circuit 62 is low, and the preset value of the main counter 50 does not change. vice versa,
When the flip-flop 56 is in the reset state, that is,
If the gate voltage is below the threshold voltage, p-channel FET 64 is conductive and n-channel FET 66 is cut off. In this case, each switching circuit 62
Output level of the time set lines 68-1, 68-
2 ,. ． ． It depends on the state of 68-m. If the time set line 68-j is grounded, the switching circuit 6
2 output level is low, but time set line 68
High when j is open.

In FIG. 1, the output of the main counter 50 is supplied to the flip-flop 58, which sets the flip-flop 58 which was previously reset at the rising edge of the signal SR. When the flip-flop 58 is set, the thyristor 17 is triggered and turned on. That is, all the electrical energy remaining in the capacitor 15 after being consumed by the delay circuit is supplied to the ignition resistor 18 and the detonator explodes.

The overexcitation circuit 70 includes an auxiliary counter 72, flip-flops 74-1, 74-2 ,. ． ． 74-n,
Clocked inverters 76-1, 76-2 ,. ． ． 76
-N and an inverter 78. The counter 72 outputs signals R1, R2. ． ． Rn is output and this is output to flip-flops 74-1 and 74-
2 ,. ． ． It is supplied to each reset terminal of 74-n. The flip-flops 74-1, 74-2 ,. ． ． 74
-N is simultaneously set at the rising edge of the signal SR, and the signal R
1, R2 ,. ． ． It is sequentially reset by Rn. The output terminal of the flip-flop 74-i (i = 1, 2, ..., N) is connected to the control terminal of the clocked inverter 76-i. The overexcitation circuit itself is disclosed in
Known in the field of electronic circuits, as disclosed in FIG. 9 of 200009.

FIG. 2B shows a clocked inverter 76-
It is a circuit diagram of i. This clocked inverter 76-i
Control terminals 83 and 84 of the flip-flop 74-
It is connected to the output terminal of i. The input terminal 81 and the output terminal 82 of the clocked inverter 76-i are connected to the oscillator 90. When a high level signal is applied to the control terminal 83 and a low level signal is applied to the control terminal 84, the clocked inverter operates as an inverter. On the other hand, when a low level signal is applied to the control terminal 83 and a high level signal is applied to the control terminal 84, the clocked inverter is electrically disconnected from the oscillator 90.

The oscillator 90 comprises a crystal oscillator 92 and a feedback resistor 9 connected in parallel with the crystal oscillator 92.
4. It is composed of capacitors 96 and 98 connected between the crystal oscillator 92 and the ground. The frequency of the crystal oscillator is preferably in the range of 1 MHz to 16 MHz. If the frequency is too low, the rise time of oscillation becomes long. As a result, the counter reset time T1 increases, and the accuracy of the delay time is adversely affected. If the frequency is too high, it will increase power consumption. As a result, the capacitor 15 cannot supply enough electrical energy to explode the detonator.

Next, the operation of the delay circuit of FIG. 1 will be described with reference to FIG.

FIG. 3 shows the waveform of each part of the delay circuit.

At time t0, a voltage Sa is applied from the electric blaster 1 to the input terminals 11 and 12. The electric energy given by the voltage Sa is stored in the capacitor 15, and the voltage Sb of the capacitor 15 rapidly increases. The constant voltage circuit 19 immediately after the application of the voltage Sa (several microseconds)
Of the constant voltage Sc (for example, 3.
3V) is output.

The constant voltage Sc is applied to the capacitor 22 via the resistor 21, and the voltage Sd of the capacitor 22 gradually increases. When the voltage Sd exceeds the voltage determined by the voltage divider formed by the resistors 44 and 46 at time t2, the comparator 42
Output level changes from high to low, and this change makes the signal SR fall. That is, when the time interval T1 (about 5 ms in this embodiment) elapses after the time t1,
The falling edge of the signal SR is generated. Signal SR is at time t
At its rising edge in 1, flip-flop 74-1
~ 74-n and set flip-flops 56 and 5
8 is reset. On the other hand, the signal SR resets the main counter 50, the frequency divider 52, and the counter 72 at the falling edge thereof at the time t2.

During the time interval T1, the crystal oscillator 92
It is over-excited by the clocked inverters 76-1 to 76-n and the inverter 78 and enters a steady state. That is, the frequency of the pulse train output from the crystal oscillator 92 is stabilized during the time interval T1.

At time t2, the frequency divider 52 starts to operate,
A pulse train Sf consisting of pulses with an interval of 1 ms is output. At the same time, the counter 72 starts counting the clock pulses supplied from the crystal oscillator 90 and generates signals R1 to Rn at intervals of 1 μs. The signal R1 sets the flip-flop 56 and resets the flip-flop 74-1 at time t3, which is 1 μs after the time t2. Therefore, the signal Sg applied to the preset circuit 60 rises at time t3, and the preset circuit 60 is turned on by the constant voltage circuit 19.
Disconnect from. This reduces the power consumption by the delay circuit.

After the time t3, the flip-flop 74-
1 to 74-n are signals Sh (= R1, R2, ... Rn)
By this, the reset is performed every T2 interval (1 μs). Therefore, the clocked inverters 76-1 to 76-76
-N is sequentially cut off from the oscillator 90. That is, the overexcitation of the oscillator 90 is gradually released by the signal Sh. As a result, the current S supplied to the crystal oscillator 90
i is 20 mA supplied from the clocked inverter 76 and the inverter 78 at the start of over-excitation, and 0.
Gradual change to 2 mA, which is supplied by the inverter 78 during steady excitation.

The crystal oscillator 92 consumes considerably more power in the initial stages of oscillation and automatically reduces its power consumption as the oscillation approaches a steady state. Therefore, over-excitation of the crystal oscillator by the clocked inverter driven by the constant voltage does not cause thermal damage to the oscillator and leads oscillation to a steady state in an extremely short time.

By utilizing this feature of the crystal oscillator, the clocked inverter 76 and the inverter 78 are used.
Can be replaced by an inverter that can supply sufficient current to induce over-excitation of the crystal oscillator. In this case, the clocked inverter 76 and the flip-flop 74 can be omitted.

When the current value of the main counter 50 reaches the preset value, the main counter 50 sets the flip-flop 58. This produces a trigger signal Sj for the thyristor 17, a current Sk being supplied from the capacitor 15 to the ignition resistor 18. In this way, the detonator explodes.

An embodiment of the blasting method carried out by using the electronic delay detonator shown in the above embodiment will be specifically described below.

<Example 1> Example 1-1 In a quarry with a bench height of 3 m, a bench was blasted with a hole diameter of 50 mmφ, a hole length of 3.0 m and a hole interval of 1.5 m. First, prior to carrying out the present invention, in order to determine the detonation time interval of the explosive charge, an AN-FO explosive charge of 1.5 using columnar charge is used.
kg / hole, 200 g of carrit as a parent die was equipped with a flashing electric detonator, and the vibration waveform at 280 m from the face was measured. As a result of synthesizing based on this waveform using a linear superposition principle by a computer and performing an analysis, the initiation time interval at which vibration was minimized was 27 ms.

Next, based on the result of the second time design, the carrit 200 g equipped with the electronic delay detonator was used as a parent die, and the same charge was applied to 8 holes of the bench as described above. The blast vibration at 170 m was measured. This result is calculated by distance correction based on the equation (1) and is shown in Table 2.

[0038]

V ′ = V × (d ′ / d) ^−0.7 (1) where V ′ is the corrected vibration velocity (cm / sec) V is the vibration velocity (cm / sec) d ′ is The correction distance (m) d is the measured distance (m). An electronic delay detonator having the same initiation time interval as that used in Example 1-2 and Example 1-1 is used, and the charging conditions are those of Example 1-1. The number of holes was changed to 15 in the same manner as in, and the blasting vibration was measured at the same position as in Example 1. This result is calculated by distance correction based on the equation (1) and is shown in Table 2.

<Comparative Example 1> As a comparative example, charging was carried out in the same manner as in Example 1 except that a DS (detonation time interval 250 ms; detonation delay by deferred squib) electric detonator was mounted on the parent die. The blasting vibration was measured at the same position. This result is calculated by distance correction based on the equation (1) and is shown in Table 2.

[0040]

[Table 2]

However, the reduction rate is a result calculated based on the corrected vibration velocity of Comparative Example 1. Examples 1-1, 1-
According to 2, it was estimated that the optimal detonation time interval for reducing ground vibration at the blast site where the experiment was conducted was 27 ms, and when blasting was performed according to this, the vibration value was reduced as estimated.

A feature of the present invention is that the initiation time interval is the minimum reference setting time interval 1 as seen in Examples 1-1 and 1-2.
It is a blasting method that can be set in integral multiples of ms and that does not change the order of initiation even if the initiation time interval is set to 1 ms, and is not limited to the reduction of ground vibration.

Example 2 In a quarry with a bench height of 7.5 m, the hole diameter is 65 mmφ, the hole length is 8.5 m, and the hole interval is 2.
The bench was blasted at 5 m and a resistance wire of 2.5 m.

First, prior to the blasting, the elastic wave velocity of the rock mass was measured in order to determine the initiation time of the electronic delay electric detonator with high time accuracy. For the measurement, three-point vibration velocimeters were installed at intervals of 10 m, rocks were vibrated by a heavy machine, and the vibration between three points was measured to obtain the elastic wave velocity. As a result, it was found that the rock mass of this crushed stone factory has an elastic wave velocity of about 2100 m / s. From this result, the action speed of gas pressure is about 2
Since it is 52 m / s (value calculated as 12% of the elastic wave velocity), the initiation time is 9.9 ms. Therefore, as an example of the present invention, an initiation time difference of 10 ms per hole was set.

Then, based on the result of the second time design, an electronic delay electric detonator (10 ms, 1 ms) with high second time accuracy disclosed in JP-A-57-14298 and JP-A-58-83200.
(15 stages) with 100 g of dynamite as a parent die, 15 holes per bench hole, ANFO explosive 15
Table 3 shows the number of rocks requiring breaker treatment, the breaker treatment time, the number of small blasts, and the number of days of rock treatment after blasting after loading with kg.

Comparative Example 2 With respect to the blasting in which the explosives were all detonated by the instantaneous electric detonator on the same bench as in the example, the same items as in the example after the blasting were measured and compared. The results are shown in Table 3.

<Comparative Example 3> On the same bench as in Example and Comparative Example 2, an MS electric detonator (25
Blasting was carried out in 1 ms to 15 stages), and the same items as in the example after the blasting were measured and compared. The results are shown in Table 3.

<Comparative Example 4> On the same bench as in Example and Comparative Example 2, a DS electric detonator (25
For the blasting performed at 0 ms for 1 to 15 steps), the same items as in the example after the blasting were measured and compared. The results are shown in Table 3.

[0049]

[Table 3]

As described above, according to the present invention, the number of rocks requiring breaker treatment after blasting, the breaker treatment time, the number of small blasts, and the number of days of rock treatment can be reduced. This can improve the crushing effect of rock by blasting.

[0051]

According to the blasting method of the present invention, the ground vibration and noise generated in the blasting work are reduced by controlling the time intervals of the explosives in each charging hole to cause interference, and the number of detonation steps is reduced. By increasing arbitrarily, detonation time of each explosive of all stages is completely separated and blasting work is performed,
It can reduce ground vibration and improve the blasting effect.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an electronic delay circuit for an ignition device according to the present invention.

2 (a) is a circuit diagram showing the preset circuit of FIG. 1,
(B) is a circuit diagram showing the clocked inverter of FIG. 1.

FIG. 3 is a diagram showing a waveform of each part of FIG.

[Explanation of symbols]

 1 Electric Blasting Device 6 Lead Wire 11, 12 Input Terminal 13 Resistance 14 Rectifier 15 Capacitor 17 Thyristor 18 Ignition Resistance 19 Constant Voltage Circuit 20, 22 Capacitor 21 Resistance 23 Counter Reset Time Circuit 30 Digital Timer 40 Reset Circuit 42 Comparator 44, 46 Voltage division resistance 50 Main counter 52 Division cycle 56,58 Flip-flop 60 Preset circuit 62 Switching circuit 64 p-Channel FET 66 n-Channel FET 67 Resistance 68-1 to 68-m Time set line 70 Overexcitation circuit 72 Auxiliary counter 74 -1 to 74-n Flip-flop 76-1 to 76-n Clocked inverter 81 Clocked inverter input terminal 82 Clocked inverter output terminal 83, 84 Control terminal 90 Oscillator 92 Crystal oscillator 4 feedback resistors 96, 98 capacitor

Claims (2)

[Claims] 1. A storage device for storing electric energy supplied from a blasting device, and a delay time for starting an operation by the electric energy stored in the storage device and outputting an ignition signal after a preset delay time. And an electronic delay detonator including a switching circuit that is closed by an ignition signal output from the delay circuit and energizes the resistance wire for ignition with the electrical energy stored in the storage means. The blasting method is characterized in that the delay time of the delay circuit is set so that the minimum detonation time interval is a unit of 1 ms, and explosives are detonated sequentially at detonation delay time intervals that are integer multiples of the minimum detonation delay time interval. . 2. The delay circuit is operable by electric energy charged in the storage means to oscillate a clock pulse, and a count value can be changed and set, and after a reset time within 10 ms. Counting means for counting the clock pulses output by the oscillating means, output means for outputting the ignition signal when the counting means counts the clock pulses by a preset count value, and within the reset time The blasting method according to claim 1, further comprising means for over-exciting the oscillation means so that the frequency of the clock pulse reaches the natural frequency of the oscillation means.