JPH06302824A - Thin-film transistor and its manufacture - Google Patents

Abstract

PURPOSE:To provide a manufacturing method of a thin-film transistor, which can obtain an LDD structure without using a cap film in an ion implantation operation and without depositing layers having two kinds of dose amounts. CONSTITUTION:The manufacture includes a process wherein an amorphous silicon film 2 having a thin film thickness is formed in a region to be used as a channel part and in a region a little larger than the region and amorphous silicon films 2 having a thick film thickness are formed in regions to be used as contact parts on both sides of it, a process wherein the amorphous silicon films 2 are recrystallized by being irradiated with a laser beam and a process wherein impurities are ion-implanted into the recrystallized silicon films excluding the region to be used as the channel part and they are activated thermally.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor and an LDD (Lightly) which have both improved mobility in a channel portion and reduced sheet resistance in a contact portion.
The present invention relates to a method of manufacturing a thin film transistor that achieves the same effect as the DopadDrain structure.

[0002]

2. Description of the Related Art FIG. 9 is a longitudinal sectional view showing a method of manufacturing a conventional thin film transistor (hereinafter referred to as TFT) in the order of steps.

A conventional method of manufacturing a TFT will be described below with reference to this drawing.

As shown in FIG. 1A, a polysilicon (hereinafter referred to as Poly-Si) film 2 is formed on an insulating substrate 1 by a thermal CVD method, a PECVD method, or the like 300-1.
It is formed to a film thickness of 500Å.

Next, as shown in FIG.
-The Si film 2 is subjected to an islanding process for element isolation.

After that, as shown in FIG.
₂ , a gate insulating film 3 made of SiN _x or the like is formed to a film thickness of 1000 to 2000 Å by sputtering or a CVD method,
A gate electrode 4 made of a refractory metal or the like is formed thereon.

Next, using the gate electrode 4 as a mask, an impurity such as P (phosphorus) or B (boron) is implanted into the source / drain regions S and D by the ion beam 5. afterwards,
The source / drain regions S and D are electrically activated by thermal annealing or laser activation treatment.

Next, as shown in FIG. 3E, a passivation film 7 made of PSG, SiN _x , or the like is applied to 3000.
After forming the film with a thickness of ˜7,000 Å, contact holes are formed on the source / drain S and D, and the source / drain electrode 8 is formed. Thereby, a TFT is obtained.

[0009]

By the way, the above-mentioned TFT
In the prior art, it has been desired to improve the mobility of the channel portion C to improve the element driving speed and reduce the sheet resistance of the contact portions S and D to reduce the element driving power.

In order to improve the mobility of the channel portion C, it is desirable to make the film thickness of the channel portion C thin (about 500Å). For that reason, if the Poly-Si film 2 is made thin, the contact is The film thicknesses of the portions to be the portions S and D also become thin. As described above, the portions to be the contact portions S and D are subjected to ion implantation and thermal activation treatment for conductivity, but when the contact portion is thin, the sheet resistance is reduced. The range of optimization of the ion implantation conditions and the activation conditions is extremely narrow, and the characteristics vary among the elements, resulting in deterioration of quality and yield.

On the other hand, if the thickness of the Poly-Si film 2 is increased in order to reduce the sheet resistance of the contact portions S and D, the mobility improvement of the channel portion C cannot be expected.

Conventionally, an LDD structure has been devised in a TFT for weakening the electric field at the drain end in order to eliminate the adverse effects associated with the shortening of the channel, that is, the adverse effects such as hot carrier phenomenon and current leakage. There is.

As a method of manufacturing a TFT having an LDD structure, for example, ion implantation is performed with a cap film formed on a region to be an n ⁻ layer to reduce the dose amount of the cap film portion to form a low concentration impurity layer. How to get, or 2
There is known a method of depositing impurity layers having different dose amounts.

However, in the above conventional method, the cap film must be formed at the time of ion implantation, which increases the number of steps. In addition, the method of depositing the n-layers of two types of dose amounts causes the problems of increasing the number of steps and complicating the dose amount management.

In view of the above circumstances, the present invention provides a TFT capable of improving both the mobility in the channel portion and the sheet resistance in the contact portion, and an effect similar to that of the LDD structure while achieving the compatibility and the number of steps. It is an object of the present invention to provide a TFT that reduces

[0016]

In the thin film transistor according to the present invention, in order to solve the above-mentioned problems, a semiconductor film in a portion to be a channel portion is formed thinner than a semiconductor film in a portion to be a contact portion by implanting impurities. It is characterized by doing.

Further, the thin film transistor according to the present invention is
A semiconductor film in a region slightly larger than this region including a region to be a channel portion is formed to be thicker than a semiconductor film in a portion to be a contact portion by implanting impurities, and a thin film in a region slightly larger than the region to be the channel portion is formed. It is characterized in that the semiconductor film is formed on the high sheet resistance layer.

Further, in the method of manufacturing a thin film transistor according to the present invention, a thin amorphous semiconductor film is formed in a region slightly larger than this region including a region to be a channel portion, and the contact portions on both sides thereof are formed. Forming a thick amorphous semiconductor film in the region to be formed, recrystallizing the amorphous semiconductor film by irradiating laser, and removing the region except the region to be the channel portion And ion-implanting impurities into the semiconductor film, followed by thermal activation.

[0019]

According to the first structure, since the semiconductor film in the portion to be the channel portion is thin and the semiconductor film in the portion to be the contact portion is thick, the mobility in the channel portion and the contact portion are improved. It is possible to reduce the sheet resistance at the same time.

Further, according to the second structure, the thin film portion in a region slightly larger than the region which becomes the channel portion is the high sheet resistance layer, and the improvement of the mobility and the reduction of the sheet resistance of the contact portion are compatible with each other. While realizing, the same effect as the LDD structure is realized.

Further, according to the above manufacturing method, the amorphous semiconductor film becomes a polycrystalline semiconductor film by laser recrystallization. Then, when ion implantation and subsequent thermal activation processing are performed on this polycrystalline semiconductor film, the crystal grain size at the time of polycrystallization becomes larger in the thin film portion than in the thick film portion. Therefore, the sheet resistance increases.

On the other hand, in the region where the contact portion is formed with a large film thickness, the grain size becomes small and the sheet resistance becomes low due to ion implantation and subsequent thermal activation. Therefore, by arranging the high sheet resistance layer at the drain end,
At the end of the drain, the electric field is apparently relaxed, and LDD
The same effect as the structure can be obtained.

[0023]

【Example】

 (Example 1)

The present invention will be described below with reference to the drawings showing its embodiments. FIG. 1 is a vertical sectional view showing a thin film transistor according to the present invention.

On the insulating substrate 1, a semiconductor film Po is formed.
The ly-Si film 2 is formed. Poly-Si film 2
Is a thin film (approx. 500Å) at the channel C.
On the other hand, the portions to be contact portions (source S / drain D) are formed as thick films (1000 to 2000 Å).

A gate electrode 4 is formed on the channel portion C via a gate insulating film 3a, and a passivation film 7 is further formed on the gate electrode 4 and the insulating film 3. A contact hole H is formed in the insulating film 3 and the passivation film 7 on the contact portions S and D of the Poly-Si film 2, and the electrodes 8 and 8 are connected to the contact portion S through the contact hole H.
-Connected to D.

According to the above structure, the Poly-Si film 2 in the portion which becomes the channel portion C is thin, and the contact portions S and D are formed.
Since the Poly-Si film 2 in the portion to be formed is thick, the mobility in the channel portion C is improved and the contact portion is formed. It is possible to achieve both reduction of sheet resistance in S and D.

FIG. 2 shows a TFT having the above structure according to the present invention.
It is a graph which showed the drain current-gate voltage characteristic in TFT (b) and (c) of a conventional structure, and (a).
In the conventional TFT, the Poly-Si film 2 having a film thickness of 1000 Å (graph b) and 500 Å
2 (graph c) are shown.

As is apparent from the comparison of FIG. 2, when the thickness of the poly-Si film 2 is reduced in the conventional structure, the sheet resistance of the contact portion is high, so that the ON current is rate-limited (c).
On the contrary, if the film thickness of the poly-Si film 2 is increased in the conventional structure, the sheet resistance of the contact portion is reduced and the ON current is not rate-controlled, but the threshold characteristic (rise of the curve).
And the OFF characteristic is bad (b). The TFT according to the present invention is
At the same time that the ON current is not rate-limited, the threshold characteristic and the OFF characteristic are improved by thinning the channel portion (a).

Next, a method of manufacturing the above TFT will be described.

(First Manufacturing Method)

First, as shown in FIG. 3A, a Poly-Si film 2 is formed on an insulating substrate 1 to a film thickness of 1000 to 2000 Å. The Poly-Si film 2 can be formed by thermal CVD, PECVD, or the like.

Next, as shown in FIG. 3B, an islanding process for element isolation is performed by etching.

Next, as shown in FIG.
-Only the region of the Si film 2 which becomes the channel portion C is thinned by etching, and the film thickness of this portion is set to 500 Å or less. The etching is, for example, dry etching using CF ₄ + O ₂ (5%) as an etching gas, the gas flow rate is 20 sccm, and the chamber pressure is 0.3 To.
The rr and Rf outputs were set to 150W.

Next, as shown in FIG.
The insulating film 3 to be the gate insulating film 3a is formed on the Si film 2 by 10
It is formed to a film thickness of 00 to 2000Å. The insulating film 3 can be made of SiO _2, SiNx, or the like, and can be formed by a sputtering method, a thermal CVD method, or the like.

After the insulating film 3 is formed, the gate electrode 4 is formed on the insulating film 3 located in the region to be the channel portion C. For the gate electrode 4, a refractory metal such as Cu or Mo, or a Poly-Si film is used. Further, the film thickness of the gate electrode 4 is set to 3000 to 6000Å, and a sputtering method or the like is used as a forming method. When the above poly-Si film is used, it is used as a gate electrode by implanting an impurity at the same time as a contact region described later and electrically activating it.

Next, as shown in FIG. 6E, impurities such as P (phosphorus), B (boron), As (arsenic) are added to the contact regions which will be the source S and the drain D, using the gate electrode 4 as a mask. Inject. The implantation conditions are as follows:
When the SiO ₂ is 00Å and the impurity is P ⁺ , the implantation output is 80 to 1000 KeV and the dose is 2
It is set to × 10 ¹⁵ cm ^-2 .

After that, the contact portion is electrically activated by thermal annealing or laser annealing. For example, the thermal annealing is performed by leaving it in an N ₂ atmosphere at 650 ° C. under a normal pressure for 2 hours, and the laser annealing is performed, for example, in a vacuum atmosphere using an ArF excimer laser (200 to 300 mJ / cm ² ). 2 to 32 sh
It is performed by irradiating ots. In addition, even with the above-mentioned thermal activation of about 650 ° C, the sheet resistance is lowered (1500 Å 300
Ω / □ or less) is possible.

Next, as shown in FIG. 3F, a passivation film 7 is formed on the entire surface. Passivation film 7
For example, PSG or SiN _x is used,
The film thickness is set to 3000 to 7000Å.

After forming contact holes H in the source S and drain D, the source / drain electrodes 8 and 8 are formed.
To form. The electrodes 8 and 8 are made of Al or Poly-Si.
Can be formed with a film thickness of 5000-100
It is set to 00Å. Next, hydrogen passivation treatment (400 ° C., 1 hour thermal annealing in a hydrogen atmosphere at atmospheric pressure) is performed. Note that this process may be performed immediately after the passivation film 7 is formed.

Through the above steps, the TFT of the present invention shown in FIG. 1 is manufactured.

(Second Manufacturing Method)

This manufacturing method is a method having a step which replaces the step forming step by etching shown in FIG. 3C in the first manufacturing method.

That is, in this method, the channel portion is set to 500 Å
If the thickness of the film is
The i film 2X is formed in the step of FIG. 3 (a) in the first method, and in the step of FIG. 3 (c), in place of this etching, as shown in FIG. Further, only the Poly-Si film 2Y is formed to a thickness of 500 Å or more.

As a result, similar to the first method, the thickness of the channel portion is as thin as about 500Å and the contact portion is 100
It is possible to obtain a TFT formed thicker than 0Å.

In the first and second manufacturing methods described above, since the contact portion is formed to have a relatively large film thickness, it is easy to set the ion implantation condition and the activation condition. Furthermore, for example, by controlling the implantation profile as shown in FIG. 5B, a concentration distribution is provided in the film thickness direction at the contact portion, and the n ⁻ / n ⁺ structure, that is, LD
The D structure can be easily provided. Further, in the first and second manufacturing methods described above, the Poly-Si film 2 may be formed by using an amorphous Si (hereinafter abbreviated as a-Si) film as a starting film. Of course.

(Embodiment 2) Another embodiment of the present invention will be described below.

The thin film transistor of this embodiment is shown in FIG.
As shown in (c), the poly-Si of the region 2a ₂ including the region 2a ₁ which becomes the channel portion is slightly larger than this region.
The film is thin, and the contact portions 2b and 2b are formed by implanting impurities.
The poly-Si film of the portion to be formed is thick, and
Region 2 that is slightly larger than the region that will be the channel portion 2a ₁
poly-Si thin film of a ₂ only is a high sheet resistance layer.

According to this structure, similarly to the TFT of the first embodiment, both the improvement of the mobility and the reduction of the sheet resistance are realized, and only the region 2a _{2 which} is a little larger than the region 2a _{1 serving as the} channel portion has the high sheet resistance. The layer has the same effect as the LDD structure.

Next, a method of manufacturing the thin film transistor having the above structure will be described.

First, as shown in FIG. 3A, an a-Si film 2 is formed on an insulating transparent substrate 1, and a region slightly larger than this region including a region to be a channel portion has a film thickness of 500Å.
The regions to be the contact portions on both sides are formed to have a film thickness of 1000Å.

Next, laser irradiation is performed from the substrate surface side in a vacuum atmosphere. An ArF excimer laser is used as the laser, and the substrate temperature at this time is 40
It was set to 0 ° C.

As a result of the above laser irradiation, as shown in FIG. 6B, the thin film region 2a having the film thickness of 500Å, that is, a region slightly larger than this region including the region to be the channel portion, has a large grain size. Is formed in the thick film region 2b having a film thickness of 1000Å, that is, a region to be a contact portion, the poly-Si film is formed to have a relatively large film thickness. -Si film is formed. Specifically, the energy density of the laser is 300 (m
J / cm ² × 8 shots), the film thickness is 500
If it is Å, the maximum particle size is 5000 Å and the film thickness is 100.
If it is 0Å, the maximum particle size will be 3000Å.

Next, the gate insulating film 3 and the gate electrode 4 are formed on the thin film region 2a which will be the channel. After that, ion implantation is performed using the gate electrode 4 as a mask.

In the above ion implantation, the doping ions are P ⁺ (phosphorus) ions and the dose amount is 2 × 10 5.
¹⁵ to 1 × 10 ¹⁶ cm ^-2 , implantation depth is 100 to 500
It is set to Å. After this ion implantation, a thermal activation process is performed by leaving it in a nitrogen atmosphere at 650 ° C. for 20 hours.

Here, the sheet resistance of the semiconductor film will be described by the thermal activation treatment after the ion implantation.

In FIG. 7, ion implantation was performed (120 Ke
V, 1 × 10 ¹⁶ cm ^-2 , P ⁺ ion), thermal activation (650
It is a graph which showed the change with sheet thickness of sheet resistance after carrying out (° C, 20 hours). As is clear from this graph, as the film thickness increases, the sheet resistance decreases and the film thickness 5 decreases.
It can be seen that the thin film region 2a of 00Å is a high sheet resistance region and the thick film region 2b of 1000Å is a low sheet resistance region.

FIG. 8 shows the relationship between the recrystallization laser energy and the sheet resistance when the ion implantation is 140 ke.
The figure shows three cases in which the dose amounts are 1 × 10 ¹⁶ , 5 × 10 ¹⁵ , and 2 × 10 ¹⁵ cm ⁻² for V and 120 keV, respectively. The thickness of the semiconductor film at this time is 500Å, and thermal activation is performed at 650 ° C. for 20 hours. As is clear from this graph, the larger the recrystallization laser energy is, that is,
The larger the crystal grain size of the polycrystalline film, the higher the sheet resistance. Therefore, the thin film region 2a having a large crystal grain size becomes a high sheet resistance region, and the thick film region 2b having a small crystal grain size is
It can be seen that this is a low sheet resistance region. As described above, when the film thickness is 1000Å, the crystal grain size becomes small (maximum grain size 3000Å), and when the film thickness is 500Å, the crystal grain size becomes large (maximum grain size 5000Å).

As described above, according to the above method, a complicated process such as two-step ion implantation is not required, and the manufacturing process can be simplified.

As a method of forming a region slightly larger than this region including the region to be the channel portion into a thin film and regions on both sides thereof to be the contact portion into a thick film, for example,
An a-Si film is formed on an insulating transparent substrate by plasma CVD with a constant film thickness of 1000Å. The substrate temperature at this time is, for example, 200 to 400 ° C., and the silane gas flow rate is 20 SCCM. After that, a resist film is formed in a region to be a contact portion and etching is performed, so that a region slightly larger than this region including a region to be a channel portion can be formed as a thin film.

At this time, if the above etching is isotropic etching, the film thickness can be gradually increased from the channel portion to the contact portion. In this case, a structure in which the crystal grain size and the sheet resistance are gradually changed is obtained. According to such a structure, even if some deviation occurs in the patterning of the gate insulating film and the gate electrode, the deviation is absorbed. As a result, it is possible to secure the same effect as that of the LDD structure, and it is possible to allow a margin for patterning accuracy.

The laser irradiation for recrystallization may be performed after the etching without removing the resist film. When the laser irradiation is performed with the resist film left, the energy of the laser is weakened in the remaining part (contact part) of the resist film, so that the crystal grain size is more remarkable than the difference in the film thickness alone. Can be different.

[0063]

As described above, according to the present invention, it is possible to improve the mobility of the channel portion and reduce the sheet resistance of the contact portion at the same time. Further, the drain withstand voltage can be improved by the structure in which the high sheet resistance layer is formed only in a region slightly larger than the region to be the channel portion.

[Brief description of drawings]

FIG. 1 is a vertical sectional view showing a thin film transistor of the present invention.

FIG. 2 is a graph showing drain current-gate voltage characteristics of a thin film transistor of the present invention and a thin film transistor having a conventional structure.

FIG. 3 is a cross-sectional view showing the method of manufacturing the thin film transistor of the present invention in the order of steps.

FIG. 4 is a cross-sectional view showing a method for forming a Poly-Si film by double-layer formation of the present invention.

5A is a sectional view of a TFT having an LDD structure obtained by controlling an implantation profile, and FIG. 5B is a graph showing an ion implantation profile.

FIG. 6 is a cross-sectional view showing the method of manufacturing the thin film transistor of the present invention in the order of steps.

FIG. 7 is a graph showing changes in sheet resistance with film thickness.

FIG. 8 shows the relationship between the recrystallization laser energy and the sheet resistance (Ω / □) at doses of 1 × 10 ¹⁶ , 5 × 10 ¹⁵ , respectively when ion implantation is performed at 140 KeV and 120 KeV. 6 is a graph showing three cases of 2 × 10 ¹⁵ cm ⁻² .

FIG. 9 is a cross-sectional view showing a method of manufacturing a conventional thin film transistor in the order of steps.

[Explanation of symbols]

1 Insulating Transparent Substrate 2 Silicon Film (Polycrystalline or Amorphous Silicon Film) 2a Thin Film Region (Large Grain Polycrystalline Silicon Film) 2a ₁ i Layer 2a ₂ n ⁻ Layer 2b Thick Film Region (Large Grain Size) Crystal silicon film: n ⁺ layer) 3a Gate insulating film 4 Gate electrode

Claims (4)

[Claims] 1. A thin film transistor, wherein a semiconductor film in a portion to be a channel portion is formed thinner than a semiconductor film in a portion to be a contact portion by implanting impurities. 2. A semiconductor film in a region slightly larger than this region including a region to be a channel portion is formed thinner than a semiconductor film in a portion to be a contact portion by implanting impurities, and is slightly smaller than the region to be the channel portion. A thin film transistor, wherein a thin semiconductor film having a large area is formed on a high sheet resistance layer. 3. The film thickness of the semiconductor film to be the channel portion is set to 500 Å or less.
The thin film transistor according to. 4. A thin amorphous semiconductor film is formed in a region slightly larger than this region including a region which becomes a channel part, and a thick amorphous film is formed in a region which becomes a contact part on both sides thereof. A step of forming a high quality semiconductor film, a step of recrystallizing the amorphous semiconductor film by irradiating a laser, and an ion implantation of impurities into the semiconductor film except for a region which becomes a channel portion. The method of manufacturing a thin film transistor according to claim 2, further comprising the step of thermally activating.