JPH0547791A - Fabrication of thin film transistor - Google Patents

Abstract

PURPOSE:To suppress leak current of TFT even when the source.drain voltage is high. CONSTITUTION:After patterning of a gate electrode 5, a gate insulation film 4 is etched without peeling off a photo resist formed on the gate electrode 5 and then etching is further proceeded from the side part of the gate electrode 5 thus forming the end part of the gate electrode 5 on the inside of the gate insulation film 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor used for driving an image display device or the like.

[0002]

2. Description of the Related Art In recent years, a thin film transistor (TFT) has been actively developed for application to an image display device such as a flat panel display. It is desired to improve the operation speed of the TFT in order to cope with the increase in the size of the display and the use of the TFT in the peripheral drive circuit. Although attempts have been made to reduce the parasitic capacitance between the gate and drain in order to improve the operation speed of the TFT, the method of forming the source and drain electrodes in a self-aligned manner with the gate electrode is a very effective method.

FIG. 1 is a cross-sectional view of a conventional self-aligned TFT manufacturing method in which a source / drain region is formed in a self-aligned manner with a gate electrode by an ion implantation method, taking a laser polycrystalline semiconductor TFT as an example. This will be described with reference to FIG. A passivation film 42 and an amorphous semiconductor layer are stacked on an insulating substrate 41, the amorphous semiconductor layer is irradiated with laser light to be polycrystallized, and the pattern of the polycrystalline semiconductor thin film 43 is formed by photolithography. A gate insulating film 44 and a gate electrode material are stacked on the gate insulating film 44, and a pattern 45 of the gate electrode is formed again by photolithography. The gate insulating film 44 is also etched in the same pattern as the gate electrode.

Here, the polycrystalline semiconductor layer is doped with impurity ions by ion implantation using the gate electrode as a mask,
Source / drain regions 47 are formed by performing heat treatment for activating the impurity ions. Further, an interlayer insulating film 48 is deposited, contact holes are formed on the source / drain regions, and source / drain electrodes 49 are formed thereon.

[0005]

In the conventional method in which the gate insulating film 44 on the semiconductor layer is also etched in the same pattern as the gate electrode, and the gate electrode is used as a mask for ion implantation, a channel region below the gate electrode is formed. The structure is such that the source / drain regions are in contact with each other. In this structure the channel −
The electric field is concentrated near the drain boundary, and the leak current becomes abnormally large under the condition that the source-drain voltage is large. This phenomenon is particularly remarkable in the polycrystalline semiconductor thin film transistor. This means that such a TFT cannot be used for driving normally white liquid crystal, polymer dispersed liquid crystal, or the like, which has a large driving voltage.

Further, it is known that an abnormal increase in leak current can be prevented by providing a region of about 1 μm, which is not doped with impurity ions, between the gate electrode and the source / drain region. .. However, it is extremely difficult to realize a distance of about 1 μm with good reproducibility by the method of forming the pattern of the gate electrode and the mask for ion implantation by ordinary photolithography, and the number of steps is increased.

[0007]

The present invention has been made to solve the above problems, and a non-single crystal semiconductor layer, a gate insulating film, and a gate electrode are formed in this order on an insulating substrate, A method of manufacturing a thin film transistor, wherein source / drain regions are formed in a self-aligned manner with respect to a gate electrode by implanting impurity ions into a semiconductor layer using the gate electrode as a mask. The gate insulating film is etched without peeling off the photoresist formed above, and etching is further advanced from the side portion of the gate electrode so that the end portion of the gate electrode is located inside the gate insulating film. The present invention provides a method for manufacturing a thin film transistor, which is characterized by forming the thin film transistor.

The present invention will be described in detail below with reference to FIGS. 1 to 3 by taking a laser polycrystalline semiconductor TFT as an example.
First, plasma CVD, sputtering, depressurization CV is performed on an insulating substrate 1 such as glass, ceramic, or plastic.
D, SiO _x , SiN _x , SiO _x by atmospheric pressure CVD, etc.
A passivation film 2 (a film thickness possible range of 50 to 1000 nm) composed of a single layer or a multilayer film of N _y , TaO _x, etc., an amorphous semiconductor layer 3 (a non-single crystal semiconductor such as silicon (Si), germanium (Ge), etc. Possible film thickness range 10-200
0 nm) is formed.

In order to control the threshold voltage of the thin film transistor as necessary, impurities such as boron (B) or phosphorus (P) in the amorphous semiconductor layer 3 are tens to hundreds of ppm in the film thickness direction. Dope uniformly or non-uniformly.

The amorphous semiconductor layer 3 is polycrystallized by irradiating a laser beam, the polycrystal semiconductor layer is patterned by photolithography, and then plasma CVD, sputtering, low pressure CVD, atmospheric pressure CVD or the like is performed thereon. SiO
_x , SiN _x , SiO _x N _y , TaO _x, or the like, which is a gate insulating film 4 (thickness range 50 to 2).
000 nm), and a gate material composed of a single layer or a multilayer film of chromium (Cr), tantalum (Ta), aluminum (Al) or the like is further formed by a vacuum vapor deposition method, a sputtering method or the like, and a gate pattern is again formed by photolithography. The electrode 5 is formed. That is, the gate is patterned.

Here, without removing the photoresist 6, the gate insulating film 4 is etched using C ₂ F ₆ as an etching gas, and then the etching is further advanced from the side of the gate electrode 5 to form a gate. Electrode 5
Of the edge of the gate insulating film 4 from the distance d (0.5 to 2.0
It is formed on the inside only by about μm (FIG. 1).

Before the manufacturing process shown in FIG.
When the gate insulating film 4 is etched by dry etching containing oxygen gas as an etching gas, the photoresist on the gate electrode 5 is reduced simultaneously with the etching of the gate insulating film 4, and the gate electrode at the pattern end of the gate electrode 5 is reduced. Since the surface of the gate electrode 5 is exposed (FIG. 2), the additional etching from the side portion of the gate electrode 5 proceeds from the vicinity of the end portion and the side portion of the gate electrode 5.

A portion 7 which becomes the source / drain region of the polycrystalline semiconductor layer is formed by ion implantation using the gate electrode 5 as a mask.
Then, impurity ions such as P, B and arsenic (As) are doped at 5 × 10 ¹⁴ to 1 × 10 ¹⁶ ions / cm ² at an acceleration voltage of 1 to 40 kV. At this time, ions such as hydrogen (H) and fluorine (F) may be implanted at the same time, or PH _x , B _x H _y , and B ions may be implanted.
Molecular ions such as F _x may be implanted at the same time.

Although the gate electrode 5 is used as a mask, the gate insulating film 4 protrudes from the edge of the gate electrode 5 by about 0.5 to 2.0 μm, and P, P, and Since B or the like is not doped, 0.5 to 2.0 is provided between the source / drain region and the gate electrode 5.
An interval of approximately μm is provided, and this positional relationship does not require alignment, and is necessarily (self-aligned) determined.

The additional etching from the side of the gate electrode 5 and the removal of the photoresist of the gate electrode pattern may be performed before or after the ion implantation.
After performing heat treatment for activating impurity ions as necessary, an interlayer insulating film 8 is deposited, contact holes are formed on the source / drain regions, and source / drain 9 are formed thereon (FIG. 3). ..

The etching of the gate insulating film 4 is more preferably dry etching containing oxygen gas as an etching gas. This is because the photoresist 6 is also slightly reduced and the etching of the gate electrode 5 is facilitated. The case of the laser polycrystallized semiconductor has been described above as an example, but the present invention can be applied regardless of whether the semiconductor layer is an amorphous semiconductor or a polycrystalline semiconductor. In addition, a non-single crystal semiconductor is a concept including an amorphous semiconductor, a microcrystalline semiconductor, and a polycrystalline semiconductor.

[0017]

EXAMPLES Examples of the present invention will be described below. A 200 nm thick passivation film of SiO _x and a 100 nm thick amorphous semiconductor layer of a-Si were formed on a glass substrate (AN manufactured by Asahi Glass Co., Ltd.) by a plasma CVD method at a temperature of 450 ° C. of the glass substrate.

About 13 W of argon ion laser light is used.
The a-Si was polycrystallized by condensing and irradiating the light with a diameter of 0 μm. Polycrystalline Si is patterned into an island shape by photolithography, and SiN _{x is} formed on the island by plasma CVD.
A gate insulating film made of 200 nm was deposited at 300 ° C., and Cr 150 nm as a gate material was vapor-deposited at 300 ° C. by an electron beam heating vapor deposition method.

A conductor portion to be a gate electrode was formed on the gate pattern by photolithography. The photoresist is OFPR-800, Cr manufactured by Tokyo Ohka Kogyo Co., Ltd.
The etching solution is 0.3mm ceric ammonium nitrate.
A composition having a composition of mol / liter and perchloric acid of 2.6% was used at room temperature. Here, the gate insulating film was etched without peeling off the photoresist. This etching was performed by reactive ion etching, and the etching gas was CFCs of 5 SCCM and oxygen of 5 SCCM. After that, the glass substrate is again immersed in the above-mentioned Cr etching solution for 60 seconds to allow the etching to proceed from the side of the gate electrode, and the edge of the gate electrode is 1.0 (± 0.15) μm.
It was formed inside the gate insulating film. In this case, the width of the photoresist is narrower than that shown in FIG.

Since the etching gas for the gate insulating film contains oxygen gas, the photoresist on the gate electrode is reduced simultaneously with the etching of the gate insulating film, and the end surface of the gate electrode is exposed (FIG. 2). As for the additional etching from the side portion of the gate electrode, the etching proceeds from the end surface and the side portion of the gate electrode. C
When the immersion time of r in the etching solution was 100 seconds, the end of the gate electrode was formed inside the 1.3 (± 0.20) μm gate insulating film.

After removing the photoresist on Cr, P ions are accelerated into the source / drain region 7 of the polycrystalline Si island by ion implantation using Cr as a mask, and the acceleration voltage is 10 kV and the dose is 2 ×. Doping was performed under the condition of 10 ¹⁵ pieces / cm ² . Although the gate electrode is used as a mask, a 1.0 μm gate insulating film protrudes from the end of the gate electrode, and the polycrystalline semiconductor layer below the gate insulating film has P
Since the ions are not doped, a gap of 1.0 μm is provided between the source / drain region and the gate electrode. After heat treatment for activating the impurity ions, an interlayer insulating film 8 was deposited, contact holes were formed on the source / drain regions, and source / drain were formed thereon.

FIG. 5 is a drain current-gate voltage characteristic curve of a polycrystalline Si TFT (b) having a structure in which the TFT (a) according to the embodiment is in contact with the conventional source / drain region and the channel region under the gate electrode. is there. It can be seen that the leakage current when the gate is reverse biased is greatly reduced.

[0023]

According to the manufacturing method of the present invention, even if a high voltage is applied between the source and the drain, a leak current is small and a TFT having favorable characteristics can be manufactured by adding only one etching step. ..

The etching of the gate insulating film is performed by dry etching containing oxygen gas as an etching gas, and at the same time as the etching of the gate insulating film, the photoresist on the gate electrode is reduced to expose the gate electrode surface at the pattern end, If additional etching from the side of the electrode proceeds from the edge and side of the gate electrode, the etching time from the side of the gate electrode should be shortened to minimize the deterioration of the linearity of the edge of the gate electrode. It has the effect of suppressing

[Brief description of drawings]

FIG. 1 is a sectional view of a TFT showing a stage after etching a gate electrode in a manufacturing method of the present invention.

FIG. 2 is a cross-sectional view of a TFT showing a stage after etching a gate insulating film by dry etching in the manufacturing method of the present invention.

FIG. 3 is a sectional view of a TFT showing the final stage of the manufacturing method of the present invention.

FIG. 4 is a sectional view of a conventional TFT.

FIG. 5 is a drain current-gate voltage characteristic diagram of a TFT according to the present invention and a conventional TFT.

[Explanation of symbols]

 1 substrate 3 amorphous semiconductor layer 4 gate insulating film 5 gate electrode 6 photoresist

Claims (1)

[Claims] 1. A non-single-crystal semiconductor layer, a gate insulating film, and a gate electrode are formed in this order on an insulating substrate, and impurity ions are implanted into the semiconductor layer using this gate electrode as a mask, whereby the gate electrode is formed. In a method of manufacturing a thin film transistor in which source / drain regions are formed in a self-aligned manner, after patterning the gate electrode, the gate insulating film is etched without stripping the photoresist formed on the gate electrode, A method of manufacturing a thin film transistor, characterized in that an end portion of the gate electrode is formed inside the gate insulating film by further advancing etching from a side portion of the gate electrode.