JPH06301568A - Duplex processor system - Google Patents

Abstract

(57) [Abstract] [Purpose] Regarding the dual processor system, the active system C
Even if C10 becomes an obstacle, the spare MM21 is not destroyed,
Another object of the present invention is to provide a dual processor system in which the processing load of the active CC10 is light. [Structure] In a dual processor system that transfers data written in its own MM11 to a standby MM21 in an active CC10, a DMAC of an active system and a standby system
13 and 23 are respectively divided into DMACs 16 and 26 dedicated to transmission and DMACs 17 and 27 dedicated to reception, and the inter-system communication control units 14 and 24 of the active system and the standby system are respectively dedicated to the reception-only DMAC 17 of the standby system and the active system. 27 are connected by the intersystem buses 31 and 32, respectively, and when the active CC 10 sets the start address and the number of words of transfer data in the DMAC 16 dedicated to transmission of its own system, Intercommunication control unit 14
And the inter-system communication control unit 14 of its own system is activated and sent to the DMAC 27 dedicated to reception of the standby system via the inter-system bus 31 for setting.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvement of a dual processor system used for voice communication, data communication and the like.

In a dual processor system, when a failure occurs in the active system, it is necessary to quickly switch to the standby system and continue processing. Therefore, the contents of the main memories of the active system and the standby system are always matched. However, if the contents are matched, the processing load of the central control unit (hereinafter referred to as CC) is light, and the CC of the active system does not cause damage to the main memory of the standby system in the event of a failure. Is desired.

[0003]

2. Description of the Related Art FIG. 2 is a block diagram of a conventional dual processor system, and FIG. 3 is a block diagram of another conventional dual processor system.

In the case of FIG. 3, the active system CC 10 and the active system main memory (hereinafter referred to as MM) 11 are the system bus 80.
Connected to the standby MM21 via the system bus 81, the standby CC20 and the standby MM21 connected to the system bus 82, and the active MM11 connected to the system bus 83. ing.

Then, the active CC 10 is replaced by the system bus 8
When writing data to the active MM11 via 0,
By writing the same data to the standby MM21 via the system bus 81, the active and standby MM11,
The contents of 21 are matched.

In the case of FIG. 2, the active system CC10, the active system MM11, the active system direct memory access control unit (hereinafter referred to as DMAC) 51, and the inter-system communication control unit (hereinafter referred to as ISC).
52, buffer memory (hereinafter referred to as BM) 5
An inter-system control device (hereinafter referred to as ISC) 50 having 3 is connected by a system bus 40, and a standby MM 21 and
The spare system DMAC 61, ISCC 62, and ISC 60 having BM 63 are connected by the system bus 41.

The active system CC10 is the active system MM11.
When data is written to the DMAC 51,
In the register in the DMAC shown in (B), the start address is set in the memory address register 70, and the number of words of transfer data is set in the memory transfer counter 71.
As shown in (A), the transmission data in which the start address of the transfer data and the number of words are added to the beginning of the transfer data is MM.
Edit on 11 and launch ISCC 52.

The ISCC 52 makes an operation request to the DMAC 51, and the MM 11 transfers the transmission data shown in FIG. 2A, in which the start address of the transfer data and the number of words are added to the head of the transfer data, to the BM 53.

Then, the ISCC 52 communicates with the standby ISCC 62 via the intersystem bus 32, and transfers the transmission data shown in FIG. 2 (A) transferred to the BM 53 to the BM 63.
The standby ISCC 62 sets the start address and the number of words added to the transfer data in the DMAC 61 to make an operation request, and transfers the transfer data transferred to the BM 63 to the MM 21 and D
Transfer from the start address set in the MAC 61.

In this way, the active system MM11 and the standby system M
The contents of M21 are matched.

[0011]

However, in the dual processor system of FIG. 3, there is a problem that the standby system MM21 to be switched may be destroyed when the active system CC10 fails. In the redundant processor system, each time the active CC 10 writes data to the MM 11, the transmission data in which the start address of the transfer data and the number of words are added to the start of the transfer data on the MM 11 as shown in FIG. 2A. I have to edit the current CC
There is a problem that the processing load of 10 is large.

It is an object of the present invention to provide a dual processor system which does not destroy the MM21 of the standby system even when the active system CC10 becomes a failure and has a light processing load on the active system CC10.

[0013]

FIG. 1 is a block diagram of a dual processor system according to an embodiment of the present invention. As shown in FIG. 1, CC10, 20, MM11, which are connected to the active system and the standby system by respective system buses 40, 41,
21, and DMACs 13, 23, ISCCs 14, 24,
The ISCs 12 and 22 having the BMs 15 and 25 respectively are provided, and the head address read from the MM11 of the own system when the data written in the MM11 of the own system is transferred to the MM21 of the standby system by the CC10 of the active system. And the number of words of transfer data are set in the DMAC 13 of the own system, and the IS of the own system is set.
When the CC 14 is activated, the ISCC 14 of the own system issues an operation request to the DMAC 13 of the own system, and the DM of the own system is DMC 13.
The AC 13 causes the MM 11 of the own system to transfer the data to the BM 15 of the own system according to the items set above, and the transferred data is
When sent to the ISCC 24 of the standby system and transferred to the BM 25 of the standby system, the ISC 24 of the standby system becomes DM of the standby system.
In the duplex processor system that requests the AC 23 to operate and transfers the data transferred to the BM 25 of the standby system to the MM 21 of the standby system, the DM of the active system and the standby system
The ACs 13 and 23 are divided into transmission-only DMACs 16 and 26 and reception-only DMACs 17 and 27, respectively.
The standby ISCCs 14 and 24 are connected to the standby DMACs 17 and 27 dedicated to reception of the working system by the intersystem buses 31 and 32, respectively, and the CC 10 of the working system is connected to the CCs of the working system. When setting the start address and the number of words of transfer data in the DMAC 16 dedicated to transmission, the ISCC 1
4 is also sent, the ISCC 14 of the own system is activated, and is sent to the receive-only DMAC 27 of the standby system via the inter-system bus 31 to be set.

[0014]

According to the present invention, when the data written in the MM11 by the CC10 is transferred to the standby MM21, the start address and the number of words of transfer data read from the own MM11 are set in the DMAC16 dedicated to transmission. When you do
The ISCC 14 of the own system is also transmitted to activate the ISCC 14 of the own system.

Then, the ISCC 14 sends the start address and the number of words of the transfer data to the DMAC 27 dedicated to reception of the standby system via the intersystem bus 31 and sets the MM1 to the operation dedicated to the DMAC 16 dedicated to transmission.
Data of the number of words set from the first address of 1 is BM
Transfer to No. 15 and communicate with standby ISCC 24, B
The data transferred to M15 is transferred to BM25 of the preliminary system.

Then, the ISCC 24 of the standby system makes an operation request to the DMAC 27 dedicated to reception, and causes the data transferred to the BM 25 to be transferred to the MM 21 from the set start address. That is, the active system CC10 can transfer the data written in the MM11 to the standby system MM21 by setting the start address and the number of transfer words in the DMAC16 dedicated to transmission, sending the same to the ISCC14, and activating the ISCC14. Therefore, the processing load on the CC 10 is reduced. Also, since the data written in the MM11 is transferred to the MM21 by using the BMs 15 and 25, C
Even if C10 becomes an obstacle, it does not destroy MM21.

[0017]

1 is a block diagram of a dual processor system according to an embodiment of the present invention. 1 is different from the conventional example shown in FIG.
6, 26, DMACs 17 and 27 dedicated to reception, and the ISCC 14 is a DMAC 2 dedicated to reception on the intersystem bus 31.
7, the ISCC 24 is connected to the receive-only DMAC 17 through the intersystem bus 30, and the active CC 10 is connected to the MM 11
In order to transfer the data written in the MM21 to the standby MM21, the start address and the number of transfer words are assigned to the DMA for transmission only.
Set to C16 and send to ISCC14, and IS
The point is that the CC 14 is activated and is set in the receive-only DMAC 27 of the standby system via the intersystem bus 31.

In this way, the ISCC 14 makes CC1
When activated at 0, the ISCC 14 is a DMA dedicated for transmission.
The operation request is sent to C16, and the data of the set number of words is transferred to the BM15 from the start address of the set MM11.
By communicating with the standby ISCC 24, the data transferred to the BM 15 is transferred to the standby BM 25.

Then, the standby ISCC 24 requests the receive-only DMAC 27 to operate, and causes the data transferred to the BM 25 to be transferred to the MM 21 from the set start address. That is, the active system CC10 can transfer the data written in the MM11 to the standby system MM21 by setting the start address and the number of transfer words in the DMAC16 dedicated to transmission, sending the same to the ISCC14, and activating the ISCC14. Therefore, the processing load on the CC 10 is reduced. Also, since the data written in the MM11 is transferred to the MM21 by using the BMs 15 and 25, C
Even if C10 becomes an obstacle, it does not destroy MM21.

[0020]

As described in detail above, according to the present invention, even if the active CC becomes an obstacle, the standby MM 21 is not destroyed, and the processing load of the active CC 10 can be lightened. is there.

[Brief description of drawings]

FIG. 1 is a block diagram of a dual processor system according to an embodiment of the present invention,

FIG. 2 is a block diagram of a conventional dual processor system;

FIG. 3 is a block diagram of another conventional dual processor system.

[Explanation of symbols]

 10 and 20 are central control devices, 11 and 21 are main memories, 12, 22, 50 and 60 are inter-system control devices, 13, 23, 51 and 61 are direct memory access control units, and 14, 24, 52 and 62 are Inter-system communication control unit, 15, 25, 53, 63 are buffer memories, 16 and 26 are transmission-only direct memory access control units, 17 and 27 are reception-only direct memory access control units, 30 to 32 are inter-system buses, 40, Reference numerals 41, 80 to 83 denote system buses.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Keiko Yuki 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Within Fujitsu Limited

Claims (1)

[Claims] 1. A central control unit (1) connected to an active system and a standby system by respective system buses (40, 41).
0, 20), main memory (11, 21), direct memory access control unit (13, 23), inter-system communication control unit (1
4, 24) and a buffer memory (15, 25), respectively, and an inter-system controller (12, 22) is provided, and the main controller (10) of the active system writes the data to the main memory (11) of its own system. In order to transfer the data to the main memory (21) of the spare system, the head address and the number of words of transfer data read from the main memory (11) of the own system are set to the direct memory access control unit (13) of the own system. And the inter-system communication control unit (14) of the self system is activated, the inter-system communication control unit (14) of the self system causes the direct memory access control unit (1) of the self system.
3), the direct memory access control unit (13) of the local system transfers the data from the main memory (11) of the local system to the buffer memory (15) of the local system according to the items set above. The transferred data is sent to the inter-system communication control unit (24) of the standby system, and the buffer memory (25) of the standby system.
Then, the inter-system communication control unit (24) of the standby system makes an operation request to the direct memory access control unit (23) of the standby system, and the data transferred to the buffer memory (25) of the standby system is transferred. In the duplex processor system for transferring to the main memory (21) of the standby system, the direct memory access control units (13, 23) of the active system and the standby system are respectively dedicated to transmission. ) And a direct memory access control unit (17, 27) dedicated to reception, and an inter-system communication control unit (14, 2) of the active system and the standby system.
4) Each of them is connected to each of the direct memory access control units (17, 27) dedicated to reception of the standby system and the active system by the intersystem bus (31, 32), and the central control of the active system is performed. When the device (10) sets the head address and the number of words of transfer data in the direct memory access control unit (16) dedicated to the transmission of the own system, it also applies to the intersystem communication control unit (14) of the own system. The transmission is performed, the inter-system communication control unit (14) of the own system is activated, and is sent to the direct memory access control unit (27) dedicated to reception of the standby system via the inter-system bus (31) for setting. A dual processor system characterized by the above.