JPH06291553A - Fm signal demodulator - Google Patents

Abstract

PURPOSE:To obtain the digital FM signal modulator capable of easily making it small in size and into IC. CONSTITUTION:The FM signal demodulator consists of a 90 deg. phase shifter 13 for phase-shifting by 90 deg. the phase of an input FM signal, a delay device 14 for delaying the input FM signal by one sampling period, a subtracter 15 and an adder 16 for deriving a difference and the sum of the input FM signal and an output of the delay device 14, a delay device 17 for delaying an output of the 90 deg. phase shifter 13 by one sampling period, an adder 18 and a subtracter 19 for deriving the sum and a difference of an output of the phase shifter 13 and an output of the delay device 17, and a devider 21 for deriving the quotient of two outputs in the outputs of the subtracter 15, the adder 16, the adder 18 and the subtracter 19.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a digitized FM.
The present invention relates to an FM demodulator that demodulates a signal.

[0002]

2. Description of the Related Art FIG. 5 shows a conventional digital FM demodulator shown in U.S. Pat. No. 4,090,145. In the figure, 1 is an input terminal for an analog FM signal, and 2 is an input terminal 1.
The quadrature sampling A / D converter that digitizes the FM signal that is input from and outputs two signals, 3 is a divider that divides the two outputs of the quadrature sampling A / D converter 2, and 4 is A calculator 5 for obtaining the arctangent of the output of the divider 3 is a differentiator for differentiating the output of the calculator 4, and 6 is an output terminal thereof.

Next, the operation will be described. The analog FM signal input from the input terminal 1 is orthogonal sampling A
It is digitized in the / D converter 2. The quadrature sampling A / D converter 2 shifts the sampling timing and outputs two digital signals orthogonal to each other. Therefore, two output signals at time kT (T is a sampling period, k is an integer) are respectively

[0004]

[Equation 1]

Can be approximately expressed as Orthogonal sampling A
The / D converter 2 has two sampling timings,
Π / with respect to the center frequency of the input FM signal
An approximate configuration can be achieved by setting them so that they are offset from each other. The two signals X (k) and Y (k) output from the orthogonal sampling A / D converter 2 are input to the divider 3,

[0006]

[Equation 2]

Is calculated and output. The calculator 4 calculates the arctangent of the output of the divider 3. That is,
The arithmetic unit 4 is

[0008]

[Equation 3]

Is output. Here, from equations (3) and (4),

[0010]

[Equation 4]

Therefore, the output θ (k) of the arithmetic unit 4 can be regarded as equal to the phase φ (k) of the input FM signal. The differentiator 5 calculates the difference between the output θ (k) of the calculator 4 and the output θ (k−1) of the calculator 4 one sampling period before, and outputs the difference from the output terminal 6.

[0012]

[Equation 5]

Since the time-differentiated phase φ of the FM signal becomes the demodulated signal, the output θ (k) -θ of the differentiator 5
(K-1) becomes a demodulated signal.

[0014]

Since the conventional FM demodulator is constructed as described above, the ROM for obtaining the arc tangent is required, which makes the device compact and IC
It was extremely unfavorable to change.

The present invention has been made to solve the above problems, and an object of the present invention is to provide an FM demodulator which does not require a ROM and can be easily downsized and integrated into an IC.

[0016]

An FM demodulator according to the present invention includes a 90 ° phase shifter for shifting an input digital FM signal by 90 ° and a first delay device for delaying the input digital FM signal by one sampling period. A first subtractor for obtaining the difference between the input digital FM signal and the output of the first delay device; a first adder for obtaining the sum of the input digital FM signal and the output of the first delay device; A second delay device that delays the output of the phase shifter by one sampling period, and a second adder that obtains the sum of the output of the 90 ° phase shifter and the output of the second delay device,
A second subtractor for obtaining the difference between the output of the 90 ° phase shifter and the output of the second delay device, the first subtractor, the second subtractor, the first adder, and the second addition It is provided with a divider that selects two of the outputs of the container and obtains their quotient.

Further, the FM demodulator according to the present invention has a sum of absolute values of the outputs of the first subtractor and the second adder, the output of the first adder and the second adder. The absolute value sums of the outputs of the subtractors are compared, and when the former is large, the divider calculates the quotient of the output of the first subtractor and the output of the second adder, and when the latter is large, the division is performed. The multiplier is configured to obtain the quotient of the output of the second subtractor and the output of the first adder.

Further, the FM demodulator according to the present invention is the sum of squares of the output of the first subtractor and the output of the second adder, the output of the first adder and the second subtraction. The sums of squares of the outputs of the adders are compared, and when the former is large, the divider calculates the quotient of the outputs of the first subtractor and the second adder,
When the latter is large, the divider is configured to obtain the quotient of the output of the second subtractor and the output of the first adder.

[0019]

In the FM demodulator of the present invention, the difference or the sum of the input digital FM signal and the signal obtained by delaying the FM signal by one sampling period is shifted by 90 ° from the signal obtained by shifting the input FM signal by 90 °. Since the demodulated output of the FM signal can be obtained by dividing the generated signal by the sum or difference with the signal delayed by one sampling period, the ROM having the arctangent table is not necessary.

[0020]

EXAMPLES Example 1. Hereinafter, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an FM demodulator according to an embodiment of the present invention. In the figure, 10 is an input terminal for an analog FM signal, 11 is an A / D converter for digitizing the analog FM signal input from the input terminal 10, and 12 is a digital FM signal output from the A / D converter 11. A delay corrector 13 for delaying shifts the phase of the digital FM signal output from the A / D converter 11 by 90 °.
A phase shifter, 14 is a delay device for delaying the output of the delay compensator 12 by one sampling period, 15 is a subtracter for obtaining a difference between the output of the delay compensator 12 and the output of the delay compensator 14, and 16 is the delay compensator 12 And an output of the delay device 14, an adder 17 delays the output of the 90 ° phase shifter 13 by one sampling period, and an output 18 of the 90 ° phase shifter 13 and the delay device 17. An adder for obtaining the sum of outputs, 19 is a subtractor for obtaining the difference between the output of the 90 ° phase shifter 13 and the output of the delay device 17, and 20 is the subtractor 15, the adder 16, the adder 18 and the subtractor 19 described above. A selection circuit that selects two outputs from the outputs, and a divider 21 that divides the two outputs of the selection circuit 20.

Next, the operation will be described. Input terminal 10
The input analog FM signal is converted into a digital signal by the A / D converter 11. Digitized FM
The signal is phase shifted by 90 ° by the 90 ° phase shifter 13. On the other hand, A
The FM signal digitized by the / D converter 11 is also input to the delay corrector 12 and delayed by the same time as the delay time generated in the 90 ° phase shifter 13. Therefore, the delay corrector 1
When the output of 2 is X and the output of the 90 ° phase shifter 13 is Y,
X and Y are signals which are digitized at the same time and have phases different from each other by 90 °. That is, the values of the signals X and Y at time kT (T is a sampling cycle, k is an integer) are X (k) and Y (k), respectively, and the amplitude of the signal X is A,
If the phase is φ (k),

[0022]

[Equation 6]

[Apply]

The signal X output from the delay corrector 12
(K) is delayed by one sampling period T in the delay device 14. The subtractor 15 outputs the output X of the delay corrector 12.
The difference between (k) and the output X (k-1) of this delay device 14,

[0025]

[Equation 7]

Is output. The adder 16 is the delay compensator 1
2 output X (k) and delay unit 14 output X (k-1),

[0027]

[Equation 8]

Is output. On the other hand, the output Y (k) of the 90 ° phase shifter 13 is delayed by one sampling period T in the delay unit 17. The adder 18 is the sum of the output Y (k) of the 90 ° phase shifter 13 and the output Y (k−1) of the delay unit 17,

[0029]

[Equation 9]

Is output. The subtractor 19 calculates the difference between the output Y (k) of the 90 ° phase shifter 13 and the output Y (k−1) of the delay device 17,

[0031]

[Equation 10]

Is output.

The selection circuit 20 includes a subtractor 15, an adder 16,
Two of the outputs of the adder 18 and the subtractor 19 are selected and output. The first output of the selection circuit 20 is P (k),
The second output is Q (k). The two outputs of the selection circuit 20 are the output DX (k) of the subtractor 15 and the output SY (k) of the adder 18, or the output DY (k) of the subtractor 19 and the output SX (k) of the adder 16. Is. That is,

[0034]

[Equation 11]

[0035] Two outputs P of the selection circuit 20
(K) and Q (k) are input to the divider 21,

[0036]

[Equation 12]

Is calculated and output. If the signals output from the selection circuit 20 are the output DX (k) of the subtractor 15 and the output SY (k) of the adder 18, (9), (1
From equations (1) and (13),

[0038]

[Equation 13]

Is satisfied. Further, the signal output from the selection circuit 20 is the output DY (k) of the subtractor 19 and the adder 1
In the case of the output SX (k) of 6 also, (10), (1
From 2) and (14),

[0040]

[Equation 14]

Holds. Generally, if α is close to 0,

[0042]

[Equation 15]

Therefore, if the sampling frequency is made sufficiently high so that φ (k) −φ (k−1) becomes close to 0,

[0044]

[Equation 16]

It becomes As mentioned above, φ (k) -φ (k-1)
Is a demodulation component, the output s (k) of the divider 21 becomes a demodulation component from the equation (19).

As described above, even if the selection circuit 20 selects the two outputs P (k) and Q (k) according to the equation (13),
Even if the formula (14) is selected, the output s of the divider 21
(K) is a demodulation component. However, when P (k) and Q (k) are selected as in equation (13), equations (9) and (11)
From the formula,

[0047]

[Equation 17]

When is true, DX (k) = SY
Since (k) = 0, the equation (16) does not hold exceptionally. Therefore, the output s (k) of the divider 21 does not become a demodulation component. Also,

[0049]

[Equation 18]

Even if is not 0, the demodulation component s (k) output from the divider 21 has low accuracy when it is close to 0. Similarly, when P (k) and Q (k) are selected as in equation (14),

[0051]

[Formula 19]

When is true, SX (k) = DY
Since (k) = 0, the output s (k) of the divider 21 does not become a demodulation component. Also,

[0053]

[Equation 20]

Even if is not 0, the accuracy of the demodulation component s (k) output from the divider 21 is low when it is close to 0. However,

[0055]

[Equation 21]

Since 0 does not become 0 at the same time, when the former absolute value is large, P (k), Q
The selection circuit 20 may be configured so that (k) is selected, and when the latter is larger, P (k) and Q (k) are selected as in equation (14).

FIG. 2 shows a configuration example of such a selection circuit 20. In the figure, 201 is the input terminal of the signal DX (k) output from the subtractor 15, 202 is the input terminal of the signal DY (k) output from the subtractor 19, and 203 is the adder 1
8, an input terminal of the signal SY (k) output from 8, an input terminal of the signal SX (k) output from the adder 16,
205 is a signal DX (k) input from the input terminal 201
And a switch for selecting and outputting one of the signals DY (k) input from the input terminal 202 and 206, the input terminal 20
A switch 207 for selecting and outputting one of the signal SY (k) input from 3 and the signal SX (k) input from the input terminal 204, and 207 is input terminals 201, 202, 203,
Switch 20 based on the four signals input from 204
This is a judging device for controlling 5, 206. 4 signals DX
(K), DY (k), SY (k), SX (k)

[0058]

[Equation 22]

If it is determined that the switches 205 and 206 select the signals DX (k) and SY (k), respectively, and if not determined, the switches 205 and 206 respectively detect the signals DY (k) and SX (k). ) Is controlled to select.

[0060]

[Equation 23]

Therefore, the decision unit 207

[0062]

[Equation 24]

When the above is true, it can be determined that the above equation (21) is true. Also, to simplify the calculation,
Approximately

[0064]

[Equation 25]

When the above is true, it may be determined that the above equation (21) is true.

3 and 4 show demodulation examples by the FM demodulator of the present invention. The input signal is a sine wave of 3 MHz, the center frequency of the carrier is 6.2 MHz, and the frequency deviation is 0.
It is an FM signal when FM-modulated at 8 MHz. FIG. 3 shows this FM signal in the FM demodulator of the present invention shown in FIG. 1 in which the selection circuit 20 always outputs signals DX (k) and SY (k).
5 shows a demodulated signal when is output. In this case, some areas cannot be demodulated as described above.
On the other hand, FIG. 4 shows the signal DX when the selection circuit 20 satisfies the equation (25) in the FM demodulator of the present invention shown in FIG.
Outputs (k) and SY (k), otherwise outputs signal DY
5 shows a demodulated signal when configured to output (k) and SX (k). In this case, it can be seen that demodulation can be performed completely.

[0067]

As described above, according to the present invention, FM demodulation can be performed by simple calculation, and ROM of arctangent is not required. Therefore, an FM demodulator which is inexpensive and easy to miniaturize can be obtained. There is.

[Brief description of drawings]

FIG. 1 is a block diagram showing an FM demodulator according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration example of a selection circuit of an FM demodulator according to an embodiment of the present invention.

FIG. 3 is a waveform diagram showing a demodulation example of the FM demodulator according to the embodiment of the present invention.

FIG. 4 is a waveform diagram showing another demodulation example of the FM demodulator according to the embodiment of the present invention.

FIG. 5 is a block diagram showing a conventional FM demodulator.

[Explanation of symbols]

 13 90 ° phase shifter 14, 17 delay device 15, 19 subtractor 16, 18 adder 21 divider

[Procedure amendment]

[Submission date] June 28, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0066

[Correction method] Change

[Correction content]

3 and 4 show demodulation examples by the FM demodulator of the present invention. The input signal has a sine wave of 3 MHz, a carrier center frequency of 6.2 MHz, and a frequency deviation of 0.
This is an FM signal when FM-modulated at 8 MHz. FIG. 3 shows this FM signal in the FM demodulator of the present invention shown in FIG. 1 in which the selection circuit 20 always outputs signals DX (k) and SY (k).
5 shows a demodulated signal when is output. In this case, some areas cannot be demodulated as described above.
On the other hand, FIG. 4 shows the signal DX when the selection circuit 20 satisfies the equation (25) in the FM demodulator of the present invention shown in FIG.
Outputs (k) and SY (k), otherwise outputs signal DY
5 shows a demodulated signal when configured to output (k) and SX (k). In this case, it can be seen that demodulation can be performed completely.

Claims (3)

[Claims] 1. A 90 ° phase shifter for shifting an input digital FM signal by 90 °, a first delay device for delaying the input digital FM signal by one sampling period, and an input digital F
A first subtractor for obtaining the difference between the M signal and the output of the first delay device, a first adder for obtaining the sum of the input digital FM signal and the output of the first delay device, and the 90 ° phase shifter. Output of 1
A second delay device for delaying the sampling period, and the above 90 °
A second adder for obtaining the sum of the output of the phase shifter and the output of the second delay device, and a second subtractor for obtaining the difference between the output of the 90 ° phase shifter and the output of the second delay device. And a divider that selects two of the outputs of the first subtractor, the second subtractor, the first adder, and the second adder, and obtains their quotient. FM demodulator. 2. A sum of absolute values of the outputs of the first subtractor and the second adder, and a sum of absolute values of outputs of the first adder and the second subtractor. If the former is large, the divider calculates the quotient of the output of the first subtractor and the output of the second adder, and if the latter is large, the divider outputs the output of the second subtractor. The FM according to claim 1, wherein the FM is configured to obtain a quotient of the output of the
Demodulator. 3. The sum of squares of the output of the first subtractor and the output of the second adder is compared with the sum of squares of the output of the first adder and the output of the second subtractor. If the former is large, the divider calculates the quotient of the output of the first subtractor and the output of the second adder, and if the latter is large, the divider is the output of the second subtractor. The FM demodulator according to claim 1, wherein the FM demodulator is configured to obtain a quotient of the output of the adder of 1.