JP2553643B2 - Carrier synchronizer - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a carrier synchronization device used in a wireless communication system or the like using a digital modulation method.

2. Description of the Related Art FIG. 5 shows a conventional carrier synchronizer.

In Figure 5, the received signal S (t) S (t) = cos (ω c t + φ (t)): the (omega _c angular frequency of the carrier wave) is input to the terminal 20, the clock reproduction circuit 26, the transmission data CLK (t) synchronized with timing To play.

On the other hand, the output signal C (t) of the voltage controlled oscillator (VCO) 29
The C (t) = cos (ω c t-θ): When (theta phase difference between the carrier wave), the output signal of the first multiplier 21, And the output signal of the second multiplier 23 is Becomes

When the first term of these output signals is taken out by the first and second low pass filters 22 and 24, respectively, the former is treated as an in-phase component I signal and the latter is treated as a quadrature component Q.
Treated as a signal.

When the I signal and the Q signal are multiplied by the third multiplier 25, Where MSK is the modulation method and a _n (=
± 1), the above equation becomes Becomes

Next, when this signal is multiplied by the clock CLK (t) from the clock recovery circuit 26 by the fourth multiplier 27, the output is (Decoding same order, corresponding to data), and when the low-pass component of this signal is extracted by the third low-pass filter 28, the data-independent signal g (θ) By controlling the voltage controlled oscillator 29 with this signal g (θ), the phase difference θ with the carrier wave is brought close to “0”.

Therefore, in the above-mentioned conventional example, the output signals of the first and second low-pass filters 22 and 24 are multiplied by the third multiplier 25, and the multiplied signal is multiplied by the clock recovery circuit 26.
The clock CLK (t) synchronized with the transmission data from the
A signal synchronized with the carrier wave of the received signal can be obtained by performing multiplication by the multiplier 27.

However, in the above-described conventional carrier synchronizer, the phase difference detection signal g serving as the control signal for the voltage controlled oscillator 29 is obtained.
Since (θ) is a signal in which π is one cycle, as shown in FIG. 6, the phase difference θ in 0 ≦ θ ≦ π / 4 and π / 4 ≦ θ
The phase difference θ in ≦ π / 2 cannot be identified, and similarly, the phase difference θ in −π / 2 ≦ θ ≦ −π / 4 and −π / 4 ≦
There is a problem that the phase difference θ when θ ≦ 0 cannot be identified.

In view of the above conventional problems, the present invention provides a phase difference θ between the received signal and the output signal of the voltage controlled oscillator, which is −π / 2 ≦ θ ≦ π / 2.
It is an object of the present invention to provide a carrier synchronization device which can be accurately identified and detected as one value in the range of 1 and can reliably synchronize each signal.

Means for Solving the Problems In order to achieve the above object, the present invention uses the output signals of the first and second low-pass filters and the clock from the clock recovery circuit to output a received signal and an output signal of a voltage controlled oscillator. A signal according to the phase difference is detected and the voltage controlled oscillator is controlled by this signal.

Operation The present invention does not multiply the output signals of the first and second low-pass filters, unlike the conventional example, by the above configuration,
The phase difference θ between the received signal and the output signal of the voltage controlled oscillator is −
It is possible to accurately identify and detect one value in the range of π / 2 ≦ θ ≦ π / 2, and to reliably synchronize the respective signals.

Embodiments Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a carrier synchronization device according to the present invention, FIG. 2 is an explanatory diagram of a complex number representation in the baseband of the modulation signal of FIG. 1, and FIG.
FIG. 4 is an explanatory diagram showing the relationship among time, I signal, Q signal, and distance r, and FIG. 4 is an explanatory diagram showing the phase difference detection characteristic of the carrier synchronizer of FIG.

In FIG. 1, 11 is a multiplier for multiplying the received signal S (t) by an output signal C (t) of a voltage controlled oscillator (VCO) 17 that oscillates a signal with a variable phase, and 13 is a received signal. S
A multiplier for multiplying (t) by the output signal of the voltage controlled oscillator 17 whose phase is delayed by π / 2 by the π / 2 phase shifter 18, 1
Reference numerals 2 and 14 are low-pass filters (LPFs) for extracting low-frequency components of the output signals of the multipliers 11 and 13, respectively.

Reference numeral 15 is a clock regeneration circuit for regenerating a clock CLK (t) synchronized with the timing of transmission data by the received signal S (t), and 16 is a low pass filter 12, 14 as described later.
Of the received signal S (t) and the oscillation signal of the voltage controlled oscillator 17 are detected by the signal from the clock recovery circuit 15 and the clock from the clock recovery circuit 15, and the voltage controlled oscillator is detected according to the phase difference.
It is a phase difference detection circuit for controlling the phase of the output signal of 17.

 Next, the operation of the above embodiment will be described.

In Figure 1, the received signal S (t) S (t) = cos (ω c t + φ (t)): the (omega _c angular frequency of the carrier wave) is inputted, a clock reproduction circuit 15, in synchronism with the timing of the transmission data CLK (t) To play.

On the other hand, the output signal C (t) of the voltage controlled oscillator (VCO) 17
The C (t) = cos (ω c t-θ): When (theta phase difference between the carrier wave), the output signal of the multiplier 11, And the output signal of the multiplier 13 is Becomes

When the first terms of these output signals are taken out by the low-pass filters 12 and 14, respectively, the former is treated as an in-phase component I signal and the latter is treated as a quadrature component Q signal.

In addition, the I signal and the Q signal are each doubled to obtain a real number,
If it is an imaginary number, it can be expressed as shown in FIG.

 Next, the operation of the phase difference detection circuit 16 will be described.

Here, if the modulation system of the received signal is the MSK system, When the synchronization with the carrier wave is established, at t = 2kT (k: integer), I = ± 1, Q = 0, and at t = (2k + 1) T, I = 0, Q = ± 1. Become.

On the other hand, when the synchronization with the carrier wave is not established, I = cos (φ (t) + θ) Q = sin (φ (t) + θ) Therefore, at t = 2kT, the position A shown in FIG. A signal exists at B, and at t = (2k + 1) T, a signal exists at positions C and D shown in FIG.

Therefore, the phase difference detection circuit 16 is, as shown in FIG.
The quadrant of the coordinates where the signal is located is determined by the sign of the I signal and the Q signal when t = 2kT and t = (2k + 1) T, and the position of this quadrant and the clock CLK from the clock regeneration circuit 15 are determined. The distance r is obtained from (t).

The absolute value of this distance r is, as shown in FIG. Therefore, as shown in FIG. 4, the signal f (θ) indicating the phase difference detection characteristic becomes a signal having 4π as one cycle, and the phase difference θ between the received signal and the output signal of the voltage controlled oscillator is −π. / 2
It is possible to accurately identify and detect one value within the range of ≦ θ ≦ π / 2, and to reliably synchronize the respective signals.

In the above embodiment, the phase difference θ between the carrier wave of the received signal and the output signal of the voltage controlled oscillator 17 is synchronized with an integral multiple of π, but there is no problem when decoding the received data.

As described above, the present invention responds to the phase difference between the received signal and the output signal of the voltage controlled oscillator by the output signals of the first and second low pass filters and the clock from the clock recovery circuit. Since the signal is detected and the voltage-controlled oscillator is controlled by this signal, the phase difference θ between the received signal and the output signal of the voltage-controlled oscillator is exactly 1 within the range of −π / 2 ≦ θ ≦ π / 2. Detected by specifying one value, each signal can be reliably synchronized.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a carrier synchronization device according to the present invention, FIG. 2 is an explanatory diagram of a complex number representation in the baseband of the modulation signal of FIG. 1, and FIG. 4 is an explanatory diagram showing the relationship among time, I signal, Q signal and distance r, FIG. 4 is an explanatory diagram showing the phase difference detection characteristics of the carrier synchronizer of FIG. 1, and FIG. 5 is a conventional carrier synchronization. FIG. 6 is a block diagram showing the device, and FIG. 6 is an explanatory diagram showing the phase difference detection characteristics of the carrier synchronization device of FIG. 11, 13 …… Multiplier, 12, 14 …… Low-pass filter (LP
F), 15 ... Clock recovery circuit, 16 ... Phase difference detection circuit, 17 ... Voltage controlled oscillator (VCO), 18 ... π / 2 phase shifter.

Claims (1)

(57) [Claims] 1. A clock regenerating circuit for regenerating a clock synchronized with the timing of transmission data by a received signal, a voltage controlled oscillator for generating a signal whose phase is variable, and a phase of an output signal of the voltage controlled oscillator is π / 2. A first phase-shifter for multiplying a received signal by an output signal of the voltage-controlled oscillator;
, A second multiplier for multiplying the received signal by the output signal of the phase shifter, and first and second low-frequency components of the output signals of the first and second multipliers, respectively. A signal corresponding to the phase difference θ between the received signal and the output signal of the voltage controlled oscillator is detected by the low-pass filter, the output signals of the first and second low-pass filters, and the clock from the clock recovery circuit, A phase difference detection circuit for controlling the voltage controlled oscillator by this signal, wherein the phase difference detection circuit determines a phase difference θ between the received signal and the output signal of the voltage controlled oscillator as −π / 2 ≦ θ ≦ π / 2. The carrier synchronization device is characterized in that one value is specified and detected within the range, and the voltage controlled oscillator is controlled in order to synchronize the respective signals.