JPS62222744A - Synchronous detection circuit for msk system signal - Google Patents

Abstract

PURPOSE:To improve the degree of freedom of design for components constitut ing the titled circuit, especially a VCO and a DC amplifier by using a synchro nous detection circuit for a demodulation circuit of an MSK signal or the like so as to bring the output voltage of the synchronizing state of the circuit to 0V. CONSTITUTION:The DC component of a clock 20 is cut off by a capacitor C2 and the result is fed to a resistor R3. The waveform is a rectangular waveform of means voltage 0V. In case a switch 26 is closed to ground, an operational amplifier 25 acts like an inverse amplifier whose gain is the unity because of R5=R6. In opening the switch 26, the noninverting input of the amplifier 25 reaches the same voltage as the terminal voltage of the resistor R3, and the amplifier acts like a non-inverting amplifier whose gain is the unity. Thus, the circuit consisting of the operational amplifier 25, the analog switch 26, the capacitor C2 and the resistors R3-R6 acts like an operation circuit, and an output whose DC component is 0V at the synchronizing state is obtained at the output. Thus, it is not required for voltage shift by the DC amplifier 22 and a stable phase difference detection output is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention applies to MSK (Mini-m
This relates to a carrier regeneration circuit in a demodulation circuit of a signal synchronous detection method using 5-hift keying (5-hift keying), and is not limited to the MSK method, but is a modified method of MSK with various band restrictions that are considered as a group of MSK. S K (Gaussian Filte)
(red MSK) or similar phase-changing offset Q
It can also be applied to demodulation circuits such as PSK (OQPSK).

(Prior Art) Synchronous detection circuits for MSK signals are described in various documents. FIG. 1 is well known for its basic configuration side view. In Figure 1, 1 and 3 are phase detectors, 2 and 4 are low-frequency p
A wave filter (LPF) removes unnecessary wave components such as carrier wave components and noise outside the signal band. 5 is a 90° phase shifter, and 6 is a voltage controlled oscillator (VCO), which generates a carrier frequency synchronized with human power 14 for synchronous detection. 7 is a loop filter (FL
) determines the phase locking loop bandwidth. 8 and 9 are multipliers (MLT), 10 and 11 are judgment circuits (DEC), 1
2 is an exclusive OR circuit (EX-OR), 13 is a timing synchronization circuit (CLK), and 15 is a demodulation output. The operation of these circuits is well known and will be briefly explained next. 1
~4 phase detectors (DET) and LPF are used for demodulating the input signal, and at the same time phase shift circuits 5~9,
VCO, FL, 2) (7) Along with MLT, phase locked circuit (
PLL). Further, the EX-OR gates 10 and 11 of the determination circuit 12 operate to determine information from the output of the LPF and obtain a demodulated output 15.

The present invention relates to a multiplier circuit (MLT) of a phase-locked circuit as described above.
) 8, the operation of the MLT 8 will be further explained.

In Fig. 1, the output of MLT9 is the product of the input signal component in phase with the output of VCO6, that is, the output of LPF2, and the output of LPF4, which is the orthogonal input signal component. It is given by Eq. [For example, see reference document (1), page 5 below.] Here, A is the amplitude of the input signal 14, g is the modulation binary information (+1), and T is the information bit length, θ. is the phase difference between the input and recovered carrier waves.

The input of MLT8 is the above VD(t) and the other CL
Input v, (t) from K13, v, (t) is 10°1
It is expressed by the following equation using a clock for determining 1 and a clock whose phase is shifted by 90'.

'/r(t)=cos(πt/T) The multiplier circuit MLT8 performs these multiplications, and its output is as shown in the following equation.

v 1I(t) = v p(t) v r(t) Here, assuming that the probability that g is +1 and -1 is equal, if only this low-frequency component is extracted using a loop filter, the following equation can be obtained. .

1, a voltage V corresponding to the phase error θ8 is obtained,
V8 can control the VCO 6 and synchronize carrier waves.

Since the multiplication circuits 9 and 8 perform multiplication of baseband signals with DC components, it is difficult to create a stable circuit using a normal analog circuit. Therefore LPF2 and LPF
4 output with OV as threshold (threshold)
A method is generally used in which the multiplier circuit is implemented as a digital circuit by converting it into a value signal or by converting it into a binary value at the inputs of the phase detectors DETI and DET3.

For binary signals, an EX-OR circuit can be used as a multiplier circuit. From the multiplier circuit 8 using this method, the VC
FIG. 2 shows the circuit up to O6 in detail.

In FIG. 2, 16 and 17 are binarized signals of in-phase and quadrature components, respectively, which are input to the multiplication circuit 9 of FIG. 1, 18 is an EX-OR circuit that functions as the multiplication circuit 9, is an EX-OR circuit 20 that functions as a multiplier circuit 8.
is the clock input, resistors R1 and R2 and capacitor C1
21 is a loop filter corresponding to FL7, 22 is a DC amplifier that serves as a voltage shift and DC voltage amplification to compensate for the DC component of the output from 19, and 23 is a VC
It is the same VCO as O6.

FIG. 3 is a time chart of waveforms of various parts in FIG. 2. a
is the phase of the input signal (i.e. the phase difference with the output of the VCO)
is shown at the top with binary modulation data (same as 15 in Figure 1), b is input 16, C is input 17,
d is the output of the EX-OR circuit 18, e is the output of the EX-OR circuit 18,
f indicates the output of the EX-OR circuit 19, respectively.

In these waveforms, the solid line indicates a state in which the output of the VCO matches the phase of the input confirmed transmission wave, and the broken line indicates a state in which the phase is shifted.

As can be seen from the circuit of FIG. 1 and the above explanation, b is
When the phase difference between the input and VCO 6 is O to πrad, it goes to H level, otherwise it goes to L level, and C shows that the phase difference is -
H level when π/2 to π/2, L at other times
become the level. The clock 20 is synchronized by the timing synchronization circuit 13 of FIG. 1 so as to have the timing shown in FIG. 3e. The fact that d and f become as shown in Figure 3 is E.
This is clear from the theory of the X-OR circuit. As shown in r, in the synchronized state, the low frequency component (average voltage) of the output waveform of 19 is the average value of the H level voltage and L level voltage, but there is a phase error. The low frequency component is biased toward the H level or L level due to the phase difference between the two. Therefore, it is passed through a loop filter and converted into VC by a DC amplifier.
If the voltage is shifted to match the center voltage of the frequency control of O23 and inputted to the VCO23, interphase Q will be performed. However, the circuit shown in Fig. 2 has the advantage of being simple because the multiplier circuit can be realized by a digital circuit, but on the other hand, the input voltage (low frequency component) to the loop filter 21 in the synchronous state is equal to the H level of the digital circuit. It has the disadvantage that it is the average value of the L level and is not 0■. Next, this drawback will be explained in more detail.

As mentioned above, the phase difference detection circuit (18 and 19 in Figure 2 are 2
A phase difference detection circuit for human power 16 and 17 is configured. ) If the average voltage in the synchronous state of the output is the average value of the H level and L level, the following problems will occur.

(1) The H level of a digital circuit (for example, a TTL circuit) changes depending on the power supply voltage. Therefore, the operation of the circuit is easily affected by fluctuations in power supply voltage and noise in the power supply circuit (
, the synchronization becomes unstable and the jitter of the reproduced carrier wave increases.

(2) If you want to increase the loop gain of the phase locked circuit,
As shown in Figure 2, it is necessary to DC amplify the phase difference detection output, but in this case it is necessary to perform a voltage shift to correct the deviation of the average voltage from Ov, and this also requires synchronous operation as in (1). This causes instability. Therefore, it is difficult to increase the loop gain.

(Specific Object of the Invention) The present invention solves the above-mentioned drawbacks of the conventional circuit.
The present invention provides a phase difference detection circuit in which the output voltage (average voltage) of the phase difference detection circuit in a synchronous state changes around OV.

(Structure and operation of the invention) FIG. 4 shows an improved circuit of FIG. 2 including a phase difference detection circuit according to the invention. In Figure 4, 21.22°23 is the second
Same loop filter and DC amplifier as shown in the figure.

The other components constitute a phase difference detection circuit.

16, 17, 18, and 20 also have the same in-phase component input as in Figure 2,
It represents orthogonal component input, EX-OR circuit, and cross input, respectively. 24 is a clock buffer gate, 25
26 is an operational amplifier, and 26 is an analog switch, which short-circuits or opens the positive phase input terminal of the operational amplifier 25 to the ground by input from the EX-OR circuit 18.

Let resistance R4=R5=R6.

Next, the operation of the circuit shown in FIG. 4 will be explained. After passing through a buffer gate 24, the clock 20 is supplied to a resistor R3 via a capacitor C2. Since the clock 20 is a repeating rectangular wave with a duty of 50% as shown in Fig. 3e, the DC component is blocked by the capacitor C2, and the waveform applied to the resistor R3 has an average voltage O and positive and negative voltage values. It becomes an equal square wave. Next, when the switch 26 is closed and short-circuited to ground, the operational amplifier 25 has a positive phase input of ○■, so R
Since 5=R6, it operates as an inverting amplifier with a gain of 1. Conversely, if switch 26 is disconnected from ground,
The operational amplifier 25 operates as a common-mode amplifier with a gain of 1 because the positive-phase input voltage becomes the same voltage as the terminal voltage of R3.

From the above, the operational amplifier 25. The circuit composed of the analog switch 26 and C2, Il to R6 operates as a multiplier circuit, and its output has a waveform similar to that shown in Fig. 3f, and moreover, the DC component in the synchronous state is OV. . Therefore, in this case, there is no need to perform a voltage shift in the DC amplifier 22, and a stable phase difference detection output can be obtained.

Even if there is a fluctuation in the power supply voltage, the terminal voltage of the resistor R3 becomes a waveform with an average voltage of 0, where the positive and negative voltages are equal due to the direct current cutoff by the capacitor C2, and the output of the EX-OR gate 18 is only used to open and close the analog switch 26. Therefore, the phase difference detection output is kept stable without fluctuation due to the power supply voltage.

(Effects of the Invention) By using the synchronous detection circuit according to the present invention in a demodulation circuit for MSK signals, etc., the following effects can be obtained, and a stable synchronous detection circuit with less jitter can be realized.

b) Since the output voltage in the synchronized state of the circuit is OV, the degree of freedom in designing each element that makes up the circuit, especially the CO and DC amplifier increases.

U) The output voltage of the circuit in the synchronous state is OV and is not affected by fluctuations in the power supply voltage or level fluctuations in the output voltages of the circuits and elements.

(References) (1) Murota, Hiraide: “GMSK for digital mobile communications
"Modulation Method" Research and Practical Application Report Vol. 32 No. 6 (1983) Nippon Telegraph and Telephone Public Corporation.

[Brief explanation of drawings]

Figure 1 shows the basic configuration of a synchronous detection circuit, how many times does it appear, Figure 2 shows the specific circuit configuration of a part of Figure 1, how many times does the waveform of each part in Figure 2, and Figure 4 The figure shows the second case when the present invention is implemented.
What are the improved configurations of the circuit shown in the figure? 1.3...Phase detector, 2,4...LPF, 5...
・90° phase shifter, 6.23...voltage controlled oscillator (
VCO), 7... Loop filter, 8.9... Multiplier, to, tt... Judgment circuit (DEC),
12.18.19...Exclusive OR circuit (EX-OR
gate), 13... timing synchronization circuit (clock generation circuit), 14... input signal, 15... demodulation output,
16.17...18 inputs at each output of LPF2 and LPF4, 21...Loop filter, 22...DC amplifier, 24...Clock buffer gate.

Claims (1)

[Claims] two phase detectors each generating detection outputs of an input digital signal and an in-phase output and a quadrature-phase output of a voltage controlled oscillator; a first multiplication circuit that multiplies the two detection outputs; an output of the first multiplication circuit; It is composed of a second multiplier circuit that performs multiplication with a clock, a loop filter, and a DC amplifier, and the output of the second multiplier circuit is passed through the loop filter and the DC amplifier to provide it as a frequency control voltage for the voltage controlled oscillator. In the synchronous detection circuit for MSK signals, the second multiplier circuit has an analog switch that is opened and closed by the output signal of the first multiplier circuit, and one input of the clock whose DC component is blocked by a capacitor, and the analog A synchronous detection circuit for MSK system signals, characterized in that it is constituted by an operational amplifier that switches to an in-phase amplifier and an inverting amplifier depending on whether a switch is opened or closed.