JPH0628495A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To provide a means for developing various single chip microcomputers in a short period. CONSTITUTION:In a single chip microcomputer 100 which contains plural pieces of function blocks, and forms a signal for selecting the function block to be operated, by a function block selecting means 9, this computer is provided with a means 101 for inhibiting a read-out operation or a write operation to areas of all or a part in a PROM 2, and this inhibiting means 101 determines validity of a PROM selecting signal generated by the function block selecting means 9 in accordance with a conducting or non-conducting state of a control terminal 102 and a power source Vss supply lead terminal 110.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and, more particularly, to a technique effectively applied to a single chip microcomputer.

[0002]

2. Description of the Related Art A single-chip microcomputer, as described in "LSI Handbook" P540 and P541 issued by Ohmsha, Ltd. on November 30, 1984, has a central processing unit as a center for program holding RO.
Functional blocks such as an M (read only memory), a RAM (random access memory) for holding data, and an input / output circuit for inputting / outputting data are formed on one semiconductor substrate. When the system configuration is performed using such a single-chip microcomputer, it is possible to reduce the mounting area and improve the reliability as compared with the case of using a general-purpose multi-chip microprocessor or the like.

[0003]

However, the single-chip microcomputer usually has different optimum built-in functions or built-in peripheral circuit configurations depending on the system in which it is installed. In particular, when the integration degree of so-called semiconductor integrated circuits is improved, the number of functional blocks that can be formed on one semiconductor substrate is increased, and the number of combinations thereof is dramatically increased, a single-chip microcomputer optimal for one system is provided. Even so, there is a case where the system becomes insufficient or over-functioning with respect to other systems. Therefore, a wide variety of single-chip microcomputers must be developed in a short period of time. Within the development period,
With regard to logic design and layout design, the development period has been shortened by applying automatic design, but the prototyping period and evaluation period have been shortened due to the complexity of the semiconductor integrated circuit manufacturing technology and improvement of the functions of the single-chip microcomputer. Has become difficult.

On the other hand, it is possible to incorporate a large-scale memory and abundant functional blocks into one single-chip microcomputer so that it can be applied to a plurality of systems. However, such a single-chip microcomputer is wasteful for any system and the manufacturing cost is high. If a large-capacity memory is built in, there is a problem that the capacity of the external memory that can be used during the external expansion operation becomes small.

It is an object of the present invention to provide a means for developing a wide variety of single chip microcomputers in a short period of time.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0007]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, the operation of reading or writing the whole or a part of the built-in memory, or the built-in functional block via the internal bus, is connected to the electrode terminal of the semiconductor integrated circuit device by a predetermined external connection for power supply. A semiconductor integrated circuit such as a single-chip microcomputer is configured so as to be fixedly prohibited according to the conduction or non-conduction state with the electrodes.

[0009]

According to the above-mentioned means, when the single-chip microcomputer according to the present invention having the built-in function and having other functions is used for the single-chip microcomputer to be developed, either one of the predetermined ones is used. By prohibiting the data read or write operation of all or part of the built-in memory or other built-in function block according to the conduction or non-conduction state with the power supply lead or the conductive pattern of, the operation is prohibited. It is possible to provide the single-chip microcomputer to be developed in a short period of time, which does not have a closed portion.

[0010]

1 is a block diagram of a single chip computer according to an embodiment of the present invention.

The single-chip computer 100 shown in FIG. 1 is a PROM having a storage capacity of CPU (central processing unit) 1,32 kbytes, although not particularly limited thereto.
(Programmable ROM) 2, RAM having a storage capacity of 1 kbyte 3, timer 4, SCI (serial communication interface) 5, A / D converter 6, and first to ninth input / output ports 71 to 79, functional block selection circuit (MS) 9, these blocks are connected to each other by an internal bus, and are formed on one semiconductor substrate by a known semiconductor manufacturing technique. The internal bus is not particularly limited, but is generated based on a 16-bit address bus 81, an 8-bit data bus 82, a read signal, a write signal, and an oscillation frequency of a crystal oscillator (not shown) or is externally supplied. And a system clock signal line generated from the generated clock signal.

In this embodiment, not all address signals (16 lines) are input to each functional block, but a functional block selection signal indicating that the functional block has been selected and the functional block. A lower address indicating which of the addresses has been selected is input. For example, one functional block selection signal and 14 lower addresses are input to the PROM 2.
The functional block selection circuit 9 decodes a predetermined plurality of bits of the address signal output from the CPU 1 and supplies the functional block selection signal to each functional block.

FIG. 2 shows an address map of the single chip microcomputer 100.

The built-in memory of the single-chip microcomputer 100 in this embodiment is the PROM 2 and R.
It is AM3. Although not particularly limited, PROM2
Is for storing programs and fixed data.
It can be written using a ROM writer.
In this embodiment, the PROM 2 is divided into two areas PROM 21 and PROM 22. The RAM 3 is used as a temporary data storage or work area. RAM
3 is divided into two areas, a RAM 31 and a RAM 32. Although not particularly limited, the timer 4 is composed of two independent timers 41 and 42 each having a timer counter and a comparison register. Although not particularly limited, the shaded area in FIG. 2 is an address area that can be assigned to the external memory during the external expansion operation.

In FIG. 1, in the peripheral portion of the chip,
A large number of terminals (bonding pads) are arranged as electrode terminals, and the bonding pads P10 to P17 are connected to the input / output terminals of the first to ninth input / output ports 71 to 79.
P20-P23, P30-P37, P40-P47, P
50-P57, P60-P63, P70-P77, P8
0-P87, P90-P97, bonding pad XT to which a crystal oscillator is connected or an external clock is supplied
AL, EXTAL, power supply terminals Vdd, Vss, etc. are arranged. Although not particularly limited, a relatively high level power source is connected to the Vdd terminal and a relatively low level power source is connected to the Vss terminal.

The single-chip microcomputer 100 thus made into one chip is attached (die-bonded) to the mount of the package in the assembly process, and the lead terminal of the package and the bonding pad are formed by gold wires, although not particularly limited. After being connected (wire bonding), it is sealed.

In the embodiment shown in FIG. 1, PRO
Data reading can be selectively prohibited for half of M2. A control circuit 101 connected to the control pad 102 is provided. When the input level of the control pad 102 is fixed to a relatively low level power supply (Vss) voltage level, at least the control circuit 101 PRO.
The control signal φinh for fixedly prohibiting the reading of half the data of M is activated to the high level, and the selection signal of the PROM 2 is generated based on this and the decoding result signal from the functional block selection circuit 9.

FIG. 3 shows an example of such a control circuit 101. This control circuit 101 is a P-channel type MOSF.
A CMOS inverter including an ETQ 10 and an N-channel MOSFET Q11 is included. The input of the CMOS inverter is supplied with a high level power source Vdd through a high resistance 103, and a signal wiring 104 and an input protection circuit 10 are provided.
It is connected to the control pad 102 via 6. Control signal φinh output from CMOS inverter
Is inverted and connected to one input of the AND gate 1051 although not particularly limited thereto. The other input of the AND gate 1051 is the functional block selection circuit 9
Is the PROM22 selection signal φSEL22 generated by
The output of the AND gate 1051 is connected to one input of the OR gate 1052. The other input of the OR gate 1052 is the PROM generated by the functional block selection circuit 9.
21 selection signal φSEL21, and OR gate 1052
Is PR as the selection signal φCS2 for the entire PROM2
Given to OM2. This selection signal φCS2 is PROM
The selection signal φC supplied to the read control circuit included in 2
When S2 is at the selection level, that is, at the high level, the read signal or the like activates the inside of the PROM 2 at a predetermined timing to enable the data read operation. If the selection signal φCS2 is at the non-selection level, that is, the low level, the operation of the PROM2 is prohibited at all.

In this embodiment, when the control pad 102 is brought into a non-connected state (floating), the control signal φ
inh is set to low level, and PROM22 selection signal φS
When the PROM 22 is selected by the EL 22, the selection signal φCS2 is activated (high level) to permit the operation of the PROM 2. On the other hand, as shown in FIG. 1, the control pad 1
02 to the lead for supplying the low level power supply Vss with wire 1
Bonding via 11 causes the control signal φin
Since h is set to the high level, the output of the AND gate 1051 is fixed to the low level, and the PROM 22 selection signal φS
Even if the PROM 22 is selected by the EL 22, the selection signal φCS2 is set to the low level. Therefore, the PROM
Even if the CPU 1 reads or writes the address corresponding to 22, the contents of the PROM 22 will not be read to the internal bus or written to the PROM 22 from the internal bus. In other words, in this state, the PROM 22 shown in the memory map of FIG. 2 is substantially the same as not existing. Therefore, the chip in which the control pad 102 is bonded to the lead 110 for supplying the low-level power Vss is not subjected to a special process such that the mold resin or the package is intentionally disassembled and modified.
In a normal use state, it can be used as a single-chip microcomputer equipped with a 16 Kbyte PROM. In addition, using a PROM writing device, PR
When writing to the OM2, the operation is similar to the above.

FIG. 4 shows another example of the control circuit 101. In addition to the AND gate 1051a and OR gate 1052a similar to those shown in FIG. 3, the control circuit 101 shown in the figure has a selection signal φSEL22 and an inhibition signal φ.
An AND gate 1051d for receiving inh and an OR gate 1052d for receiving the output of the AND gate 1051d and the selection signal φSEL21 are provided. OR gate 1052
The output of d is the selection signal φCSE for the external memory.
In this configuration, the control pad 102 is bonded to the lead 110 for supplying the low-level power supply Vss, and the control signal φinh is set to the high level.
When 2 is selected, the selection signal φCS2 is set to low level. At this time, the external memory selection signal φCSE is set to high level so that the external memory can be read / written.

According to the embodiment of FIG. 1, it is possible to immediately develop a single-chip microcomputer in which the usable memory capacity is changed. In this case, since the actual chip is the same in both PROM 32 kbytes and PROM 16 kbytes, the trial production and evaluation can be standardized, the work amount and period required for these can be reduced, and the development cost can be reduced. . Developed in this way, for example, PR
Since the OM 16 kbyte single-chip microcomputer actually has a built-in PROM 32 kbyte block, it has a larger chip area than the case where a single-chip microcomputer actually built with a PROM 16 kbyte block was developed. Although the cost is high, there is an effect that it can be developed in a short period of time and the development cost can be reduced. These can obtain a great effect especially when performing small-quantity multi-product production. On the other hand, in the case of mass production, the increase in the manufacturing cost exceeds the reduction in the development cost. Actually PR
Even if it is necessary to develop a single-chip microcomputer having a built-in OM 16-kbyte block, the development method according to the present embodiment develops and provides a PROM 16-kbyte single-chip microcomputer in a short period of time.
At the same time, a single-chip microcomputer in which a PROM 16 kbyte block is built is actually developed, and switching is performed at the time of completion of development to reduce the manufacturing cost. In this case, since there is no difference in function between the two types of single-chip microcomputers, there is no problem such as system design change due to switching.

FIG. 5 shows still another example of the control circuit 101. In this example, the control signal φinh generated by the control circuit 101 controls the change of the capacity of the RAM 3 in addition to the capacity of the PROM 2 and the operation permission or prohibition of some functions of the timer 4. Control signal φinh
Is inverted and AND gate 1051a, as described above.
It is connected to one input of 1051b and 1051c. The other inputs of the AND gates 1051a, 1051b and 1051c are supplied with the PROM22 selection signal φSEL22, the RAM32 selection signal φSEL32 and the timer 42 selection signal φSEL42 generated by the functional block selection circuit 9, and the outputs of the AND gates 1051a and 1051b are supplied. , OR gates 1052a, 1052b are connected to one input. The other input of the OR gates 1052a and 1052b has the PR generated by the functional block selection circuit.
OM21 selection signal φSEL21, RAM31 selection signal φ
SEL31 is supplied to OR gates 1052a, 105
2b and AND gate 1051c outputs PROM2 selection signal φCS2, RAM3 selection signal φCS3, and timer 4
PROM2, R respectively as 2 selection signal φCS42
It is given to AM3 and timer 4.

In the circuit configuration shown in FIG. 5, when control pad 102 is disconnected, control signal φin
h is set to low level, and PROM22 selection signal φSEL
22, RAM32 selection signal φSEL32, timer 42 selection signal φSEL42, PROM22, RAM3
2. When the timer 42 is selected, its operation is permitted. On the other hand, when the control pad 102 is bonded to the lead for supplying the low-level power supply Vss via the wire 111 as shown in FIG. 1, the control signal φinh is set to the high level, and the AND gates 105a, 1051b,
The output of 1051c is fixed to low level, and PROM2
2 selection signal φSEL22, RAM31 selection signal φSEL
31 and timer 42 selection signal φSEL41 makes PRO
Even when the M22, the RAM 32, and the timer 42 are selected, the selection signal φCS2, the selection signal φCS3, and the selection signal φCS42 maintain the low level deactivation level. Therefore, the control pad 102 is the lead 1 for supplying the low-level power supply Vss.
The chip bonded to 10 is essentially a PROM
16-kbyte, 512-byte RAM, 1-channel timer can be used as a single-chip microcomputer.

By providing a plurality of control pads 102, two or more combinations can be realized depending on the combination of the states of these control terminals.

FIG. 6 shows still another example of the control circuit 101. The control signal φinh generated by the control circuit 101 shown in the figure is not particularly limited, but functions to select which of the timer 411 and the timer 412 existing at the same address is used. In this example, when the control pad 102 is disconnected, the control signal φinh is set to low level and the timer 41
The timer 411 is selected by the selection signal φSEL41, and the selection signal of the timer 412 is fixed to the low level. Therefore, only the timer 411 can be used. On the other hand, when the control pad 102 is bonded to the lead for supplying the low-level power supply Vss via the wire 111 as shown in FIG. 1, the control signal φinh is set to the high level, and therefore the timer 41 selection signal φSEL 41 causes the timer 412 to operate. Is selected and the selection signal of the timer 411 is fixed at a low level. Therefore, only the timer 411 can be used.

According to this embodiment, it is possible to immediately develop a single-chip microcomputer in which usable functional blocks are changed. That is, a function block that cannot be built in one single-chip microcomputer due to the number of terminals or restrictions on the memory map is built-in in advance, and the function block can be selected as needed to develop a single-chip microcomputer. . Also, the address of the functional block can be changed. For example, if the address of the timer 41 is H'FFC8-
When changing from H'FFCF to H'F000 to H'F007, the selection signals of H'FFC8 to H'FFCF and H '
Any of the selection signals of F000 to H'F007 causes timer 4
Whether the 1 selection signal φCS41 is generated may be switched by the control signal φinh.

FIG. 7 shows an essential part of a single chip computer according to the second embodiment of the present invention. In the first embodiment, the function selection of the single-chip microcomputer is performed by the presence / absence of bonding of the control pad 102, but in the present embodiment, such selection is performed by the program for the fuse circuit. That is, the input of the control circuit 101 is connected to the low level internal power supply Vss wiring not through the control pad 102 but through the fuse 130 that can be blown by the laser, and the PROM 3
When the size is set to 2 kbytes, if the fuse 130 is blown by a laser in the wafer manufacturing process, it becomes the same as the case where the control pad 102 is unconnected in FIG. on the other hand,
If the PROM is 16 kbytes, the fuse 130
If it is left as it is, it becomes the same as the case where the control pad 102 is in the connected state in FIG. Further, although not shown, the portion corresponding to the fuse can be processed by etching using a photomask or electrically blown. Further, the initial state may be a non-conducting state, and the conducting state may be selectively performed later. According to the present embodiment, it is easier to provide a large number of fuses than to provide a large number of dedicated control terminals, and this is highly effective in realizing various single-chip microcomputers.

FIG. 8 shows the essential parts of a single-chip computer according to the third embodiment of the present invention. In this embodiment, the selection of the single chip microcomputer is PR.
This is performed by a program for the same nonvolatile memory element as OM2. FIG. 8 shows a configuration example of a main part corresponding to FIG. In this case, the input 104 of the control circuit 101
Through the PROM element Q12 to the low level internal power supply V
When the PROM is 32 kbytes connected to ss and the PROM element is in the write state, that is, in the off state, the control pad 102 is the same as the non-connected state in FIG. On the other hand, when the PROM is 16 kbytes, the erased state in which the PROM element Q12 is not written, that is, the ON state is similar to the case where the control pad 102 is connected in FIG. Such PR
The method of writing the OM element has no direct relation to the present invention, and thus a detailed description thereof will be omitted. If the PROM element and the writing circuit of the PROM 2 as the built-in memory are shared, the physical scale can be reduced.

Here, considering the probability of occurrence of defects in the single chip microcomputer in the process of manufacturing the semiconductor integrated circuit, the probability is proportional to the physical area, that is, in each block of the single chip microcomputer, It is known that a block having the largest physical area is most likely to have defects. One of such blocks having a large physical area is the PROM2. This is because the address decoder / input / output circuit of the PROM 2 has a high withstand voltage circuit in addition to the large number of storage elements and the property of writing using a high voltage. At this time, P
Even if the chip is manufactured as a single-chip microcomputer with a ROM of 32 kbytes but has a defect in the portion of the PROM 22, the PRO according to the present embodiment is used.
By prohibiting the operation of M22, the PROM can be used as a 16-kbyte single-chip microcomputer. Therefore, according to the present invention, even if a part of a built-in functional block such as a PROM has a defect, the chip is not discarded and it can be used as a single-chip microcomputer that does not use the defective part.

FIG. 9 shows the essential parts of a single-chip computer which is a modification of the second embodiment shown in FIG. 7 using a fuse. In the embodiment of FIG. 7, the PROM 22
Even if the chip has a defect in
Can be used as a single-chip microcomputer of 16 kbytes of PROM. However, in the present embodiment, even if a chip having a defect in either PROM21 or PROM22, PROM16k
The byte can be used as a single-chip microcomputer. Therefore, the addresses A0 to A13 are directly input to the PROM 2, and the address A14 is input via the fuse 131. At this time, the address A14
Is input to the high level power source Vdd through the high resistance 103a.
Combined with.

If the PROM 2 has no defect, the fuse 130 is blown by a laser. If there is a defect in the PROM 22 portion, the fuse 130 may be set in a state in which it is not blown out as described above. If the PROM 21 is defective, the fuse 130 is not blown by the laser, and the selection signal φCS2 of the PROM 2 is set to the high level when the address corresponding to the PROM 21 is selected. Further, the fuse 131 is melted and the PROM
When the PROM2 is selected, the address A14 input to 2 is fixed to the high level, and P
The ROM 22 is used. That is, PRO
The part of M22 is the address H'0 corresponding to PROM21.
000 to H'3FFF 16K bytes PROM can be used.

By prohibiting the data read or write operation of the built-in functional block in each of the above embodiments, the number of terminals is changed in the case of the single-chip microcomputer to be developed which does not have that portion. Can be considered. Further, it is conceivable that the terminals (bonding pads) used will be changed. That is, in FIG. 1, the bonding pads P10 to P connected to the input / output terminals of the first to ninth input / output ports 71 to 79.
17, P20 to P23, P30 to P37, P40 to P4
7, P50 to P57, P60 to P63, P70 to P7
7, P80 to P87, P90 to P97 are included, but it is conceivable to prohibit the operation of the eighth to ninth input / output ports 78 to 79. In this case, the bonding pads P80 to P87 and P90 to P97 connected to the input / output terminals of the eighth to ninth input / output ports 78 to 79 are present, and the bonding with the lead terminals is not performed.

In such a case, for example, the distances from the lead terminals evenly arranged in the package to the bonding pads are the bonding pads P80 to P87 and P9.
0 to P97 become larger than those in the absence of P97, and the length of the wire connecting them also becomes long. A long wire may move due to the flow of the sealant and come into contact with an adjacent wire or chip when sealing is performed after bonding. When the wire is made of a metal wire such as a gold wire as described above, a signal short-circuits due to the contact between the wires, and the single-chip microcomputer does not operate normally. This measure will be described below with reference to FIG.

FIG. 10 shows an embodiment of a semiconductor integrated circuit device in which the number of terminals can be easily changed. FIG. 1A shows an overall cross section of the semiconductor integrated circuit device in a sealed state. Reference numeral 200 is a chip, 201 is a covered wire, 202 is a lead terminal, 203 is a sealant such as resin, and 204 is a chip mount. FIG. 1B shows an enlarged cross-sectional view of the vicinity of the bonding wire, 205 is a bonding pad, 201A is a metal wire forming the covered wire 201,
201B is an insulating coating that covers the metal wire 201A.
The semiconductor integrated circuit device shown in FIG. 10, for example, a single-chip computer has the lead terminal 202 and the bonding pad 205 of the single-chip computer.
Are connected by a covered wire 201 in which the surface of the metal wire 201A is covered with an insulating coating 201B, and then the sealant 2
It is molded with 03. A method of connecting the covered wire 201 is known, for example, from Japanese Patent Application Laid-Open No. 63-182828, so its detailed description will be omitted. As shown in FIG. 10, if the covered wire 201 is used for wire bonding, the single chip microcomputer can operate normally even if the wires contact each other or the wire and the chip, and the number of terminals of the single chip microcomputer is changed. It is possible to prevent inconveniences that may occur when doing so.

According to the above embodiment, the following effects are obtained. That is, in a semiconductor integrated circuit device including a plurality of functional blocks, an operation of reading or writing all or part of an internal memory or a functional block through an internal bus is performed by a predetermined operation coupled to an electrode terminal of the semiconductor integrated circuit device. By configuring the semiconductor integrated circuit device so as to be fixedly prohibited according to the conduction state or the non-conduction state with one of the power supply external connection electrodes, a semiconductor that does not have such a prohibited portion. It can be provided in a short period of time as an integrated circuit device.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and needless to say, various modifications can be made without departing from the scope of the invention. Yes. For example,
In order to prohibit the operation of the functional block, in addition to prohibiting the functional block selection signal, the prohibition signal may be directly input to the functional block to put the functional block in the reset state and the clock may be stopped. Further, in the above embodiment,
The case where the lead terminal of the package and the bonding pad are connected by wire bonding has been described, but the flip-chip method in which the bonding pad has a connection electrode structure such as a solder bump, and the chip is mounted face down on the conductive pattern of the wiring board, Alternatively, in the wafer manufacturing process, a beam-shaped lead is formed on the connection electrode part of the chip, and this is connected face-down to the conductive pattern of the wiring board. A TAB (Tape Automated Bond), which is formed by face-up bonding to a conductive lead of a lead frame formed on a tape such as resin and then separating the lead from the tape.
ing) method can also be adopted. Further, the number and types of function blocks incorporated, the method of selecting the function blocks, the package, and the like are not limited at all. Further, the specific configurations of the control circuit 101 and the control pad 102 are not limited to those in the above embodiment, and various modifications can be made. For example, the control circuit 101 can be included in the functional block selection circuit 9. It is also possible to combine the embodiments with each other. The PROM element shown in FIG. 9 may be provided inside the PROM 2.

In the above description, the case where the invention made by the present inventor is mainly applied to the single-chip microcomputer which is the field of application which is the background of the invention has been described, but the present invention is not limited thereto and other semiconductor integrated circuits are used. The present invention can be applied to a circuit device, and the present invention can be applied to a semiconductor integrated circuit device having at least a plurality of functional blocks.

[0038]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, in a semiconductor integrated circuit device having a plurality of functional blocks built-in, the operation of reading or writing all or part of the built-in memory or the functional blocks via an internal bus is coupled to the electrode terminals of the semiconductor integrated circuit device. By configuring the semiconductor integrated circuit device so as to be fixedly prohibited according to the conduction state or the non-conduction state with one of the predetermined power supply external connection electrodes, it is as if the operation is prohibited. There is an effect that it can be provided in a short period of time as a semiconductor integrated circuit device that does not have a closed portion.

[Brief description of drawings]

FIG. 1 is a block diagram of a single-chip microcomputer according to a first embodiment of the present invention.

FIG. 2 is an example address map of the single-chip microcomputer shown in FIG.

3 is a block diagram of an example of a control circuit applied to the single-chip microcomputer in FIG.

4 is a block diagram of another example of a control circuit applied to the single-chip microcomputer in FIG.

5 is a block diagram of another example of a control circuit applied to the single-chip microcomputer in FIG.

6 is a block diagram of yet another example of a control circuit applied to the single-chip microcomputer in FIG. 1. FIG.

FIG. 7 is a block diagram showing a main part of a single-chip microcomputer according to a second embodiment of the present invention.

FIG. 8 is a block diagram showing a main part of a single-chip microcomputer according to a third embodiment of the present invention.

FIG. 9 is a block diagram showing a modification of the second embodiment of the present invention.

FIG. 10 is a configuration explanatory view for preventing a situation where the bonding wires come into contact with each other and short-circuit when the number of terminals of the semiconductor integrated circuit is changed.

[Explanation of symbols]

 1 CPU 2 PROM 3 RAM 4 timer 5 SCI 6 A / D converter 9 functional block selection circuit 101 control circuit 102 control pad 110 lead terminal 111 wire φinh inhibit signal 130 fuse 131 fuse 201 coated wire 201B insulating coating

Claims (8)

[Claims] 1. A semiconductor integrated circuit including a plurality of functional blocks, wherein a signal for selecting a functional block to be operated is formed by a functional block selecting means, at least one of the functional blocks or all or at least one of the functional blocks. A part of the read operation or the write operation is prohibited, and this prohibiting means is a signal generated by the functional block selecting means based on a state selected from a first state and a second state. A semiconductor integrated circuit, which determines the effectiveness of the semiconductor integrated circuit. 2. The semiconductor integrated circuit according to claim 1, wherein the functional block in which the read operation or the write operation is prohibited is a programmable ROM. 3. The prohibiting means determines the first state and the second state depending on whether or not the input of the electrode terminal is fixed to one of the predetermined power supply voltage levels. Item 3. The semiconductor integrated circuit according to item 1 or 2. 4. The semiconductor integrated circuit according to claim 1, wherein the prohibition means determines the first state and the second state by conduction or non-conduction of the program link. 5. The prohibiting means includes a first state and a second state according to an erased state or a written state of the nonvolatile memory element.
The semiconductor integrated circuit according to claim 1 or 2, wherein the state is determined. 6. A semiconductor integrated circuit including a plurality of functional blocks, wherein a signal for selecting a functional block to be operated is formed by the functional block selecting means, wherein a plurality of functional blocks among the functional blocks are provided. Of all or part of the read operation or write operation is provided, and the prohibiting means is generated by the functional block selecting means based on a state selected from a first state and a second state. A semiconductor integrated circuit, which determines the validity of a signal to be applied. 7. A data processing device is included as one functional block, and the prohibiting means excludes prohibition of operation of the data processing device.
7. The semiconductor integrated circuit according to claim 6. 8. The semiconductor device according to claim 1, wherein the prohibition unit makes an external memory readable or writable in place of the functional block in which the read operation or the write operation is prohibited. Integrated circuit.