JPH0628310A - Processor system - Google Patents

Abstract

PURPOSE:To minimize the overhead applied to the transfer of data carried out between a processor and a computing element and also to perform the arithmetic operations with a small number of instructions by giving the data read out of a memory to the computing element with no intervention of a data bus. CONSTITUTION:A processor 31 outputs an address signal and an control signal and reads the data on a data bus into a internal register. The memory circuits 33 and 34 output the data designated by the address signal outputted from the processor 31 based on the control signal of the processor 31. An arithmetic circuit 35 inputs the output data on both circuits 33 and 34 via an exclusive line and computes the data to output this computing result. A buffer circuit 40 decides whether the computing result received from the circuit 35 should be outputted to the data bus or not based on the address and control signals of the processor 31. Thus, the data are simultaneously inputted to the circuit 35 from the circuits 33 and 34 via the exclusive line. Then, the overhead can be minimized for the transfer of data and therefore the instruction executing time is shortened.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to processor systems. In particular, the present invention relates to a processor having only an arithmetic unit having a limited function inside, and a processor system having an arithmetic unit having an expanded function and a memory connected to a bus.

[0002]

2. Description of the Related Art In order to improve the performance of a processor system, a dedicated arithmetic unit may be placed on the bus of the processor. For example, when the processor does not have a built-in multiplier, the multiplier may be placed on the bus of the processor to execute the multiplication at high speed. In a processor that does not have a built-in multiplier, multiplication is repeated by addition. Up to 16 additions are required for 16-bit multiplication.
If it takes 1 clock to add 1 bit, it takes 16 clocks to execute the multiplication. Depending on the application, such as for embedded control, the frequency of multiplication is high, and high-speed multiplication is required.

FIG. 9 shows an example of a system having a conventional external arithmetic circuit. The arithmetic unit is an example of a multiplier, and the processor 10, the bus controller 11, the multiplier 12, the source register 13, the source register 14, and the buffer 15
Made of. The processor 10 has a basic clock BC
LK operates in synchronization with the double frequency clock CLK. Hereinafter, when simply described as a clock, it represents one cycle of the basic clock BCLK. The input data to the multiplier 12 is the source register 13 and the source register 1
Given from 4. The multiplication result is passed through the buffer 15
It is output to the data bus.

In the conventional example, the source data of the multiplication is written in the source register 13 and the source register 14 in the write bus cycle of the processor, and the multiplication result is read in by the processor in the read bus cycle. Addresses are assigned to the source register 13, the source register 14, and the buffer 15, respectively, and the bus controller 11 controls the control signal SW1 when the addresses output on the address bus in the bus cycle of the processor match the respective addresses. SW2 and MOE are output. The source registers 13 and 14 internally latch the data on the data bus at the rising edges of the control signals SW1 and SW1, respectively, and supply the data to the multiplier. The buffer 15 has a control signal M
When OE is active (low level), the multiplication result output from the multiplier is output on the data bus.

FIG. 10 shows the timing of multiplication in the conventional example. In the write bus cycle of clock 1, the processor outputs the address of the source register 13 to the address bus, and outputs the data set in the source register 13 to the data bus. The bus controller 11 outputs a rising edge to the control signal SW1 at an appropriate timing. At the rising edge, the source register 13 internally latches the data on the data bus and outputs it to the multiplier. At clock 2, similarly, the other data of the multiplication is set in the source register 14. In the read bus cycle of clock 3, the processor outputs the address of the buffer 15 to the address bus. The bus controller 11 uses the control signal MOE
To activate. The buffer 15 outputs the output of the multiplier on the data bus, and the processor internally reads this value. Since there is one clock period from setting the data in the source register to reading the multiplication result by the processor, the multiplier 12 may end the multiplication during this period. As described above, in the conventional example, it took a minimum of 3 clocks to execute one multiplication. When the multiplication process is written in an actual program, the following three instructions are required, and more clocks are required for one multiplication. mov r1, @ src13_adr ... (1) mov r2, @ src14_adr ... (2) mov @mul_adr, r3 ... (3)

The mov instruction is an instruction for transferring data with the first operand as the source and the second operand as the destination. r1, r2, and r3 are internal registers of the processor. @ Src13_adr, @ src1
4_adr and @mul_adr indicate access to the addresses of the source register 13, the source register 14, and the buffer 15, respectively.

The instruction (1) writes the value of the internal register r1 of the processor to the source register 13. Instruction (2) sets the value of the internal register r2 to the source register 14
Write to. The instruction (3) reads the multiplication result into the internal register r3. The product of r1 and r2 is r
Stored in 3.

If the number of execution clocks of the instructions (1) and (2) for executing the write bus cycle is 2, and the instruction (3) including the read bus cycle is 4, it takes 8 clocks to execute these three instructions.

As described above, although the multiplication speed of the multiplier is as high as one clock, the instruction for setting the data and the instruction for reading the multiplication result are different, and the processing time is long, so once. It took as long as 8 clocks to multiply by.

[0010]

As described above, in the conventional processor system, the overhead of setting the data from the processor to the arithmetic unit and reading the arithmetic result from the arithmetic unit to the processor is large, and the processing speed is increased. There was a drawback that it could not be achieved.

The present invention eliminates the above-mentioned drawbacks and minimizes the overhead of data transfer between the processor and the arithmetic unit by giving the data read out from the memory to the arithmetic unit without passing through the data bus. The purpose of the present invention is to realize the operation with a small number of instructions, thereby improving the performance by reducing the instruction execution time and reducing the memory capacity by reducing the code size of the program.

[0012]

In order to achieve the above object, according to the present invention, a processor for outputting an address signal and a control signal to read data on a data bus into an internal register, and the address signal output by the processor. A memory circuit for outputting the data designated by the processor in accordance with the control signal of the processor; an arithmetic circuit for inputting the output data of the memory circuit through a dedicated line to perform an arithmetic operation and outputting the arithmetic result; A processor system comprising: a first buffer circuit for controlling whether or not the operation result is output from the operation circuit to the data bus according to an address signal and the control signal.

The memory circuit inputs two or more independent signal groups of the address signals of the processor and outputs two or more independent data designated by the signal groups. To provide a processor system.

Further, a second buffer circuit for controlling whether or not the output signal of the memory circuit and the data bus are connected by the address signal and the control signal of the processor is provided, and the first buffer circuit is provided. One of the buffer circuit and the second buffer circuit does not output when one is outputting data to the data bus, and the processor circuit outputs both the output of the arithmetic circuit and the output data of the memory. To provide a processor system that can be read by a.

A second buffer circuit for controlling whether or not the output signal of the memory circuit and the data bus are connected by the address signal of the processor and the control signal, and the address signal of the processor. A bus control circuit for outputting to the memory circuit two or more independent signal groups of the address signals of the processor when the processor determines to read the output from the arithmetic circuit by the control signal. , One of the first buffer circuit and the second buffer circuit does not output when one is outputting data to the data bus, and outputs the output of the arithmetic circuit and the data of the memory. A processor system is provided which is readable by the processor. Further, there is provided a processor system in which these arithmetic units are multipliers.

[0016]

By using the means provided by the present invention, the input data of the arithmetic unit can be simultaneously given from the memory circuit to the arithmetic unit via the dedicated line, so that the overhead of data transfer can be reduced as compared with the conventional case. As a result, the effective time of the instruction is shortened and the performance of the entire processor system can be improved.

Further, since it is not necessary to read the operand input to the arithmetic unit into the processor once, the effective time of the instruction can be shortened and the code size of the program can be reduced accordingly.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the first embodiment of the processor system of the present invention. The processor system includes a processor 31, a bus controller 32, an upper RAM 33, a lower RAM 34, a multiplier 35, a source register 36, a source register 37, buffers 38, 39 and 40, and a gate 4.
1 and 42.

The processor 31 has a basic clock BCL.
K operates in synchronization with the double frequency clock CLK. The signal of the processor is connected to the address bus, the data bus, and the control bus.

Address signals A00 to A29 are signals for outputting addresses to be accessed by the processor when executing a bus cycle. A00 to A29 are connected to the address bus.

The data signals D00 to D31 are used for reading and writing data and are connected to the data bus. In the read bus cycle, the processor
The data on D31 is read internally. In the write bus cycle, the processor outputs data to D00 to D31.

Byte control signals BC0 to BC3
Is a signal which is made active (0: Low level) by the processor corresponding to the byte position to be accessed when the bus cycle is executed. BC0, BC1, BC2, B
When C3 is active, the data signals D00 to D00
D07, D08 to D15, D16 to D23, D24 to D
31 indicates that it is accessed.

The read / write signal RW is a signal indicating whether the bus cycle is read or write. The processor is
The RW signal is set to 1 (High level) in the read bus cycle and 0 (Low level) in the write bus cycle. The address strobe signal AS is active in the bus cycle by the processor (0: Low level).
This is the signal to be turned on.

The data transfer end signal DC is a signal for controlling the end of the bus cycle. When the external circuit activates the DC signal (0: Low level), the processor ends the bus cycle with the clock.

Byte control signals BC0 to BC3,
Read / write signal RW, address strobe signal A
The S and data transfer end signal DC are connected to the control bus.

The bus controller 32 is an upper RAM 33.
And a circuit for controlling access to the lower RAM 33 and writing data to the source register 36 and the source register 37. The bus controller 32 inputs the address signals A00 to A29, the byte control signals BC0 to BC3, the read / write signal RW, and the AS signal output from the processor via the address bus and the control bus.
Address signals RADRH0 to RADR to the upper RAM 33
H7 and enable signals CE0 and CE1, address signals RADRL0 to RADRL7 and enable signals CE2 and CE3, and read / write signal RRW are commonly output to the lower RAM. In addition, SCL indicating the timing of the data latch of the source register 36 and the source register 37 of the multiplier
Output K signal.

The upper RAM 33 and the lower RAM 34 are memories for storing data and programs, and the upper RA
M33 is a data bus D00 to D1 via a buffer 38.
Connected to 5. The lower RAM is connected to the data buses D16 to D31 via the buffer 39. RAM
Each word of the address signal RADRH0-7, RAD
Selected by RL0-7. In this embodiment, since there are eight addresses, the size of each RAM is 512 bytes. Further, by the enable signals CE0 to CE3,
It can be accessed in byte units. When CE0 to CE3 become active (0: Low level), RA
Data is read from M and data is written to RAM. When the read / write signal RRW is 1 (High level), it is a read access and the RAM outputs data. When the read / write signal RRW is 0 (Low level), it is a write access and the RAM outputs data.

The multiplier 35 has 16-bit data IX0-IX.
IX15 and IY0 to IY15 are input, and 32-bit multiplication results IP0 to IP31 are output. IXM, IYM
Indicates whether IX0 to IX15 and IY0 to IY15 are signed integers (IXM, IYM = 1) or unsigned integers (IXM, IYM = 0), respectively. Signed integers are in 2's complement notation. Two input data IX0
When ˜IX15 and IY0 to IY15 are both unsigned integers (IXM = IYM = 0), the multiplication result is unsigned, and when either one is a signed integer, the multiplication result is also signed. IRND is the high-order 1 of the multiplier result
This signal specifies whether to round 6 bits. Only when IRND is 1, the lower 16 most significant bits (IP1
Add 1 to 5). An example of such a multiplier is the Toshiba standard cell TC25SC series hard macrocell MP16. FIG. 2 shows a circuit configuration diagram of this multiplier. Next, the operation of the processor system shown in FIG. 1 will be described. The operation of the processor system is R
It is divided into an AM access operation and a multiplication operation. (1) RAM access operation

In the RAM access operation, the upper RAM and the lower RAM are accessed as a normal 32-bit width RAM. The words of the same address in the upper RAM 33 and the lower RAM 34 are accessed.

An example of the address format is shown in FIG. RADR fields A22 to A29 are upper RAM 3
3 and the RAM address of the lower RAM 34 (RADRH0 to
7, RADRL0-7) are commonly used. Further, in the example of FIG. 3, the upper addresses A00 to A21 are all 0.

In the RAM access operation, the bus controller 32 activates CE0 to CE3 corresponding to BC0 to 3, and the upper RAM 33 and the lower RAM 3 in byte units.
Access 4 When the RW signal is 1 and the read bus cycle is set, the RRW signal is set to 1 and data is read from the memory. RR when RW signal is 0 and write bus cycle is RR
The W signal is set to 0 and the data on the bus is written in the upper RAM 33 and the lower RAM 34. Bus controller 3
2 outputs A22 to A29 to RADRH0 to RADRH7 and RADRL0 to 7, and a higher RAM 33 and a lower RA.
Access the same word in M34.

In the RAM access state, the bidirectional buffers 38 and 39 are enabled by the A00 signal, and the direction is controlled by the RW signal. RW
When the signal is 1 and is in the read bus cycle, the output of the RAM is output to the data bus. When the RW signal is 0 and the write bus cycle is set, the data output from the processor is input to the RAM on the data bus. Also, the gate 40 is disabled by the A00, RW, and AS signals, and the output of the multiplier is not output to the data bus. Thus, in the RAM access operation, the upper RAM 3
3 and the lower RAM 34 are accessed as a 32-bit RAM. (2) Multiply operation

In the multiplication operation, the data read from the upper RAM is directly stored in the source register 36, and the data read from the lower RAM is directly stored in the source register 37 using a dedicated line without passing through the data bus. Then, the multiplication results IP0-31 are output to the data bus. The processor reads the multiplication result at the next clock.

The multiplication operation is determined by the address signal and RW signal output from the processor. When the address A00 is 1 and all of A04 to A13 are 0 and RW is 1 (read bus cycle), the multiplication operation is performed.

In the multiplication operation, among the addresses output in the bus cycle, independent fields are assigned to the RAM addresses (RADRH0-7, RADRH0-7, RADRH0-7) of the upper RAM33 and the lower RAM34.
RADRL0-7). As a result, word data independent from the upper RAM and the lower RAM can be read and used as source data for multiplication.

An example of the address format in the multiplication operation is shown in FIG. A00 is 1 and A04 to A13 are all 0, indicating that the multiplication operation is performed. A01,
A02 and A03 are connected to IRND, IXM, and IYM, respectively, and specify a multiplication mode. A14 to A21 are addresses RADRH to the upper RAM, and the word of the upper RAM designated by this field is read out.
A22 to A29 are addresses RADRL to the lower RAM, and the word of the lower RAM designated by this field is read out.

In the multiplication operation, the bus controller 32 uses C
E0 to CE3 are activated, RRW is set to 1, and data is read from the memory. The bus controller 32 is A
14-A21 to RADRH0-RADR7, A22-
A29 is output to RADRL0 to RADRL7 to read independent words in the upper RAM and the lower RAM. The data read from the upper RAM is transferred to the source register 36 and the lower RAM
The data read from is stored in the source register 37 and output to the multiplier 35. At this time, the bidirectional buffers 38 and 39 are disabled by the A00 signal, and the RAM output is not output to the data bus. The gate 40 is enabled by the A00, RW, and AS signals, and the output of the multiplier is output to the data bus. Therefore, the processor can perform 16-bit multiplication in one read bus cycle.

In order to realize the above-mentioned RAM access operation and multiplication operation, the bus controller 32 has a structure as shown in FIG. Read / write signal R to RAM
The RW becomes 0 (Low level) by the gate 65 only while AS is active (0: Low level) in the write bus cycle. When all of A00 to A21 are 0 (Low level), the RAM is accessed and the RM signal becomes active (0: Low level). A00 is 1 and A0
When all of 4 to A13 are 0 and RW is 1, the multiplication operation is performed, and the MM signal becomes active (0: Low level). CE0 to CE3 are active (0: low level) while AS is active in the RAM access operation and the multiplication operation. When the MM signal is active and multiplication operation is performed,
A14 to 1 are RADRH0 to RAD by the selector 61
It is output to RH7. Otherwise, A22 to A29 are RA
It is output to DRH0 to RADRH7. RADRL0
A22 to A29 are output to 7. In the case of RAM access, the data transfer end signal DC is returned to the processor at the bus cycle start clock. Therefore, RAM access is executed in one clock. In the multiplication operation, the bus controller returns the data transfer end signal DC to the processor with a delay of 1 clock by the flip-flop 62. The multiplication operation is completed in 2 clocks. During the multiplication operation, the falling edge of SCLK is output.

FIG. 6 shows the timing of the multiplication operation. At clock 1, the processor 31 outputs the address corresponding to FIG. Where IRND = IXM = I
It is assumed that YM = 0, RADRH field = A, and RADRL field = B. The bus controller recognizes the address of the multiplication operation and activates CE0 to CE3 (0: Lo
w level). In the upper RAM 33, A is the lower RA
B is given to M34, and the contents of the respective RAMs are output to the source registers 36 and 37. The output from the RAM is latched in the source registers 36 and 37 at the falling edge of SCLK from the bus controller 32. The multiplication is calculated by the latched data. At clock 2, the bus controller activates the data transfer end signal DC. The processor 31 reads the multiplication result output on the data bus via the buffer 40. There is the same one clock time as in the conventional example from setting the value in the source register to reading the multiplication result.
Therefore, the same speed multiplier can be used. In this embodiment, since one multiplication is performed in one read bus cycle, it can be executed in a minimum of two clock cycles.

Next, a programming example in the case of performing multiplication in the processor system of the present invention will be shown. Since multiplication is executed in one read bus cycle, mov @me
A memory-to-register transfer instruction such as m or reg is used. Here, the first operand indicates a memory read access, and if mem is an address value for the multiplication operation shown in FIG. 5, the multiplication result can be stored in the internal register reg.

For example, the unsigned word (16 bits) data A at the address h'10 (h 'indicates a hexadecimal number) and the unsigned word data B at the address h'C2 are multiplied, and the 32-bit multiplication result is obtained. Consider the instruction that stores a in the internal register r0 of the processor.

Data A is stored in the upper RAM,
The word address of the RAM is h'04. Also,
The data B is stored in the lower RAM, and the word address of the RAM is h'30. Therefore, the address of the multiplication operation shown in FIG. 4 is A00 = 1, IRN
From D = IXM = IYM = 0, A01 = A02 = A03 =
0, A04 to A13 = 0 to 0, A14 to A21 = h'0
4, A22 to A29 = h'30, and the address becomes h'800010c0. Therefore, the product of the data A and B can be obtained from mov @ h'800010c0, r0 and stored in the internal register r0.

Only the result of rounding the upper 16 bits is r0
If the data is to be stored in, the address can be read with a 16-bit width from the address of A01 = 1 from IRND = 1. This command looks like this: mov @ h'c00010c0. h, r0. ".h" after the h operand indicates that the data transfer is 16 bits wide. If the data is a signed integer, it is sufficient to read from the address where IXM and IYM are set to 1. As the next example of the program, data A and B
Consider an inner product operation that adds the product of This can be realized by the following addition instruction. add @ h'800010c0, r0

The add instruction add adds the value of the first operand to the second operand. Therefore, in the above instruction, the data A and B read from the address h'800010c0
Will add the product of to r0. The inner product operation is an operation that frequently appears in applications such as signal processing, and this processor system can easily realize this operation with an addition instruction.

Next, a second embodiment of the present invention is shown in FIG. In the first embodiment, in the multiplication, one of the source data must be stored in the upper RAM and the other must be stored in the lower RAM. In the second embodiment, the RAM is a 2-port RA
By constructing with M, such a restriction is eliminated. The processor system of the second embodiment includes a processor 81, a bus controller 82, a 2-port RAM 8
3, a multiplier 85, a source register 86, a source register 87, buffers 88, 89 and 90, and gates 91 and 92. Bus controller 82 and 2 port R
Except for AM83, it is the same as the first embodiment.

The bus controller 82 is a 2-port RAM
It is a circuit for controlling access to 83 and writing data to the source register 86 and the source register 87. The bus controller 82 has address signals A00 to A29 and byte control signals BC0 to B output by the processor.
The C3, read / write signal RW, and AS signal are input via the address bus and the control bus. 2-port RA
Address signal RADR to upper port PORTH of M83
H0 to RADRH8 and enable signals CE0, CE1,
Lower port PORTL address signal RADRL0-RA
The DRL 8 and the enable signals CE 2 and CE 3 are commonly output as the read / write signal RRW. It also outputs the SCLK signal indicating the timing of the data latch of the source register 36 and the source register 37 of the multiplier.

Similar to the first embodiment, the RAM access operation is performed when A00 to A28 are all 0 bus cycles. At this time, the bus controller 82 uses RADRH0.
= 0, RADRH1 to RADRH8 = A22 to A29,
RADRL = 1, RADRL1 to RADRL8 = A22
~ A29 is output.

When A00 = 1 and A04 to A13 = 0 to 0 and RW = 1 (read access), the multiplication operation is performed. At this time, the bus controller 82 uses CE0 to CE.
3 is activated and RADRH0-8 are A12-A2
0 and outputs A21 to A29 to RADRL0 to RADRL8. The address format at this time is shown in FIG.

The 2-port RAM 83 is a memory that stores data and programs, and is a high-order port PORTH.
Are connected to the data buses D00 to D15 via the buffer 88. The lower port PORTL is connected to the data buses D16 to D31 via the buffer 89. Two
Each word of the port RAM has an address signal RADRH0.
.About.8 and RADRL0 to 8 can access two words at the same time. In this embodiment, since there are nine addresses, the size of the 2-port RAM is 1 Kbyte.

As described above, in the second embodiment, the RAM is set to 2
By making the port RAM, any two data can be read at the same time and can be used as the source data of the multiplier.

The content of the invention is not limited to this. For example, it is equally applicable to a 32-bit width RAM. Also, the multiplier has been described as having 16 bits for input and 32 bits for output, but it is not limited to this.
It can also be applied to a multiplier having 32 bits of input and 32 bits of output.

In the embodiment, the case where the RAM size is 1 Kbytes in total has been described, but the present invention is not limited to this, and a RAM having a size of 512 bytes or 2 Kbytes can be applied. Although the case where the RAM is used as the memory has been described in the embodiment, the present invention is not limited to this, and the ROM may be used.

Further, although the example of the multiplier has been described in the embodiment, the method of the present invention can be applied to an arithmetic circuit which inputs data from the outside and outputs an arithmetic result therefor. For example, the method of the present invention can be applied to a floating point arithmetic circuit.

In the embodiment, the case where two source data are simultaneously input to the arithmetic unit has been described, but the present invention is not limited to this, and one or three or more data are simultaneously input to the arithmetic unit. May be.

[0056]

According to the present invention, since the source data of the arithmetic unit can be given from the memory to the arithmetic unit at the same time, the head of data transfer can be reduced. For example, when a multiplier capable of multiplying by one clock is used as the arithmetic unit, the multiplication, which takes a minimum of three clocks in the conventional system, can be executed in a minimum of two clocks in the present invention.

Further, in the present invention, since multiplication can be performed by one read operation, multiplication can be performed by one data transfer instruction. In the conventional example, two write bus cycles and one read bus cycle had to be executed, so three instructions were required. Assuming that the number of execution clocks of the instruction that performs the read operation is 4 clocks and the number of execution clocks of the instruction that executes the write bus cycle is 2 clocks, the multiplication that took 8 clocks in the conventional example can be performed in 4 clocks in the present invention. In this way, the multiplication can be processed faster than in the conventional example. At the same time, the present invention can reduce the code size of the program.

Further, according to the present invention, the inner product operation can be realized at high speed with one add instruction. The inner product operation is an operation that appears frequently in signal processing and the like, and the processor system of the present invention can exhibit high performance in such an application.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit configuration diagram showing a first embodiment of the present invention.

FIG. 3 is an address format used in the first embodiment of the present invention.

FIG. 4 is an address format used in the first embodiment of the present invention.

FIG. 5 is a circuit configuration diagram showing a first embodiment of the present invention.

FIG. 6 is a timing chart showing a first embodiment of the present invention.

FIG. 7 is a circuit configuration diagram showing a second embodiment of the present invention.

FIG. 8 is an address format used in the second embodiment of the present invention.

FIG. 9 is a circuit configuration diagram showing a conventional example.

FIG. 10 is a timing chart during operation of the conventional example.

[Explanation of symbols]

 31 Processor 32 Bus Controller 33 Upper RAM 34 Lower RAM 35 Multiplier 36, 37 Source Register 38, 39, 40 Buffer 41, 42 Gate

Claims (5)

[Claims] 1. A processor for outputting an address signal and a control signal to read data on a data bus into an internal register, and a memory for outputting data designated by the address signal output by the processor according to the control signal of the processor. A circuit, an arithmetic circuit for inputting the output data of the memory circuit through a dedicated line and performing an arithmetic operation and outputting the arithmetic result, and the arithmetic result from the arithmetic circuit according to the address signal and the control signal of the processor. A processor system comprising: a first buffer circuit for controlling whether to output to a data bus. 2. The memory circuit receives two or more independent signal groups of the address signals of the processor as inputs, and outputs two or more independent data designated by the signal groups. The processor system according to claim 1. 3. A second buffer circuit for controlling whether or not the output signal of the memory circuit is connected to the data bus according to the address signal and the control signal of the processor, the first buffer circuit comprising: The buffer circuit and the second buffer circuit are
2. The processor system according to claim 1, wherein when one of them outputs data to the data bus, the other does not output. 4. A second buffer circuit for controlling whether or not the output signal of the memory circuit and the data bus are connected by the address signal and the control signal of the processor, and the address signal of the processor. A bus control circuit that outputs two or more independent signal groups of the address signals of the processor to the memory circuit when it is determined that the processor reads the output from the arithmetic circuit based on the control signal and the control signal. And the first buffer circuit and the second buffer circuit are
3. The method according to claim 2, wherein when one of them outputs data to the data bus, the other does not output.
The processor system described. 5. The processor system according to claim 1, wherein the arithmetic circuit is a multiplication circuit.