JPH06276190A - Bulk transfer device - Google Patents

Abstract

PURPOSE:To enable bulk transfer by adding the external input/output terminals of a circuit for two-channel bulk transfer use and a register, cascade-connecting them and specifying as 64kbpsX(n) ((n) is an integer of >=2.) CONSTITUTION:This device is provided with interface circuits 15, 18, ..., provided with the layer 1 function of an ISDN (integrated services digital network) circuit, bulk transfer circuits for performing the delay correction of data corresponding to control signals and memories 17, 20, ..., for storing the data to be corrected in delay. Also, cascade connected plural correction circuits 11, 12, ... 13 and the function of the layers 2 and 3 of the ISDN circuit are provided and a control circuit CPU 14 for supplying the control signals simultaneously to the respective correction circuits is provided. In such a manner, by cascade- connecting the control circuit CPU 14, the delay correction of a B channel >=2B is enabled and the data transfer of 64kbpsX(n) ((n is the integer of >=2) >=125kbps can be executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention utilizes a circuit switching service of an integrated digital communication network (ISDN) to provide 64 nk
The present invention relates to a bulk transfer device that performs bps (n is an integer) communication.

[0002]

2. Description of the Related Art FIG. 3 shows the configuration of a conventional 2 × 64 kbps bulk transfer device. In FIG. 3, 33 is I
An SDN (Comprehensive Digital Communication Network) I / F (interface) LSI (hereinafter referred to as "I / F / .LSI") having a layer 1 function of an ISDN line. A control circuit (CPU) 32 has a control function of data delay correction for bulk transfer, in addition to the functions of layers 2 and 3 of the ISDN line. Reference numeral 34 denotes a bulk transfer control circuit, which has a function of correcting delay of data by a signal from the control circuit 32. Reference numeral 35 is a delay correction memory for delay correction.

FIG. 4 shows a functional configuration of the bulk transfer control circuit 34 of the conventional bulk transfer device shown in FIG.

In FIG. 4, reference numeral 41 denotes a B1 channel reception counter latch circuit, which has a function of latching the B1 counter input by a latch signal from the control circuit 32. A B2 channel reception counter latch circuit 42 has a function of latching the B2 counter input by a latch signal from the control circuit 32. Reference numeral 43 is a read counter for reading data from the delay correction memory 35, and has a function of selecting either the B1 or B2 channel in response to a select signal from the control circuit 32.

Next, the operation of the above conventional example will be described.
In FIG. 3, when there is an incoming call from the ISDN line to the device or when an outgoing call is made from the device to the ISDN line, the Dch call control is performed by the control circuit 32 through the ISDN basic I / F / LSI 33. I do. Dch
When the Bch is connected by the call control of, the counter value is extracted from the B1 channel data and the B2 channel data. When the latch signal is input from the control circuit 32, the counter values of the B1 and B2 channels are latched by the counter latch circuits 41 and 42. After the latched counter value is read out by the control circuit 32 and its judgment is performed, when the select signal is input from the control circuit 32, the counter value of the selected B1 or B2 channel is output to the read counter 43.

The B1 and B2 channel data are written to the address of the reception counter in the delay correction memory 35 and read from the address of the read counter 43.

[0007]

However, in the above-mentioned conventional example, only the delay correction of the data for two channels B1 and B2 can be performed, and therefore 64 kbps × 2 = 128 kb.
There is a problem that only ps data transmission can be performed, and a request for high speed transmission cannot be met.

The present invention solves such a conventional problem. By adding an input terminal of a counter latch signal from the outside and a data read register to the bulk transfer control circuit and connecting them in cascade, 64k
An object of the present invention is to provide a bulk transfer device for realizing data communication of 128 kbps or more of bps × n (n ≧ 2).

[0009]

In order to achieve the above object, the present invention provides an interface circuit having a layer 1 function of an ISDN line, a bulk transfer circuit for performing delay correction of data according to a control signal, and data for delay correction. A control circuit having a memory for storing a plurality of correction circuits connected in cascade and having the functions of layers 2 and 3 of the ISDN line, and supplying the control signal to each of the plurality of correction circuits at the same time. And are provided.

[0010]

The present invention has the following actions (effects) with the above-mentioned constitution. That is, by connecting the control circuit in a cascade, it is possible to realize delay correction of B channel of 2B or more and data transfer of 64 kbps × n of 128 kbps or more.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the configuration of an embodiment of the bulk transfer device of the present invention. In FIG. 1, 15 and 18 are I
It is an SDN basic I / F / LSI and has the layer 1 function of the ISDN line.

Reference numeral 14 designates a control circuit (CPU), and an ISD.
In addition to the N-layer layer 2 and layer 3 functions, it has a data delay correction function for bulk transfer. Bulk transfer control circuits 16 and 19 have a function of performing data delay correction by a signal from the control circuit 14. Reference numerals 17 and 20 denote delay correction memories for delay correction.

The block 11 shown by a dotted line is generically referred to as a delay correction circuit 1, the block 12 is a delay correction circuit 2 and the block 13 is a delay correction circuit n. These n delay correction circuits are connected in cascade. .

FIG. 2 shows a functional configuration of the bulk transfer control circuit of the embodiment. In FIG. 2, reference numeral 21 is a correction circuit 1.
B1 channel reception counter latch circuit, which latches the B1 counter input by a latch signal from the control circuit 14. Reference numeral 22 denotes a B2 channel reception counter latch circuit of the correction circuit 1, which latches the B2 counter input by a latch signal from the control circuit 14. Reference numeral 25 denotes a B1 channel reception counter latch circuit of the correction circuit 2, which latches the B1 counter input by a latch signal from the correction circuit 1. Reference numeral 26 denotes a B2 channel reception counter latch circuit of the correction circuit 2, which latches the B2 counter input by the latch signal from the correction circuit 1. 27, 2
Reference numeral 8 is a read counter register, which sets the contents of the counter for reading from the control circuit 14. Reference numerals 29 and 30 denote transmission counters, which are reset by a reset signal input from the control circuit 14.

Next, the operation of the above embodiment will be described.
In FIG. 1, when an incoming call is made from the ISDN line to the device or when an outgoing call is made from the device to the ISDN line, the Dch call control is performed by the control circuit 14 through the I / F / LSIs 15 and 18. To do. When the Bch is connected by the Dch call control, the correction circuits 1 and 2 extract the counter values from the B1 channel data and the B2 channel data, respectively. When the latch signal from the control circuit 14 is input, the counter values of the B1 and B2 channels are latched by the counter latch circuits 21 and 22. Further, since this latch signal is output from the correction circuit 1 and input to all the other correction circuits connected in the cascade, all counters are latched at the same time. That is, the counter values of the B1 channel and B2 channel are also latched in the counter latch circuits 25 and 26. After reading the latched counter from the control circuit 14 and making the determination,
The most advanced counter value is set by the control circuit 14 in the read counter registers 27 and 28 of each correction circuit. The B1 channel data and the B2 channel data are written to the delay correction memories 17 and 20 at the address of the reception counter and read at the address of the read counter. Further, the transmission counters 29 and 30 are reset to a common reset input from the control circuit 14.

[0016]

The present invention is clear from the above embodiment,
It has the following effects.

That is, the input / output terminal of a latch signal for simultaneously latching the reception counter value, the reset signal input terminal of the transmission counter, and the register for setting the value of the read counter from the control circuit are 64 kbps × n (n ≧ 2). Data can be transferred, and high-speed transmission of 128 kbps or higher can be performed.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of a bulk transfer device of the present invention.

FIG. 2 is a diagram showing a functional configuration of a bulk transfer control circuit in FIG.

FIG. 3 is a block diagram of a conventional bulk transfer device.

FIG. 4 is a diagram showing a functional configuration of a conventional bulk transfer control circuit.

[Explanation of symbols]

 11 correction circuit 1 12 correction circuit 2 13 correction circuit n 14 control circuit (CPU) 15 ISDN basic I / FLSI1 16 bulk transfer control circuit 1 17 delay correction memory 1 18 ISDN basic I / FLSI2 19 bulk transfer control circuit 2 20 delay correction Memory 2 21 Correction circuit 1B1 channel counter latch circuit 22 Correction circuit 1B2 channel counter latch circuit 23 Correction circuit 1 24 Correction circuit 2 25 Correction circuit 2B1 channel counter latch circuit 26 Correction circuit 2B2 channel counter latch circuit 27 Correction circuit 1 read counter 28 Correction Circuit 2 read counter 29 Correction circuit 1 transmission counter 30 Correction circuit 2 transmission counter 31 Correction circuit 32 Control circuit (CPU) 33 ISDN basic I / F LSI 34 Bulk transfer control circuit 35 Delay correction memory 41 B1 chip Channel counter latch circuit 42 B2 channel counter latch circuit 43 read counter 44 transmission counter

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location H04L 12/50 29/04 8220-5K H04L 13/00 303 Z

Claims (1)

[Claims] 1. A bulk transfer device for performing communication of 64 × nkbps (n is an integer) by using two or more B channels by a circuit switching service of an integrated digital communication network (ISDN), and a layer of the ISDN line. A plurality of cascaded correction circuits having an interface circuit having one function, a bulk transfer circuit that performs delay correction of data according to a control signal, and a memory that stores data for delay correction, and a layer 2 of the ISDN line. And a control circuit that has the function of layer 3 and that supplies the control signal to each of the plurality of correction circuits at the same time.