JPH06268132A - Lead frame for semiconductor device - Google Patents
Lead frame for semiconductor deviceInfo
- Publication number
- JPH06268132A JPH06268132A JP8264693A JP8264693A JPH06268132A JP H06268132 A JPH06268132 A JP H06268132A JP 8264693 A JP8264693 A JP 8264693A JP 8264693 A JP8264693 A JP 8264693A JP H06268132 A JPH06268132 A JP H06268132A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- gold
- nickel
- semiconductor device
- plated part
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Other Surface Treatments For Metallic Materials (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Chemically Coating (AREA)
- Electroplating Methods And Accessories (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、めっき処理された半導
体装置用リードフレームに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame for a semiconductor device which has been plated.
【０００２】[0002]
【従来の技術】半導体装置用リードフレームは、半導体
素子との良好な接合性、半導体素子とインナーリードを
接続するワイヤとのワイヤボンディング性、及びアウタ
ーリードを外部機器に接続する為にはんだ付け性が良い
ことを要求される。この為、リードフレームの表面の全
部あるいは一部には、金めっき皮膜を形成している。2. Description of the Related Art A lead frame for a semiconductor device has a good bondability with a semiconductor element, a wire bondability with a wire connecting a semiconductor element and an inner lead, and a solderability for connecting an outer lead to an external device. Is required to be good. Therefore, a gold plating film is formed on all or part of the surface of the lead frame.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、従来の
金めっき皮膜は比較的皮膜の厚みが１μｍ以上と厚く、
このため高価な金を大量に使用するという問題点があっ
た。そこで、一部においては、銀めっき皮膜も使用され
ているが、マイグレーションの問題があり、近年のよう
に隣合うリードのピッチが極めて小さいリードフレーム
においては、使用中に故障を生じる等の問題点があっ
た。本発明はかかる事情に鑑みてなされたもので、金の
優れた特性を生かしつつ、比較的安価に製造できる半導
体装置用リードフレームを提供することを目的とする。However, the conventional gold plating film has a relatively large film thickness of 1 μm or more,
Therefore, there is a problem that a large amount of expensive gold is used. Therefore, silver plating film is also used in some of them, but there is a problem of migration, and in a lead frame in which the pitch of adjacent leads is extremely small as in recent years, there is a problem such as failure during use. was there. The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a lead frame for a semiconductor device, which can be manufactured at a relatively low cost while taking advantage of the excellent characteristics of gold.
【０００４】[0004]
【課題を解決するための手段】前記目的に沿う請求項１
記載の半導体装置用リードフレームは、下地ニッケルめ
っきをした銅系合金からなる導電部材の全面あるいは所
要部分に０．１５μｍ以下の金めっきをして構成されて
いる。請求項２記載の半導体装置用リードフレームは、
請求項１記載の半導体装置用リードフレームにおいて、
下地ニッケルめっきは、２層以上となっている。請求項
３記載の半導体装置用リードフレームは、下地銅めっき
をしたニッケル系合金からなる導電部材にニッケルめっ
きを行い、しかる後その全面あるいは所要部分に０．１
５μｍ以下の金めっきをして構成されている。請求項４
記載の半導体装置用リードフレームは、請求項３記載の
半導体装置用リードフレームにおいて、ニッケルめっき
は、２層以上となっている。なお、所要部分とは、該リ
ードフレームに他の機器を接続するワイヤボンディング
及び／又ははんだ付けを行うアウターリード等をいう。
また、銅めっき及びニッケルめっきには電解めっきで行
う場合の他、無電解めっきで行う場合も含む。A method according to the above-mentioned object.
The semiconductor device lead frame described above is formed by gold plating of 0.15 μm or less on the entire surface or a required portion of a conductive member made of a copper-based alloy plated with nickel base. The lead frame for a semiconductor device according to claim 2,
The lead frame for a semiconductor device according to claim 1,
The underlying nickel plating has two or more layers. In the lead frame for a semiconductor device according to claim 3, a conductive member made of a nickel-based alloy plated with a base copper is plated with nickel, and thereafter, the entire surface or a required portion is coated with 0.1.
It is configured by gold plating of 5 μm or less. Claim 4
The above described lead frame for a semiconductor device is the lead frame for a semiconductor device according to claim 3, wherein the nickel plating has two or more layers. The required portion means an outer lead or the like for wire bonding and / or soldering for connecting another device to the lead frame.
Further, copper plating and nickel plating include not only electrolytic plating but also electroless plating.
【０００５】[0005]
【作用】請求項１〜４記載の半導体装置用リードフレー
ムにおいては、表面には金めっきが全部あるいは所要部
分に行われているので、ワイヤボンディング性及びはん
だ濡れ性が良く、更にはその厚みが０．１５μｍ以下で
あるので極めて薄く、これによって高価な金の使用量が
大幅に減少する。そして、薄い金めっきの下層にはニッ
ケルめっきが行われているので、表面の薄い金めっき層
を通して下地の銅が拡散するのを防止できる。特に、請
求項２及び４記載の半導体装置用リードフレームにおい
ては、ニッケルめっきの処理過程で発生するピンホール
を最小限に押さえ、下層の銅あるいは鉄の腐食が防止さ
れる。In the lead frame for a semiconductor device according to claims 1 to 4, since gold plating is applied to the entire surface or a required portion of the surface, the wire bonding property and solder wettability are good, and further, the thickness is Since it is 0.15 μm or less, it is extremely thin, which significantly reduces the amount of expensive gold used. Since nickel plating is performed on the lower layer of the thin gold plating, it is possible to prevent the underlying copper from diffusing through the thin gold plating layer on the surface. Particularly, in the semiconductor device lead frame according to the second and fourth aspects, the pinholes generated during the nickel plating process are suppressed to a minimum, and the corrosion of the lower layer copper or iron is prevented.
【０００６】[0006]
【実施例】続いて、本発明を具体化した実施例につき説
明する。ここに、図１は本発明の第１の実施例に係る半
導体装置用リードフレームの使用状況を示す断面図、図
２は本発明の第２の実施例に係る半導体装置用リードフ
レームの部分断面図、図３は本発明の第３の実施例に係
る半導体装置用リードフレームの部分断面図である。図
１に示すように、本発明の第１の実施例に係る半導体装
置用リードフレーム１０は、基材１１が銅系合金からな
って、下地ニッケルめっき１２が施され、その表面には
金めっき１３が施されている。前記下地ニッケルめっき
１２はその厚みが０．２〜１μｍ程度となって、前記金
めっき１３は厚みが０．１μｍ程度となっている。EXAMPLES Next, examples embodying the present invention will be described. 1 is a cross-sectional view showing the usage of the lead frame for a semiconductor device according to the first embodiment of the present invention, and FIG. 2 is a partial cross-section of the lead frame for a semiconductor device according to the second embodiment of the present invention. 3 and 4 are partial sectional views of a lead frame for a semiconductor device according to a third embodiment of the present invention. As shown in FIG. 1, in a lead frame 10 for a semiconductor device according to a first embodiment of the present invention, a base material 11 is made of a copper-based alloy, a base nickel plating 12 is applied, and the surface thereof is gold plated. 13 has been applied. The base nickel plating 12 has a thickness of about 0.2 to 1 μm, and the gold plating 13 has a thickness of about 0.1 μm.
【０００７】前述のように、薄い金めっき１３の下地に
ニッケルめっき１２を行うことによって仮に金めっき１
３の表面にピンホール等があった場合にでも、銅合金か
らなる基材１１と金との作用によって局部電池が形成さ
れ、基材１１が陽極となって急速に腐食するのを防止で
きる。なお、図１において、１４は半導体素子を、１５
はボンディングワイヤを示す。As described above, the gold plating 1 is temporarily performed by performing the nickel plating 12 on the base of the thin gold plating 13.
Even if there is a pinhole or the like on the surface of No. 3, it is possible to prevent a local battery from being formed by the action of the base material 11 made of a copper alloy and gold, and the base material 11 serving as an anode to be rapidly corroded. In FIG. 1, 14 is a semiconductor element, and 15 is a semiconductor element.
Indicates a bonding wire.
【０００８】この為、下地ニッケルめっきはピンホール
が極めて少ない状態で行う必要があり、緻密なめっき層
が形成される無電解めっきによって行うのが好ましい
が、図２の第２の実施例に示すように、基材１１の表面
に無電解めっき法あるいは電解めっき法を用いて下地ニ
ッケルめっき１６、１７を２層あるいは多層に渡って行
い、その上に金めっき１３を行うのが好ましく、これに
よってめっき処理中に発生するピンホールを無くし、基
材１１の腐食を防止する。For this reason, it is necessary to perform the nickel plating on the base in a state where there are very few pinholes, and it is preferable to perform the electroless plating in which a dense plating layer is formed. However, as shown in the second embodiment of FIG. As described above, it is preferable that the base nickel plating 16, 17 is applied to the surface of the base material 11 in two or more layers by using the electroless plating method or the electrolytic plating method, and the gold plating 13 is applied thereon. Pinholes generated during the plating process are eliminated to prevent corrosion of the base material 11.
【０００９】次に、図３に示す本発明の第３の実施例に
ついて説明するが、ニッケル合金系からなるリードフレ
ームの基材１８の表面には下地銅めっき１９が施され、
中間層としてニッケルめっき２０が施され、表面には薄
い金めっき２１が行われている。前記金めっき２１は
０．１μｍ程度となって、下地銅めっき１９、ニッケル
めっき２０は０．２〜１μｍ程度の厚みとなっている。Next, a third embodiment of the present invention shown in FIG. 3 will be described. A base copper plating 19 is applied to the surface of a base material 18 of a lead frame made of a nickel alloy.
Nickel plating 20 is applied as an intermediate layer, and thin gold plating 21 is applied on the surface. The gold plating 21 has a thickness of about 0.1 μm, and the base copper plating 19 and the nickel plating 20 have a thickness of about 0.2 to 1 μm.
【００１０】ここで、下地銅めっき１９、ニッケルめっ
き２０は、上部にイオン化傾向の小さい金がめっきされ
ていることによる金と基材との電池作用による腐食を防
止する為のものである。また、前記ニッケルめっき２０
は一層で行うと、ピンホール等が生じ易いので、多層で
行う方が好ましく、更には、前記銅めっき１９及びニッ
ケルめっき２０は、無電解めっきで行うのが好ましい。
これによって緻密なめっき層を形成し、ピンホール等が
形成されるのを防止できる。Here, the base copper plating 19 and the nickel plating 20 are for preventing the corrosion of gold and the base material due to the cell action due to the plating of gold having a low ionization tendency on the top. Also, the nickel plating 20
If it is performed in a single layer, pinholes and the like are likely to occur, so it is preferable to perform it in multiple layers, and further, the copper plating 19 and nickel plating 20 are preferably performed in electroless plating.
This can form a dense plating layer and prevent formation of pinholes and the like.
【００１１】[0011]
【発明の効果】請求項１〜４記載の半導体装置用リード
フレームにおいては、表面には金めっきが全部あるいは
所要部分に行われているので、ワイヤボンディング性及
びはんだ濡れ性が良く、半導体素子と連結するワイヤ、
アウターリードに更にはんだめっきを行ったり、はんだ
付けすることが容易にできる。更には、金めっきの厚み
が０．１５μｍ以下であるので極めて薄く、これによっ
て高価な金の使用量が大幅に減少でき、廉価な半導体装
置用リードフレームを提供できる。そして、薄い金めっ
きの下層にはニッケルめっきが行われているので、表面
の薄い金めっき層を通して下地の銅が拡散するのを防止
でき、これによってリードフレームの腐食を防止でき、
長期の寿命を有する半導体装置を提供できる。特に、請
求項２及び４記載の半導体装置用リードフレームにおい
ては、ニッケルめっきの処理過程で発生するピンホール
を最小限に押さえ、下層の銅あるいは鉄の腐食が防止さ
れ、これによってリードフレームの腐食、マイグレーシ
ョンによるリード間短絡等を防止できる。In the lead frame for a semiconductor device according to the first to fourth aspects, since gold plating is applied to the entire surface or a required portion of the surface, the wire bonding property and solder wettability are good, and the semiconductor element and Wire to connect,
The outer leads can be easily plated with solder or soldered easily. Furthermore, since the thickness of the gold plating is 0.15 μm or less, it is extremely thin, so that the amount of expensive gold used can be greatly reduced, and an inexpensive lead frame for a semiconductor device can be provided. Then, since nickel plating is performed on the lower layer of the thin gold plating, it is possible to prevent the underlying copper from diffusing through the thin gold plating layer on the surface, thereby preventing corrosion of the lead frame,
A semiconductor device having a long life can be provided. Particularly, in the lead frame for a semiconductor device according to claims 2 and 4, pinholes generated during the nickel plating process are minimized to prevent corrosion of the copper or iron in the lower layer, which leads to corrosion of the lead frame. It is possible to prevent a short circuit between leads due to migration.
【図１】本発明の第１の実施例に係る半導体装置用リー
ドフレームの使用状況を示す断面図である。FIG. 1 is a cross-sectional view showing a usage state of a lead frame for a semiconductor device according to a first embodiment of the present invention.
【図２】本発明の第２の実施例に係る半導体装置用リー
ドフレームの部分断面図である。FIG. 2 is a partial cross-sectional view of a semiconductor device lead frame according to a second embodiment of the present invention.
【図３】本発明の第３の実施例に係る半導体装置用リー
ドフレームの部分断面図である。FIG. 3 is a partial cross-sectional view of a semiconductor device lead frame according to a third embodiment of the present invention.
１０ リードフレーム １１ 基材 １２ 下地ニッケルめっき １３ 金めっき １４ 半導体素子 １５ ボンディングワイヤ １６ ニッケルめっき １７ ニッケルめっき １８ 基材 １９ 下地銅めっき ２０ ニッケルめっき ２１ 金めっき 10 Lead Frame 11 Base Material 12 Nickel Base Plating 13 Gold Plating 14 Semiconductor Element 15 Bonding Wire 16 Nickel Plating 17 Nickel Plating 18 Base Material 19 Base Copper Plating 20 Nickel Plating 21 Gold Plating
Claims (4)
なる導電部材の全面あるいは所要部分に０．１５μｍ以
下の金めっきをしたことを特徴とする半導体装置用リー
ドフレーム。1. A lead frame for a semiconductor device, characterized in that a conductive member made of a copper-based alloy plated with a base nickel is plated with gold of 0.15 μm or less on the entire surface or a required portion.
ている請求項１記載の半導体装置用リードフレーム。2. The lead frame for a semiconductor device according to claim 1, wherein the underlying nickel plating has two or more layers.
なる導電部材にニッケルめっきを行い、しかる後その全
面あるいは所要部分に０．１５μｍ以下の金めっきをし
たことを特徴とする半導体装置用リードフレーム。3. A lead frame for a semiconductor device, characterized in that a conductive member made of a nickel-based alloy plated with a base copper is plated with nickel, and then the entire surface or a required portion is plated with gold of 0.15 μm or less. .
る請求項３記載の半導体装置用リードフレーム。4. The lead frame for a semiconductor device according to claim 3, wherein the nickel plating has two or more layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5082646A JP2826650B2 (en) | 1993-03-16 | 1993-03-16 | Lead frame for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5082646A JP2826650B2 (en) | 1993-03-16 | 1993-03-16 | Lead frame for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06268132A true JPH06268132A (en) | 1994-09-22 |
| JP2826650B2 JP2826650B2 (en) | 1998-11-18 |
Family
ID=13780200
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5082646A Expired - Lifetime JP2826650B2 (en) | 1993-03-16 | 1993-03-16 | Lead frame for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2826650B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009007656A (en) * | 2007-06-29 | 2009-01-15 | Japan Pure Chemical Co Ltd | Electrolytic gold-plating solution and gold plated film obtained using the same |
| US7843700B2 (en) | 2004-04-14 | 2010-11-30 | Denso Corporation | Semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4949264A (en) * | 1972-05-17 | 1974-05-13 | ||
| JPH04174546A (en) * | 1990-11-07 | 1992-06-22 | Furukawa Electric Co Ltd:The | Manufacture of semiconductor lead frame |
-
1993
- 1993-03-16 JP JP5082646A patent/JP2826650B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4949264A (en) * | 1972-05-17 | 1974-05-13 | ||
| JPH04174546A (en) * | 1990-11-07 | 1992-06-22 | Furukawa Electric Co Ltd:The | Manufacture of semiconductor lead frame |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7843700B2 (en) | 2004-04-14 | 2010-11-30 | Denso Corporation | Semiconductor device |
| US8179688B2 (en) | 2004-04-14 | 2012-05-15 | Denso Corporation | Semiconductor device |
| JP2009007656A (en) * | 2007-06-29 | 2009-01-15 | Japan Pure Chemical Co Ltd | Electrolytic gold-plating solution and gold plated film obtained using the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2826650B2 (en) | 1998-11-18 |
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