JPH06260608A - Semiconductor storage - Google Patents

Abstract

PURPOSE:To suppress an amount of scattering of mutual conductance of transistors and to prevent reduction in read speed and generation of malfunction by providing a first dummy wiring region with a wiring pattern in the same shape at the inside and outside of a bit line amplifier circuit with a predetermined first wiring pattern. CONSTITUTION:Since a bit line balancing circuit 4. bit line amplifier circuits 1, 2, and 3, and a bit line selection circuit 5 are connected to bit line pairs constituting a memory cell array region 6. they are laid out being adjacent to the memory cell array region 6. The bit line balancing circuit 4 is laid out along one side of each memory array region 6, a dummy wiring region 9, the bit line amplifier circuits 1, 2, and 3, a dummy wiring region 10, and further the bit line selection circuit 5 are provided in order at the outside viewed from the memory cell array region 6 of the bit line balancing circuit 4, thus preventing nonuniformity in diffraction of light on mask pattern exposure.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device, and more particularly to the structure of a peripheral circuit of a static random access memory (SRAM).

[0002]

2. Description of the Related Art Generally, a semiconductor memory device such as an SRAM comprises a memory cell array region and a peripheral circuit such as a decoder circuit and a bit line amplifier circuit adjacent to the memory cell array region. Of these peripheral circuits, a bit line amplifier circuit that amplifies the data of the bit lines that configure the memory cell array, a bit line selection circuit that selects a specific bit line, and a bit line balancing circuit that balances the bit line pairs to the same potential. It is necessary to install a specific peripheral circuit such as for each bit line pair.
Therefore, these specific peripheral circuits are arranged along one side of the rectangular memory cell array region. The transistor (FET, the same applies hereinafter) gate electrodes forming these specific peripheral circuits are generally formed of a polysilicon film, and the density of the pattern is very high.

[0003]

However, as described above, in the conventional semiconductor memory device including the above-mentioned specific peripheral circuit having such a configuration, the wirings of the respective circuits are densely arranged by a predetermined pattern. . However, since the circuit configurations are different and the wiring patterns of the connecting portions that connect the respective circuits are different, there is a difference in the density of the wiring patterns at that portion, and the regularity of the patterns is different.

The inventor of the present invention has found that when the regularity of the formed pattern is different as described above, the dimension thereof becomes larger or smaller than the design target value, and the amount of variation becomes different. If the width of the wiring, particularly the wiring of polysilicon that becomes the gate electrode of the transistor becomes larger than the design target value, as a result, the channel length of the transistor becomes longer than the design target value. For example, when the design target value of the wiring width of polysilicon is 0.8 μm, the width of the wiring becomes thicker by about 0.06 μm due to the above-mentioned cause, and the channel length of the transistor using the wiring as a gate electrode becomes that much longer. Further, when the value becomes smaller than the design target value, the channel length of the transistor becomes shorter.

One of the reasons why the width of the wiring varies with respect to the design target value is considered to be as follows. If the regularity of the wiring formation pattern is disturbed, the regularity changes in the lithography process for selectively removing the polysilicon film, that is, in the process of applying a photoresist and then exposing with a predetermined mask pattern. The spots affected affect the diffraction of light and change the exposure conditions. That is, the exposure condition changes in such a direction that the width of the selectively left polysilicon film becomes larger or smaller than the design target value.

If there is a difference in the channel lengths of the transistors forming the bit amplifier circuit, the transconductance of the transistors greatly fluctuates, and as a result, the ability of amplifying data from the bit line is deteriorated.

Since the decrease in the data amplification and supply capability from the bit line causes a delay in the potential change of the output of the bit line amplifier circuit at the time of reading the signal, the semiconductor memory device cannot be read.
Not only does it significantly reduce speed, but it also causes malfunctions.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor device which suppresses variations in mutual conductance of transistors forming a peripheral circuit and prevents a decrease in reading speed and occurrence of malfunction.

[0009]

In a semiconductor memory device of the present invention, a memory cell array region formed in a substantially rectangular shape on the surface of a semiconductor substrate and a predetermined side of the memory cell array region are arranged adjacent to each other. A bit line amplifier circuit having a first wiring pattern and a first dummy wiring region having a wiring pattern of the same shape inside and outside the bit line amplifier circuit as viewed from the memory cell array region are provided.

Further, in the semiconductor memory device of the present invention, the bit line amplifier circuits are respectively arranged at both end portions of the bit line amplifier circuit.
And a second dummy wiring region having the wiring pattern of.

Preferably, the first and second dummy wiring regions are formed in the same manufacturing process as the wiring pattern of the bit line amplifier circuit.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to the drawings.
Referring to FIG. 1, a semiconductor chip 8 constituting a semiconductor memory device of an embodiment of the present invention includes a memory cell array region 6 in which memory cells are arranged in an array and a row decoder for selecting a word line according to an input address. 7, a bit line balancing circuit 4 for balancing the bit line pair to the same potential, and bit line amplifier circuits 1, 2, 3, for amplifying the potential on the bit line pair.
It includes a bit line selection circuit 5 for selecting a specific bit and the like (this semiconductor memory device also includes other circuits as peripheral circuits, but these other circuits are omitted for convenience of description).

Since the bit line balancing circuit 4, the bit line amplifier circuits 1, 2, 3 and the bit line selection circuit 5 are connected to the bit line pairs forming the memory cell array region 6, they are adjacent to the memory cell array region 6. Are arranged. Specifically, the bit line balancing circuit 4 is arranged along one side of each memory cell array region 6, and the dummy wiring regions 9 are sequentially arranged outside the memory cell array region 6 of the bit line balancing circuit 4 in order. Bit line amplifier circuit 1,
Bit line selection circuits 5 are provided outside the dummy wiring regions 10, 2, and 3.

As will be described later in detail, the dummy wiring regions 9 and 10 are made of polysilicon wiring layers having line symmetry and similar shapes with respect to the bit line balancing circuits 1, 2 and 3.

Next, referring also to FIG. 2, a plurality of memory cells MC are arranged in an array to form a memory cell array region 6. 1 for each memory cell MC
Word lines WL and two bit line pairs BLa, BLb
(In FIG. 2, only the rightmost column has a bit line pair BL.
a and BLb) are connected to each other. The number of bit line pairs is equal to the number of columns of memory cells forming memory cell array region 6. Each of these bit line pairs includes a bit line balancing circuit 4, bit line amplifying circuits 1, 2, 3 and a bit line selecting circuit 5.
Respectively connected to.

The bit line balancing circuit 4 includes as many transistor MP10s whose source / drain paths are connected to the bit lines BLa and BLb and the gate is connected to the control signal φ as the number of bit line pairs.

The bit line amplifier circuits 1, 2, 3 are
A plurality of transistors MP20 whose drains are connected to one of the output lines of the bit line amplifier circuit and the contact point ε, and whose gates are connected to the bit line BLa, and source / drain paths of which are one of the output lines of the bit amplifier circuit γ And a plurality of transistors MP40 connected to the contact ε and the gate connected to the bit line BLb, and a plurality of transistors connected to the contact ε and the ground power source for the source / drain path and connected to the output α of the bit line selection circuit for the gate. Each MP30 is provided. Transistors MP20, MP30 and MP40
Since there is a restriction on the chip surface area in the arrangement of the above, the area where the plurality of transistors MP20 are formed is defined as the bit line amplifier circuit 3
The region in which the plurality of transistors MP30 are formed is the bit line amplifier circuit 2 and the plurality of transistors MP40
The region in which is formed is formed as the bit line amplifier circuit 1.

The dummy wiring region 9 has a bit line amplifier circuit 3
Is arranged adjacent to the memory cell array region 6 side, and the dummy wiring region 10 is arranged adjacent to the bit line amplifier circuit 1 opposite to the memory cell array region 6 side.

The bit line selection circuit 5 includes a NAND circuit MP60 for inputting a plurality of bit line selection circuit control signal lines μ,
It is composed of an inverter circuit MP50 which inputs the signal input λ and outputs an output signal α.

In the read operation of this semiconductor memory device, one word line WL selected by row decoder 7 is activated. The storage contents of the plurality of memory cells MC connected to the word line WL are supplied to each bit line pair. Bit lines BLa and BLb forming a bit line pair
Either one of them has a potential lower than the power supply potential according to the stored contents of the memory cell MC, and the other bit line remains at the power supply potential. The potential difference of one bit line pair selected by the bit line selection circuit 5 is amplified by the bit line amplification circuits 1, 2 and 3 and sent to an output circuit (not shown) to complete the read operation for one stored content. To do. Then, before the next read, the control signal φ is set to the active level to electrically connect the bit lines BLa and BLb to restore the power supply potential together.

FIG. 3 is a plan view showing the bit line balancing circuit 4, the bit line amplifying circuits 1, 2, 3 and the bit line selecting circuit 7 and the dummy wiring regions 9, 10 of the semiconductor memory device shown in FIG. The same components as those in FIG. 2 are denoted by the same reference numerals.

The transistor MP20 has a diffusion layer forming region 1
2, the gate power source made of the polysilicon layer 11a is the bit line BLb made of the first aluminum film.
To the contact hole 13a, and the drain region is formed of a second aluminum film 14a formed of a layer different from the first aluminum film and the output line β of the bit line amplifier circuit.
Are connected through a plurality of contact holes 15a.

The transistor MP20 has a diffusion layer forming region 1
2, the gate electrode made of the polysilicon layer 11b is connected to the bit line BLa made of the first aluminum film through the contact hole 13b, and the drain region is made of a layer different from the first aluminum film. Become second
Is connected to the output line γ of the bit line amplifier circuit made of the aluminum film 14b through the plurality of contact holes 15b.

The transistor MP30 is similarly formed in the diffusion layer forming region 12, the gate electrode made of the polysilicon layer 11c is connected to the output α of the bit line selecting circuit 5 made of the silicide layer 16 through the contact hole 17, and the source region is It is connected to a ground power source made of the second aluminum film 14c through a contact hole 15c.

The source regions of the transistors MP20 and MP40 and the drain region of the transistor MP30 are connected by the same diffusion layer forming region 12.

The inverter MP50 forming the bit line selection circuit 5 is formed in the diffusion layer forming regions 20a and 20b, and the gate electrode formed of the polysilicon layer 21a is the NAND circuit of the bit line selection circuit 5 formed of the first aluminum film 23. Of the ground power sources 24a and 24b made of aluminum film through the contact holes 22a and 22b, respectively.
And the drain region is connected to the output α of the bit line selection circuit 5 made of the silicide layer 16 and the contact hole 2 respectively.
It is connected through 5a and 25b.

The NAND circuit MP60 is formed in the diffusion layer forming regions 20c and 20d, and the gate electrodes made of the polysilicon layers 21b and 21c are made of the first aluminum film. The bit line selection circuit control signals 23b and 23c are formed. μ through contact holes 25d and 25e, the source region is connected to the power supply 24c and the ground power supply 24d made of the second aluminum film through the contact holes 22c and 22d, and the drain region is made of the first aluminum film 23. NAND circuit MP6
0 output λ is connected through contact holes 25f and 25g, respectively.

The transistor MP10 constituting the bit line balancing circuit 4 is formed in the diffusion layer forming region 17, and its gate electrode is composed of three polysilicon wirings 18,
Source and drain regions are connected to bit lines BLa and BLb through contact holes 19, respectively.

The dummy wiring region 9 and the dummy wiring region 10 are line-symmetrically configured by the same shape and the same number of polysilicon wirings as the bit line amplifier circuits 1, 2 and 3, and the bit line amplifier circuits 1, 2 and 3 are formed. The distance between them is also equal. In this embodiment, the polysilicon wiring in the dummy wiring region 9 has the same shape as the gate electrode of the bit line amplifier circuit 1, and the polysilicon wiring in the dummy wiring region 10 has the same shape as the gate electrode of the bit line amplifier circuit 3. Are all formed of polysilicon wiring in the same manufacturing process.

Next, the manufacturing process of this embodiment will be described. The surface of the semiconductor substrate is selectively oxidized to form the memory cell array region 6 and the diffusion layer forming regions 12, 20a, 20b, 20.
c, 20d, 17 etc. are divided. Next, a gate oxide film is formed in the diffusion layer forming regions 12, 20a, 20b, 20c, 20d, 17 and the like, and a polysilicon film having a thickness of 350 to 400 nm doped with phosphorus and boron is deposited.
Next, a positive photoresist film is deposited and the pattern on the photomask is transferred to the photoresist film. By this step, the gate electrodes 11a of the bit line amplifier circuits 1, 2, 3 are
11b, 11c, the gate electrode 21 of the bit line selection circuit 5
The dummy wiring regions 9 and 10 are simultaneously formed together with a, 21b and 21c, the gate electrode 18 of the bit line balancing circuit 4, and the like.

Gate electrodes 11a, 11b, 1 are formed by patterning the polysilicon film by plasma etching using the photoresist film having a predetermined pattern transferred as a mask.
1c, 21a, 21b, 21c, 18 and dummy wiring regions 9, 10 are formed.

FIG. 4 shows a wiring pattern of the polysilicon film formed in this same step. As shown in the figure, by providing the dummy wiring regions 9 and 10, the gate electrodes 11a and 11b are provided outside and inside the bit line amplifier circuits 1, 2 and 3 with the pattern of the gate electrodes 11a, 11b and 11c as the center. 30 and 40 patterns having the same shape as 11b are formed. With such a configuration, it can be formed in a pattern symmetrical with respect to a line (CL in FIG. 4) passing through the centers of the gate electrodes 11a, 11b, 11c.

Next, the gate electrodes 11a, 11b, 11
The diffusion layer forming regions 12, 17, 20a, 20b, 20c, 20 using c, 19, 21a, 21b, 21c as a mask.
Ions are implanted into d to form source and drain regions,
Transistors MP10, MP20, MP30, MP4
0, MP50, MP60 are formed.

After depositing an interlayer insulating film and forming a contact hole 17, a silicide layer 16 is deposited to form contact holes 13, 19 and 25, and then a first aluminum film is deposited to form a bit. The input / output 23 of the NAND circuit of the line selection circuit 5 and the bit lines BLa and BLb are formed. After that, contact holes 15 and 22 are formed and a second aluminum film is deposited to form the output of the bit line amplifier circuit and the ground power supply 14, the power supply of the bit line selection circuit and the ground power supply 24.

Through the above steps, the semiconductor memory device according to this embodiment is formed.

Referring to FIG. 5, the gate electrodes 11a-1 and 11b-1 at the right end of FIG. 4, that is, the chip electrodes 11a-1 and 11b-1 at the end are counted to the right, and the numbers of the gates 11a and 11b are counted on the horizontal axis. Gate width L of electrodes 11a and 11b
In the graph in which the vertical axis is taken as the vertical axis, the width L of the gate electrode of the transistor MP20 of the bit line amplifier circuit 3 obtained according to the present embodiment is shown by a black circle, and the width L of the gate electrode according to the conventional technique is shown by X. The width L of the gate electrode of the transistor MP40 of the line amplifier circuit 1 is shown as a white circle, and the width L of the gate electrode according to the conventional technique is shown as +. In this embodiment, the gate electrodes 11a and 11b are set to 0.8.
m μm (A in FIG. 5).

As is apparent from FIG. 5, the width of the gate electrode 11a of the conventional semiconductor memory device is about 0.06 μm above the design target value of 0.8 μm, and the width of 11b is about 0.06 μm. On the other hand, in the present embodiment, the difference between the two remains at 0.03 μm or less. As described above, the reason why it is possible to prevent the width of the gate electrode from deviating from the design target value by a large amount is that the formation pattern of the polysilicon layer of the gate electrodes 11a and 11b is set by the dummy wiring regions 9 and 10 as described above. This is because the above-mentioned unevenness does not occur in the diffraction of light during the mask pattern exposure for forming the polysilicon layer (see FIG. 4).

As described above, when the width of the gate electrode varies and, as a result, the channel length increases or decreases, the transconductance of the transistor varies.

To more quantitatively show the adverse effects of variations in the transconductance of the transistors, referring to FIG. 6 in which the horizontal axis represents time t and the vertical axis represents the potential of the bit line and the read output, When the transconductance of the transistor MP20 forming the bit line amplifier circuit decreases and the transconductance of the transistor MP40 increases, the output of the bit line amplifier circuit changes from the solid line (1) a to the dotted line (1) b, causing a delay. The delay from the solid line (2) a to the dotted line (2) b even when the read output rises in the semiconductor memory device (about 2 to 3 nse in the above conventional example).
c) is generated. These problems were solved by this embodiment.

In the above embodiment, the dummy wiring area 9
The wiring patterns 30 and 40 of 10 and 10 are described as the polysilicon wirings having the same shape as the polysilicon wiring patterns 11b and 11a of the gate electrode.
The values and shapes of the wiring widths and pitch widths of the wirings 40 and 40 do not have to be exactly the same as the wiring patterns 11b and 11a of the gate electrode, and it is sufficient if the above-mentioned symmetry is substantially maintained.

In addition to the variation in the width of the polysilicon wiring layers of the bit line amplifier circuits 1, 2 and 3 arranged in the peripheral portion of the memory chip, which is the object of the improvement of the first embodiment, these polysilicon wiring layers have different widths. The inventor of the present invention has observed that the width of the wiring varies at both ends of each wiring pattern. This second embodiment provides a solution to this problem.

More specifically, the variation of the width of the polysilicon wiring layer is not only generated above and below the bit line amplifier circuits 1, 2, and 3 as viewed from the memory cell array region, but also the bit line amplifier circuits 1, 2, and 3. Since the same can be seen at the end portions in the length direction of the polysilicon wiring pattern of No. 3, in order to deal with this, in the second embodiment, at both end portions of each of the bit line amplifier circuits 1, 2, and 3. A dummy wiring region 26 is provided (see FIG. 7). In the second embodiment, the constituent elements other than the dummy wiring region 26 are common to the first embodiment, and therefore, in FIG. 7, the constituent elements are indicated by common reference numerals and the description thereof is omitted. To do.

FIG. 8 is a plan view showing the bit line amplifier circuits 1, 2, 3, the bit line balancing circuit 4, the bit line selection circuit 5 and the dummy wiring regions 9, 10, 26 of the semiconductor memory device of FIG. .

The pattern configurations of the transistors MP20, MP30, MP40 constituting the bit line potential supply circuits 1, 2, 3 and the transistor MP10 constituting the bit line balancing circuit 4 and the dummy regions 9, 10 are the same as those in FIG. .

The dummy wiring region 26 has the same pattern as the pattern configuration of the gate electrodes 11a, 11b, 11c made of the polysilicon layers forming the bit line amplifying circuits 1, 2, 3. , 3 at both ends. As is clear from FIG. 9 in which only the polysilicon wiring pattern is taken out from this pattern configuration, the polysilicon layer 1 at the end portions of the circuits 1, 2 and 3 is shown.
1a-1, 11a-2, 11b-1, 11b-2, 11
Polysilicon wiring layers 27a-1, 27a-2, 27b-1, 27b- integrally with the patterns of c-1, 11c-2.
2, 27c-1 and 27c-2 are arranged. In the present embodiment, the dummy wiring region 26 has the polysilicon wirings 27a-1, 27b-1, 27c- of the two bit line amplifier circuits.
1, 27a-2, 27b-2, 27c-2.

As shown in the graph of FIG. 10 in which the physical quantities similar to those of FIG. 5 are plotted on the horizontal axis and the vertical axis on the same scale, the effect of the dummy wiring region 26 of the bit line amplifier circuits 1, 2, 3 according to the present embodiment is This is remarkable as compared with the case of the conventional technology (indicated by X). In this graph, the width of the gate electrode 8a is 0.8 mμm (A in FIG. 10) as in FIG.

As is apparent from FIG. 10, the width L of the polysilicon wiring is the second from the end of the pattern (the right end of the circuit pattern in FIG. 7), that is, the two wirings 27a-2, 27b in the dummy wiring region 26. Up to -2, the variation is large with respect to the design target value, but there is not much difference from the design target value in the third and subsequent polysilicon wirings, that is, the gate electrodes 11a-1 and 11b-1. Therefore, the present embodiment suppresses the variation in the width of the gate electrodes of the transistors forming the bit line amplifier circuits 1 and 2 and prevents the variation in the mutual conductance of the transistors.

In this embodiment, the dummy wiring region 26 is composed of the polysilicon wirings 27 of the two bit line amplifier circuits. However, if the number of the polysilicon wirings 27 is three or more, the widths of the gate electrodes 11a and 11b are increased. And the design target value are even smaller.

The dummy wiring areas 9 and 10 are also extended to the left side toward the dummy wiring area 26 in FIG.
Further, it is possible to suppress variations in design target values for the gate electrodes 11a and 11b.

Also in the present embodiment, as in the first embodiment, the wirings 27a and 27 forming the dummy wiring area 26 are formed.
The values of the wiring width, pitch width, etc. of b and 27c do not have to be exactly the same as those of the gate electrodes 11a, 11b and 11c, and these electrodes 11a, 11b and 11c and the dummy wiring region 27 are not necessary.
If the patterns of the wirings 27a, 27b, and 27c are substantially similar to each other and the values of the pitch width and the like are substantially the same, the above-described effect can be obtained.

Second Embodiment By implementing the second embodiment in combination with the first embodiment, the transistors in both the vertical and horizontal directions of FIG. 3 or FIG. 8 as viewed from the memory cell area of the bit line amplifier circuits 1, 2 and 3. It will be apparent to those skilled in the art that it becomes possible to eliminate the nonuniformity of the gate width and improve the effect of preventing a decrease in read speed and a malfunction.

Further, in the above-mentioned first and second embodiments, the case where the gate electrode of the transistor is made of polysilicon has been described, but the case where these gate electrodes are made of other materials such as aluminum is also used. It will be clear that the invention has similar applicability.

Further, the present invention is not limited to the SRAM constructed by the first and second embodiments, but may be a DRAM (dyna).
micRAM), mask ROM, PROM (progr
amable read only memory
y), EPROM (erasable PROM), EE
PROM (electrically erasable)
It will be apparent to those skilled in the art that it is equally applicable to ePROM), etc.

[0054]

As described above, the semiconductor memory device of the present invention can prevent variations in the mutual conductance of the transistors forming the peripheral circuit, and can prevent a decrease in the read operation of the semiconductor memory device and an error. It has become possible.

[Brief description of drawings]

FIG. 1 is a plan view schematically showing an entire semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific circuit configuration of the semiconductor memory device shown in FIG.

3 is a plan view schematically showing part of a wiring pattern of a bit line amplifier circuit, a bit line selection circuit, and a bit line balancing circuit of the semiconductor memory device shown in FIG.

FIG. 4 is a plan view showing a wiring pattern of only a polysilicon wiring layer of the wiring patterns shown in FIG.

FIG. 5 is a graph showing variations in gate width with respect to design target values in the semiconductor device according to the present embodiment and the prior art.

FIG. 6 is a waveform diagram showing a power supply level waveform and an output waveform of an output of a bit line amplifier circuit of a semiconductor memory device.

FIG. 7 is a plan view schematically showing an entire semiconductor memory device according to a second embodiment of the present invention.

8 is a plan view schematically showing part of a wiring pattern of a bit line amplifier circuit, a bit line selection circuit, and a bit line balancing circuit of the semiconductor memory device shown in FIG.

9 is a plan view showing a wiring pattern of only a polysilicon wiring layer among the wiring patterns shown in FIG. 7. FIG.

FIG. 10 is a graph showing variations in gate width with respect to a design target value in semiconductor memory devices according to the present embodiment and the prior art.

[Explanation of symbols]

 1, 2, 3 bit line amplifier circuit 4 bit line balancing circuit 5 bit line selection circuit 6 memory cell array area 7 row decoder 8 semiconductor chip 9, 10, 26 dummy wiring area

Claims (13)

[Claims] 1. A memory cell array region formed in a substantially rectangular shape on a surface of a semiconductor substrate, and a bit line amplifier circuit arranged adjacent to a predetermined side of the memory cell array region and having a first circuit layout pattern. A semiconductor memory device comprising: a first dummy region having the same shape layout pattern inside and outside the bit line amplifier circuit as viewed from the memory cell array region. 2. A both end portion of a bit line amplifier circuit having a memory cell array region formed in a substantially rectangular shape on a surface of a semiconductor substrate and a first circuit layout pattern arranged adjacent to a predetermined side of the memory cell array region. And a second dummy wiring region each having a circuit layout pattern substantially the same as the first circuit layout pattern. 3. The semiconductor memory device according to claim 1, wherein the first dummy region is provided in the same manufacturing process as a predetermined wiring of the bit line amplifier circuit. 4. The semiconductor memory device according to claim 2, wherein the second dummy region is provided in the same manufacturing process as the bit line amplifier circuit. 5. The semiconductor memory device according to claim 1, wherein the first dummy regions have substantially the same line-symmetrical shape centering on the first circuit layout pattern region. 6. The semiconductor memory device according to claim 2, wherein the first dummy area has a shape similar to that of the first circuit layout pattern area. 7. The first and second dummy regions are regions partitioned by a layer forming a gate of a transistor of a bit line amplifier circuit.
The semiconductor memory device described. 8. The semiconductor memory device according to claim 7, wherein the transistor forming the bit line amplification having the first circuit layout pattern is a MOS transistor. 9. The semiconductor memory device according to claim 1, wherein the memory cell forms an SRAM. 10. The semiconductor memory device according to claim 1, wherein the memory cell forms a DRAM. 11. The semiconductor memory device according to claim 1, wherein the memory cell constitutes an EPROM. 12. An EEPROM according to the memory cell
3. The semiconductor memory device according to claim 1, wherein the semiconductor memory device comprises: 13. The semiconductor memory device according to claim 1, wherein a CCD memory is formed by the memory cells.