JP2723678B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a structure in a memory cell array region of a static random access memory (hereinafter, referred to as SRAM).

[0002]

2. Description of the Related Art In general, a semiconductor memory device comprises a memory cell array region and a decoder circuit, a selection circuit and the like adjacent thereto. Among these components, the memory cell array region is particularly configured by regularly arranging memory cells. Therefore, the transistors (generally, MOS transistors) constituting the memory cell are regularly arranged in the memory cell array region.

FIG. 5 is a circuit diagram showing a configuration example of an SRAM in which a memory cell is formed by nMOS transistors. Memory cells S11, S12 ..., S21, S2
Are arranged in an array to form a memory cell array region. Each memory cell has a corresponding 1
Are connected to two word lines W1, W2,... And two digit lines D1, D2 forming a pair. Digit line D
A load circuit composed of transistors T1 and T2 and a balancing circuit composed of a transistor T3 and a signal φ are connected to 1, D2 to balance the potentials of these two lines to a constant potential. Further, a column selecting circuit T for selecting any of the paired digit line combinations.
4, T5,... Are provided, and a sense amplifier SAMP for amplifying the potential difference between the selected pair of digit lines is connected to the digit line group.

A memory cell (for example, S
1) is a flip-flop circuit in which input terminals and output terminals of two inverters (an inverter including a transistor M1 and a resistor R1 and an inverter including a transistor M2 and a resistor R2) are cross-coupled, and input and output of two flip-flops Output terminals C and D and digit line D
1 and D2, respectively, and has transfer gate transistors M3 and M4 whose gates are connected to the word line W1.

In such a semiconductor memory device, whether the data stored in one memory cell is 0 or 1 is determined by determining whether the potentials of nodes C and D in the memory cell are high potential and low potential, respectively. Or a combination of low and high potentials.

At the time of a read operation, a selected word line (eg, W1) is activated and transfer gate transistor M
3, M4 connect nodes C and D to digit lines D1 and D2. Either of the potentials of these two digit lines falls according to the state of the two contacts C and D in the memory cell, and a potential difference occurs between the two. This potential difference is applied to the sense amplifier SAM
P senses and amplifies and sends it to an output circuit (not shown).

At the time of a write operation, contrary to the read operation,
A potential difference corresponding to the write data is given to digit lines D1 and D2, and transfer gate transistors M3 and M4 are turned on to forcibly set the potential state in the memory cell.

FIG. 6 is a plan view showing a partial pattern of a memory cell array region of the semiconductor memory device shown in FIG. The same components as those in FIG. 5 are denoted by the same reference numerals. In the figure, a thin solid line indicates an active region defined by a field oxide film formed by selective oxidation, a hatched region indicates a polycrystalline silicon region above the active region, and a cross hatched region indicates a polycrystalline silicon region. And a direct contact region between the active region and the active region, and a thick solid line indicates an aluminum wiring layer further above the polycrystalline silicon region.

The transistor M1 is provided in the active region 1, and its gate electrode G1 is made of a polycrystalline silicon film.
The drain region d2 (node D) of the transistor M2 is connected by a direct contact 7 and its source region s
c1 is connected to the polysilicon line 11 by a direct contact 10, and its drain region d1 is a gate electrode G2 of a transistor M2 made of a polysilicon film.
(Node C) and the direct contact 8.

The transistor M2 is provided in the active region 2 and its source region scS2 has a direct contact 1
2 is connected to the polycrystalline silicon wiring 11 and connected to the ground line GND made of aluminum wiring by the contact hole 4.

The transistor M3 is provided in an active region 3a which is an extension of the active region 3, and its source / drain path is connected to a digit line D1 with a contact hole 5 (contact A) and a gate electrode G2 of the transistor M2. The gate electrode G3 is provided between the direct contact 9 (contact point C) and the intersection region between the word line W1 made of polycrystalline silicon wiring and the active region 3a.

The transistor M4 is an extension of the active region 2, and is provided in the active region 2a running parallel to the length direction of the active region 3a. A source / drain path of M4 is provided between a contact hole 6 (contact B) connected to the digit line D2 and a direct contact 7 (contact D) connected to the gate electrode G1 of the transistor M1;
Word line W1 made of polycrystalline silicon wiring and active region 2
The intersection region with a becomes the gate electrode G4.

Although load resistors R1 and R2 and power supply line Vcc are not shown in FIG. 6, both of them are formed in a memory cell array region by a polycrystalline silicon film of a layer different from a polycrystalline silicon film forming a transistor. Is formed.

One of the memory cells (S11) is constituted by the transistors M1 to M4 described above. FIG. 6 shows memory cells S12, S21, S2 having the same circuit configuration.
2 is also shown.

A power supply line Vcc for supplying power to the memory cells and a ground power supply line GN are provided in the memory cell array region.
D is drawn into the memory cell array region from a peripheral portion other than the memory cell array region, and is arranged between the memory cells. Generally, one power supply line is arranged for every 6 to 12 memory cells. FIG. 6 shows a portion where a ground power supply line GND made of an aluminum wiring layer above the active region or the polycrystalline silicon layer is arranged between the memory cells S11 and S21 and the memory cells S12 and S22.

By the way, a transistor constituting a memory cell is formed in an active region defined by a field oxide film formed by selective oxidation in an initial step in manufacturing.
Therefore, in a memory cell array region in which memory cells are arranged in an array, an active region for forming this transistor is mostly formed according to a regular pattern. For example, the transistors M1 and M2 shown in FIG.
A large number of active regions for forming M3 and M4 are formed in a memory cell array region according to a regular pattern. This will be described with reference to FIG.

FIG. 7 is a plan view showing only the active region in the memory cell array region wider than the region shown in FIG. A region 200 surrounded by a dotted line is the range shown in FIG. As described above, the transistor M2 is provided in the region 3a which is an extension of the active region 3, and the transistor M2
Reference numeral 4 denotes an extension of the active region 2, which is provided in a region 2a running parallel to the length direction of the region 3a. As is apparent from FIG. 7, the formation patterns of the active regions (2a and 3a) are regularly arranged at intervals GAP2 in the memory cell array region not particularly shown in FIG.

However, since the power supply lines are arranged in the memory cell array region, the arrangement regularity of the transistors around the region where these power supply lines are arranged is disturbed. That is, as shown in FIG. 6, since the ground power supply lines GND are arranged between the memory cells S11 and S21 and the memory cells S12 and S22, the regions 3a where the transistor M3 in each memory cell is formed are connected. Of the other active region (2a or 3)
a) It becomes wider than the gap GAP2 between the competitors (see also FIG. 7). Therefore, the formation pattern of active region 3a for forming this transistor is the same as that of ground power supply line G.
The regularity described above is disturbed in the adjacent part of the ND.

FIG. 8 is a sectional view taken along line XX of FIG. The field insulating film 3 on the surface of the P-type silicon substrate 32
The gate oxide film 30 is formed on the active region 3 defined by 1 and a word line W1 made of a polycrystalline silicon film is arranged thereon. The portion of the active region 3a becomes the gate electrode G3 of the transistor M3 (FIGS. 5 and 6).
D is the gate width of this transistor. Word line W1
A digit line D1 made of aluminum wiring and a ground power supply line GN are formed on the upper side thereof through an insulating layer 33 so as to be orthogonal to the same line.
D is arranged. Since a transistor cannot be formed in a lower layer portion where the ground power supply line GND is arranged, an active region is not formed and the field insulating film 3 is simply formed.
Only one exists. Therefore, the interval between the transistors M3 adjacent to the ground power supply line GND, that is, the interval GAP1 between the active regions 3a is different from the other active regions (2a or 3a).
a) The gap GAP2 is larger than the gap GAP2, and the regularity of the formation pattern of the active region 3a is disturbed at that portion.

[0020]

However, as described above, in the conventional semiconductor memory device, the pattern of the active region for forming the transistor forming the memory cell is disordered at the portion adjacent to the power supply wiring. ing. The active region in which the regularity of the formation pattern is disturbed has a much larger variation with respect to the design target value in dimensions than the other regularly formed active regions.

FIG. 9 shows an example of this variation. 8, the vertical axis represents the width of the active region 3a shown in FIG. 8, that is, the width W which is the gate width of the transistor M3 (FIGS. 5 and 6).
D, and the horizontal axis represents the distance L from the active region to the ground power supply line GND. GW is a design target value of the gate width. As is clear from FIG. 9, the difference (ΔW1) from the design target value GW increases as the width WD of the active region, which becomes the gate width of the transistor, approaches the ground power supply line GND. For example, if the design target value GW is 0.7 μm,
The maximum value of ΔW1 is 0.3 μm.

If the variation in the size of the active region, particularly the variation in the gate width of the transistor, is smaller than the design target value, there are the following problems. That is,
As shown in FIG. 10, the width WD is larger than the design target value GW by Δ.
When W1 becomes smaller, the drain current I of the transistor becomes Δ
I will be reduced. For example, the drain current of a transistor is 0.25
If the gate width is reduced by 0.3 μm as in the above example, the drain current at that time is reduced by 0.144 mA, which is about 40% of the drain current value at the design target value. % Of the current will flow. That is, the transistor performance is reduced.

As shown in FIG. 11, the decrease in transistor performance causes a delay in the potential change (1) of the digit line connected to the transistor (change from the solid line to the dotted line), and reduces the potential difference of the digit line. The output (2) of the sense amplifier to be amplified is delayed. As a result, the data output time (3) of the semiconductor memory device is delayed (about 5 ns).
c) In addition to significantly lowering the performance of the semiconductor memory device, it sometimes causes a malfunction.

It is considered that the dimensional variation of the active region, which causes the above-mentioned problems, occurs due to the following reasons.

In the active region, an oxide film is grown on the surface of the substrate by a thermal oxidation method, and a silicon nitride film is deposited thereon by a CVD method. After selectively removing the silicon nitride film by lithography, a field insulating film is formed by using the silicon nitride film of the active region left by the selective oxidation method as an oxidation resistant mask, and formed by peeling the silicon nitride film. Is done. That is, the size of the active region is determined by the size of the silicon nitride film selectively left by the lithography technique.

However, if the regularity of the formation pattern of the active region is disturbed in the vicinity of the power supply wiring, the lithography technique for selectively removing the silicon nitride film, that is, after applying a photoresist, When exposing with a predetermined mask pattern, the exposure condition changes in a portion where the regularity is disturbed due to a change in light interference. When the exposure condition changes, the dimension of the silicon nitride film that is selectively left largely varies from the design target value, and as a result, the dimension of the active region varies.

Accordingly, it is an object of the present invention to prevent a decrease in the performance of a transistor forming a memory cell and to prevent a decrease in the performance and malfunction of a semiconductor memory device.

[0028]

According to the semiconductor memory device of the present invention, a first active region in which one transistor forming a first memory cell is formed and one transistor forming a second memory cell are formed. A second active region, a wiring region provided above the region between the first and second active regions, and the first active region and the second active region below the wiring region. each said from the two active regions layer in the region becomes of the first active region and said second active region between the
Dummy regions are provided for suppressing dimensional variations in pattern width .

This dummy region has a similar shape to other active regions, and is formed by the same manufacturing process.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to the drawings.
In the present embodiment, as in FIG. 5, an SRAM in which a memory cell is configured by nMOS transistors will be described as an example. Therefore, the memory cells S11, S12, S21, S2
2 and the like are the same as those in FIG. 5, and the description of the configuration and circuit operation is omitted.

FIG. 1 is a plan view showing a partial pattern of a memory cell array region of a semiconductor memory device according to the present invention. 5 and 6 are denoted by the same reference numerals. FIG.
Have memory cells S11 having the same circuit configuration as in FIG.
Four S12, S21, and S22 are shown. The pattern configuration of each memory cell is exactly the same as in FIG.

The difference between this embodiment and the conventional example shown in FIG. 6 is not the pattern configuration of the area where the memory cells S11, S12, S21 and S22 are formed, but the ground power supply line GND in the memory cell array area. It is in the pattern configuration of the arranged area. In the present embodiment, the memory cell S11
And a memory cell S12, a ground power supply line GND is arranged. In this region, as described above, the interval between the transistors M3 in each memory cell is wider than the interval GP2 between the active regions (2a or 3a) where other transistors (M3 or M4) are formed. I have.

Therefore, in this embodiment, the transistor M
The dummy region 17 formed in the same step as the active region region 3a in which the
a. Thereby, as is clear from FIG. 2, the interval between the active region 3a and the dummy region 17 becomes equal to the interval GAP2 between the other active regions (2a or 3a). In order to prevent the dummy region 17 from being in a floating state, the contact 15
Dummy region 17 is connected to ground power supply line GND.

With such a configuration, the pattern of the active region for forming the transistor forming the memory cell is not disturbed in the regularity in the portion adjacent to the power supply wiring.

FIG. 3 is a sectional view taken along line XX of FIG. A gate oxide film 30 is formed on active region 3 partitioned by field insulating film 31, and a word line W1 made of a polycrystalline silicon film is arranged thereon. A digit line D1 made of aluminum wiring and a ground power supply line GND are formed on the word line W1 via an insulating layer 33 at right angles to the same line.
Is arranged. A dummy region 17 having a shape similar to that of the active region 3a is formed in a lower layer portion where the ground power supply line GND is arranged. As a result, the distance between the active region 3a and the dummy region 17 is changed to another active region (2a or 3a).
It is equal to the competitor's interval GAP2.

FIG. 4 shows the variation of the dimensions of the active region with respect to the design target value when the active region is formed in a regular pattern according to the present embodiment. As is clear from the figure,
The width WD of the active region, which is the gate width of the transistor, is
Even if it is close to the ground power supply line GND, the difference from the design target value GW does not increase at all. That is, it is possible to prevent a decrease in transistor performance in the memory cell array region.

With the configuration as in this embodiment,
Variations in the dimensions of the active region can be prevented. The reason is that the regularity of the formation pattern of the active region is not disturbed by the dummy region 17 even in the portion adjacent to the power supply wiring, so that the light interference changes during the mask pattern exposure for forming the active region. This is considered to be caused by the fact that the exposure condition does not change unlike the related art.

As described above, according to this embodiment, since the transistor performance of the transistor in the memory cell array region can be prevented from being lowered, the potential change of the digit line connected to the transistor is not delayed. Therefore, no delay occurs in the output of the sense amplifier that amplifies the potential difference of the digit line.

Therefore, it is possible to prevent the performance degradation and malfunction of the semiconductor memory device due to the delay of the data output time of the semiconductor memory device.

In the embodiment described above, the SRAM constituted by the nMOS is described as an example, but the present invention is not limited to this. For example, the S
RAM is also possible. In this case, the ground power supply line GND may be set to the power supply line Vcc in the wiring pattern shown in FIG.

Further, the present invention is not limited to an SRAM, but a memory including a memory cell array in which memory cells are arranged in an array, ie, a regular array, such as a DRAM (dynamic RAM) and a PROM (pROM).
programmableread only memo
ry), EPROM (erasable PROM),
EEPRO (electrically erasab
le PROM), a shift register, a CCD memory, and the like. Therefore, the circuit configuration and pattern configuration shown in FIGS. 1 and 5 are not limited to this.

In the above description, the term "active region" is used, but this simply means that a field insulating film is formed by a selective oxidation method and an element can be formed by the field oxide film. . In other words, this region is not necessarily implanted or diffused with impurities or the like. In the case of the present embodiment, after the dummy region 17 is formed by the selective oxidation method, like the other active regions,
After a polycrystalline silicon film for forming a gate electrode is formed, impurities are implanted by impurity implantation for forming source / drain regions. However, in the present invention,
It is also possible to prevent impurities from being implanted into the dummy region by devising a mask pattern, increasing the number of mask steps, and the like.

[0043]

As described above, in the semiconductor memory device of the present invention, the first active region in which one transistor forming the first memory cell is formed, and the one transistor forming the second memory cell are formed. Is formed in a lower layer of a power supply wiring region provided above a region between the first active region and the second active region where the first region is formed.
By providing a dummy region in the same layer as the two active regions in a region between the active region and the second active region, it is possible to prevent a decrease in transistor performance of the transistors in the memory cell array region. There is no delay in the potential change of the digit line
This has the effect that the output of the sense amplifier for amplifying the potential difference of the digit line is not delayed.

[Brief description of the drawings]

FIG. 1 is a plan view showing a partial pattern of a semiconductor memory device according to one embodiment of the present invention.

FIG. 2 is a plan view showing a pattern of a part of an active region of a memory cell array region of the semiconductor device according to one embodiment of the present invention;

FIG. 3 is a sectional view taken along line XX of FIG. 1;

FIG. 4 is a diagram showing a variation of a gate width with respect to a design target value in the semiconductor device of FIG. 1;

FIG. 5 is a circuit diagram illustrating an example of an SRAM.

6 is a plan view showing a partial pattern of a memory cell array region of the semiconductor memory device shown in FIG.

FIG. 7 is a plan view showing a pattern of a part of an active region of the memory cell array region of FIG. 5;

FIG. 8 is a sectional view taken along line XX of FIG. 6;

9 is a diagram showing a variation of a gate width with respect to a design target value in the semiconductor device of FIG. 6;

FIG. 10 is a diagram illustrating a relationship between a gate width and a drain current of a transistor.

FIG. 11 is a waveform diagram showing a digit level voltage waveform and an output waveform of a semiconductor memory device.

[Explanation of symbols]

 S11, S12, S21, S22 Memory cell M1, M2, M3, M4 Transistor W1, W2 Word line D1, D2 Digit line 1, 2, 2a, 3, 3a Active region 17 Dummy region GAP1, GAP2 Spacing between active regions

──────────────────────────────────────────────────の Continuation of the front page (51) Int.Cl. ⁶ Identification number Agency reference number FI Technical indication location H01L 27/108 H01L 29/76 301G 27/11 27/10 434 27/115 29/762 29/788 29/792

Claims (18)

(57) [Claims] A first active region in which one transistor forming a first memory cell is formed; a second active region in which one transistor forming a second memory cell is formed; a wiring region and provided on an upper layer of the region between the second active region, the said two active regions in a region between the lower layer in the first active region of the wiring region and the second active region The first active region and the second active region.
A semiconductor region provided with a dummy region for suppressing a dimensional variation of each pattern width of the conductive region . 2. An active region column forming region in which a plurality of active regions in which transistors forming a memory cell are formed are disposed in one direction, and the active region column forming region is disposed so as to be orthogonal to the direction of the active region column forming region. a wiring region where the upper layer wiring is formed, consists of the active region and the same layer in the lower layer of the wiring region in the intersection region between the active region columns forming region and the wiring region
Each pattern width of the first active region and the second active region
A semiconductor region provided with a dummy region for suppressing dimensional variation of the semiconductor memory device. 3. The device of claim 1, wherein the dummy region has a shape similar to the first and second active regions.
13. The semiconductor memory device according to claim 1. 4. The semiconductor memory device according to claim 1, wherein said dummy region is provided in the same manufacturing process as said first and second active regions. 5. The semiconductor memory device according to claim 1, wherein said dummy region is a region partitioned by a field oxide film formed by a selective oxidation method. 6. The transistor according to claim 1, wherein one transistor forming the first memory cell and one transistor forming the second memory cell are the same transistor in the circuit configuration of each memory cell. 13. The semiconductor memory device according to claim 1. 7. The semiconductor memory according to claim 1, wherein one transistor forming the first memory cell and one transistor forming the second memory cell are of the same type. apparatus. 8. The semiconductor memory device according to claim 6, wherein one transistor forming the first memory cell and one transistor forming the second memory cell are MOS transistors. 9. The semiconductor device according to claim 2, wherein a distance between the dummy region and the active region adjacent to the dummy region is equal to a distance between a plurality of active regions constituting another active region column forming region. Semiconductor storage device. 10. The semiconductor memory device according to claim 2, wherein said wiring is a power supply wiring. 11. A semiconductor device comprising: a memory cell array region in which a plurality of memory cells are arranged in an array; and a word line connected to the plurality of memory cells and two digit lines forming a pair. Item 3. The semiconductor memory device according to item 1 or 2. 12. The memory cell includes a flip-flop circuit in which two inverters are cross-coupled, and two data input / output transfer gate transistors whose gates are connected to a word line. 3. The semiconductor memory device according to claim 1, wherein: 13. The semiconductor memory device according to claim 1, wherein said memory cell forms an SRAM. 14. The semiconductor memory device according to claim 1, wherein said memory cells constitute a DRAM. 15. The semiconductor memory device according to claim 1, wherein said memory cell forms an EPROM. 16. An EEPROM using the memory cells.
3. The semiconductor memory device according to claim 1, wherein 17. The semiconductor memory device according to claim 1, wherein a shift register is constituted by said memory cells. 18. The semiconductor memory device according to claim 1, wherein said memory cell constitutes a CCD memory.