JPH06252355A - Semiconductor device - Google Patents

Abstract

(57) [Summary] [Object] To realize a semiconductor device having high resistance to a surge input such as static electricity from the outside in a complementary MOS semiconductor device. [Structure] An excessive input such as static electricity from the outside is efficiently escaped by a diode arranged under a pad electrode so that it is not directly applied to an internal circuit. Pad electrode 1
P or N of the PN junction diode arranged under 16
The impurity concentration of the high-concentration diffusion layer 112 is set higher than that of the high-concentration diffusion layer in another region on the same substrate. In addition, the P or N-type high-concentration diffusion layer is in contact with the lower surface,
Alternatively, a P-type high concentration diffusion layer is provided. Further, two diodes are arranged under the pad electrode and connected to the positive and negative power supplies, respectively. [Effect] In particular, it has a low-concentration region such as an LDD structure and can protect an output terminal in which the drain of a miniaturized transistor having a low surge resistance is directly connected to a pad.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a complementary MOS semiconductor device having an integrated circuit in which MOS transistors of different conductivity type are formed on the same substrate, so that the internal circuit is protected from surge input such as excessive static electricity from the outside. Concerning the structure for protection.

[0002]

2. Description of the Related Art In a conventional semiconductor device, as a protection against an external surge input such as static electricity, a diffusion resistance, a poly.
A protection circuit was constructed by combining various resistors such as silicon, diodes, transistors, etc. to protect them.

[0003]

In recent years, miniaturization of transistors has been progressing, and as a transistor structure, as a countermeasure against hot carriers, for example, an LDD in which a low concentration diffusion layer is provided at a gate end of a drain diffusion layer is used. (Lightly
The Doped Drain structure and the double diffusion structure in which a low concentration region is provided by utilizing the difference in diffusion coefficient between arsenic and phosphorus have been positively adopted from a transistor channel length of 2 μm or less. In this way, as transistor miniaturization progresses and a drain structure with a low-concentration region becomes available, the breakdown strength against the surge input of the transistor itself becomes significantly weaker with the decrease in channel length. The protection effect against is becoming insufficient. Especially for the output terminal where the drain of the transistor is directly connected to the bonding pad, the surge withstand capacity of the transistor itself becomes the surge withstand capacity of the output terminal, so it is greatly affected by the decrease in the surge withstand capacity of the transistor due to miniaturization of the transistor. It has the problem of being lost.
Therefore, the present invention solves such a problem, and an object of the present invention is to provide a complementary MOS semiconductor device having a sufficient protection effect even if a transistor is miniaturized.

[0004]

The present invention provides a second region formed on a well region having a first conductivity type on a semiconductor substrate.
Conductive type MOS transistor and the second on the same substrate
A complementary MOS semiconductor device having a first-conductivity-type MOS transistor formed on a well region having a second-conductivity-type, connected to a power supply for supplying a second-conductivity-type charge carrier, A first conductivity type well region and a second conductivity type high-concentration diffusion layer formed on the well region, located under the bonding pad region, and connected to the bonding pad electrode. A second-conductivity-type high-concentration diffusion layer which has a diode and has the impurity concentration of the second-conductivity-type high-concentration diffusion layer formed on the same substrate and included in active elements other than the diode. Is higher than the impurity concentration of.

Further, the present invention is characterized by including the step of forming the second conductivity type high-concentration diffusion layer in the same pattern as the pad opening.

Further, according to the present invention, a well region of the first conductivity type, which is connected to a power supply for supplying charge carriers of the second conductivity type, and a lower portion of the bonding pad region formed on the well region are formed. A diode consisting of a second conductivity type high-concentration diffusion layer connected to the bonding pad region, the first diode being formed on the lower surface of the second conductivity type high-concentration diffusion layer. It is characterized in that the conductive type high concentration diffusion layers are in contact with each other.

According to the present invention, the impurity concentration of the first conductivity type high concentration diffusion layer is higher than the impurity concentration of the first conductivity type high concentration diffusion layer included in the active element other than the diode. It is characterized by

The present invention also includes the step of forming a first conductive type high concentration diffusion layer in contact with the lower surface of the second conductive type high concentration diffusion layer in the same pattern as the pad opening. It is characterized by

Further, according to the present invention, a diode having a first conductivity type well region and a second conductivity type high-concentration diffusion layer formed on the well region, and a second conductivity type well are provided. Region and a diode including a first-conductivity-type high-concentration diffusion layer formed on the well region, the second-conductivity-type high-concentration diffusion layer, and the first-conductivity-type diode. A high-concentration diffusion layer of the second conductivity type are both connected to the bonding pad electrode, and the well region of the first conductivity type is connected to a power supply supplying charge carriers of the second conductivity type, and The second conductivity type well region is connected to a power supply for supplying the first conductivity type charge carriers, and the second conductivity type high concentration diffusion layer and the first conductivity type high concentration diffusion layer are provided. And are located under the bonding pad electrode area. .

Further, the present invention has a diode comprising a well region of a first conductivity type and a high-concentration diffusion layer of a second conductivity type formed on the well region, and the second region. Conductive type high-concentration diffusion layer is located below the bonding pad electrode region, and the second conductive type high-concentration diffusion layer is connected to the bonding pad electrode, and the first conductive type high-concentration diffusion layer is connected to the bonding pad electrode. A first-conductivity-type high-concentration diffusion layer formed on the conductivity-type well region is located opposite one or more sides of the second-conductivity-type high-concentration diffusion layer, and
The high-concentration diffusion layer of the first conductivity type is connected to a power supply for supplying charge carriers of the second conductivity type.

Further, according to the present invention, the contact hole connecting the bonding pad electrode and the high concentration diffusion layer is
It is characterized in that it is in the bonding pad electrode region and is not in the bonding pad opening.

[0012]

1 is a plan view showing a first embodiment of the present invention, and FIGS. 2 (a) to 2 (d) are sectional views showing the main manufacturing steps of the first embodiment of the present invention. . The cross section of AA 'in FIG. 1 corresponds to FIG. 2 (d).

A first embodiment will be described below with reference to FIGS. 1 and 2A to 2D.

In FIG. 1, 104 is a gate electrode of an N-channel transistor, 107 is a source electrode, and 108 is a drain electrode.

Reference numeral 109 is an N-type high-concentration diffusion layer of an electrostatic protection diode located under the pad region according to the present invention. Since an excessive input current from the outside flows through this region, it is desirable to have a large area as much as possible. .

Reference numeral 110 is a P-type well connection region, and since an excessive input from the outside flows, it is desirable to arrange it as large as possible in the vicinity of the N-type diffusion layer 109.

Reference numeral 112 is an N-type high-concentration diffusion layer having a higher impurity concentration than the other regions of the electrostatic protection diode located under the pad region according to the present invention, 114 is a contact hole, and 115 is a wiring electrode. Yes, 116 is a pad electrode, and 120 is a pad opening.

Next, the first embodiment shown in FIG. 1 will be described in more detail with reference to FIGS. 2A to 2D together with the manufacturing method.

(FIG. 2A) First, the P-type well region 102 is formed on the P-type silicon substrate 101. For example, the P-type well is formed by implanting 2 × 10 ¹² cm ⁻² ions of boron. Next, an element isolation film 103 is formed by a LOCOS (local oxidation of silicon) method, and then a gate oxide film is formed by a thermal oxidation method to form a gate electrode 104 of the N-channel transistor.

Next, in order to form the lightly doped drain region 105 of the LDD structure of the N-channel transistor, for example, arsenic is ion-implanted at 1 × 10 ¹⁴ cm ^-2 at an energy of 40 keV.

Next, simultaneously with the source and drain regions of the transistor, a high concentration diffusion region of the electrostatic protection diode located below the pad region is formed.

First, for example, silicon dioxide is deposited by a chemical vapor deposition (hereinafter referred to as CVD) method and etched back to form a sidewall spacer 106 on the sidewall of the gate electrode 104.

Thereafter, for example, phosphorus is ion-implanted at a dose of 4 × 10 ¹⁵ cm ^-2 with an energy of 60 keV into the N-channel transistor region and the electrostatic protection diode region under the pad according to the present invention, to form an N-channel transistor. A source region 107 and a drain region 108 of a transistor and an N-type high concentration diffusion region 109 of an electrostatic protection diode are formed.

Next, for example, 40 keV of boron is selectively applied to the P-type well connection region 110 of the electrostatic protection diode.
5 × 10 ¹⁵ cm ^-2 ions are implanted with the energy of. At this time, the P-type well connection region 110 needs to be formed at a position facing at least one side of the N-type high-concentration diffusion region 109 of the electrostatic protection diode, and may be formed so as to surround it, as shown in FIG. desirable.

(FIG. 2 (b)) Next, the impurity concentration of the N-type high-concentration diffusion layer of the electrostatic protection diode according to the present invention is made higher than that of the high-concentration diffusion layer of the other region. Therefore, first, the photoresist 111 is formed in the same pattern as the pad opening by photolithography using the same photomask as the pad opening.

After that, for example, phosphorus is ion-implanted at a dose of 1 × 10 ¹⁶ cm ^-2 at an energy of 70 KeV to form an N-type high-concentration diffusion layer 112 in the pad region according to the gist of the present invention.

(FIG. 2C) Next, after removing the photoresist, 5000 Å of silicon dioxide is formed as the field insulating film 113 by, for example, the CVD method.

Next, a contact hole 114 for connecting the high-concentration diffusion layer and the wiring layer is opened. At this time, the pad electrode and the N-type high-concentration diffusion layers 109 and 11 are formed for the purpose of the present invention.
The contact hole 114 connecting to 2 needs to be located outside the pad opening.

After that, as the wiring electrode 115 and the pad electrode 116, for example, aluminum is formed by a 1 μm sputtering method. At this time, the P-type well connection region 11
Must be wired so that 0 is connected to the negative power supply. As a result, when a normal input is applied to the pad electrode,
The diode composed of the N-type high-concentration diffusion layer 112 and the P-type well region 102 becomes a voltage in the opposite direction and is insulated, and a breakdown current flows in the diode only when an excessive input is applied.

Next, as the passivation film 117, for example, silicon nitride is formed to a thickness of 1.2 μm by the CVD method.

(FIG. 2D) Finally, the passivation film 117 is etched by plasma of carbon tetrafluoride to form the pad opening 118.

The above is the first embodiment of the present invention.

As described above, by connecting the electrostatic protection diode to the pad electrode as in this embodiment, the diode is reverse biased against normal input from the outside and is insulated. An excessive input such as static electricity can be absorbed by the reverse breakdown current of the diode to protect the internal circuit.

Further, by setting the impurity concentration of the N-type high concentration diffusion layer 112 of the diode higher than that of other N-type high concentration diffusion layers, the breakdown voltage of the diode is lower than the breakdown voltage of the PN junction of the internal circuit. Therefore, an excessive input from the outside is absorbed by the diode, and a voltage higher than the breakdown voltage is not applied to the internal high impedance circuit.

Reverse breakdown voltage of a PN junction diode composed of a P-type well region and an N-type high-concentration diffusion layer, phosphorus ion implantation amount in the N-type high-concentration diffusion layer, and boron ion implantation amount in the P-type well region. Is shown in the graph of FIG.
In this embodiment, the implantation amount of the P well region 102 is 2 ×.
Since the ion implantation amount of the N-type high-concentration diffusion layer 112 is 10 × ¹² cm ⁻² , the breakdown voltage is about 10.5 V because the ion implantation amount is 1 × 10 ¹⁶ cm ⁻² . In addition, the source region 10 of the N-channel transistor
7, the ion implantation amount of the drain region 108 is 4 × 10 ¹⁵ c
m ⁻² , its breakdown voltage is about 12.8 V,
10.5 even if there is an excessive input such as static electricity from the outside
Since a voltage higher than V is not applied to the internal circuit, it is not destroyed.

Further, by disposing the diode under the pad electrode, a diode having a large area, that is, high absorption efficiency for excessive input can be formed without increasing the element area.

Since the P-type region 110 connected to the negative power source is arranged near the N-type high-concentration diffusion layer 112 of the diode, the excessive input current absorbed by the diode is transferred to the internal circuit. You can escape to the power line without reaching.

Further, since the contact hole connecting the pad electrode 116 and the N-type high-concentration diffusion layer 109 is formed outside the pad opening, the surface of the pad electrode is completely flat and wire bonding is performed. It does not deteriorate the adhesion of the wire.

Further, since the N-type high-concentration diffusion layer 112 of the diode can be formed by using the same photomask as the pad opening, the present invention can be implemented without increasing the number of photomasks.

Next, a second embodiment of the present invention will be described.

4 (a) to 4 (c) are sectional views of the main manufacturing steps showing the second embodiment of the present invention.

The second embodiment will be described below with reference to FIGS. 4 (a) to 4 (c).

(FIG. 4A) First, the P-type well region 20 is formed on the P-type silicon substrate in the same manner as in the first embodiment.
1. Device isolation film 203, gate electrode 204, lightly doped drain region 205 of LDD structure, gate / sidewall spacer 206, source region 207, drain region 20
8. N-type high concentration diffusion region 20 of electrostatic protection diode
9. P-type well connection region 21 of electrostatic protection diode
0, photoresist with the same pattern as the pad opening 2
11 is formed.

(FIG. 4 (b)) After that, for example, boron is ion-implanted at an energy of 200 KeV at 1 × 10 ¹⁵ cm ⁻² to form a P-type high-concentration diffusion layer 212 under the pad region according to the gist of the present invention. .

At this time, the P-type high-concentration diffusion layer 212 must be formed so as to be embedded in the boundary portion between the P-type well region 201 and the N-type high-concentration diffusion region 209.

Next, the field insulating film 113 is formed as in the first embodiment.

(FIG. 4C) Next, the wiring electrode 215, the pad electrode 216, and the passivation film 217 are formed in the same manner as in the first embodiment.

The above is the second embodiment of the present invention.

As in the present embodiment, the electrostatic protection diode formed of the N-type high-concentration diffusion layer 209 and the P-type high-concentration diffusion layer 212 connected to the pad electrode is formed under the pad region. The reverse breakdown voltage of the diode was about 7.8V. Therefore, even if there is an excessive input from the outside, a voltage of 7.8 V or higher is not applied to the internal circuit, and the internal circuit is not destroyed.

Next, a third embodiment of the present invention will be described.

FIG. 5 is a plan view showing a third embodiment of the present invention, and FIGS. 6A to 6D are sectional views showing main manufacturing steps showing the third embodiment of the present invention. BB 'in FIG.
The cross section corresponds to FIG. 6 (d).

The third embodiment will be described below with reference to FIGS. 5 and 6A to 6D.

In FIG. 5, reference numeral 303 is an N-type well region, and all other portions are P-type well regions. 305
Is a gate electrode of the N-channel transistor, and 30
Reference numeral 9 is a source electrode, and 310 is a drain electrode.

Reference numeral 311 denotes an N-type high-concentration diffusion layer of an electrostatic protection diode located below the pad region according to the gist of the present invention. Since an excessive input current from the outside flows through this region, it is desirable to have a large area as much as possible. . 313
Is a P-type well connection region of the electrostatic protection diode, and since an excessive input current from the outside flows in this region,
It is desirable to dispose a large area as close to the N-type high concentration diffusion layer 311.

Reference numeral 314 denotes a P-type high-concentration diffusion layer of the other electrostatic protection diode located below the pad region according to the gist of the present invention. Since an excessive input current from the outside flows in this region, the area is as large as possible. It is desirable to do. Reference numeral 312 denotes an N-type well connection region of the electrostatic protection diode, and since an excessive input current from the outside flows through this region, it is desirable to arrange it in a large area near the P-type high concentration diffusion layer 314.

Reference numeral 317 is a contact hole, and 318
Is a wiring electrode, 319 is a pad electrode, 321
Is a pad opening.

Next, the third embodiment shown in FIG. 5 will be described in more detail together with the manufacturing method according to FIGS. 6 (a) to 6 (d).

(FIG. 6A) First, a P-type well region 302 and an N-type well region 3 are formed on a P-type silicon substrate 301.
Form 03. For example, 2x boron in a P-type well
10 ¹² cm ^-2 , 1 × 10 ¹² cm ^-2 phosphorus in N-type well
It is formed by ion implantation.

Next, LOCOS (local oxidation of silicon)
After forming the element isolation film 304 by the method, a gate oxide film is formed by the thermal oxidation method, and the gate electrode 305 of the N-channel transistor is formed.

Next, in order to form the lightly doped drain region 306 of the LDD structure of the N-channel transistor, for example, arsenic is ion-implanted at an energy of 40 keV at 1 × 10 ¹⁴ cm ^-2 .

(FIG. 6B) Next, at the same time as the source and drain regions of the transistor, an electrostatic protection diode (hereinafter referred to as diode A) on the P-type well region located under the pad region according to the gist of the present invention. ) And an electrostatic protection diode (hereinafter referred to as diode B) on the N-type well region.

First, a side wall spacer 307 is formed on the side wall of the gate electrode 305 by depositing, for example, silicon dioxide by a chemical vapor deposition (hereinafter referred to as CVD) method and etching back.

Then, the N-channel transistor region,
A region other than the diode A region and the N-type well connection region is covered with a photoresist 308, and, for example, phosphorus is ion-implanted at an energy of 60 keV at 4 × 10 ¹⁵ cm ⁻² to form a source region 309 and a drain region of the N-channel transistor. 310, N-type high-concentration diffusion region 311 of diode A, N
A mold well connection region 312 is formed. Furthermore, for example, phosphorus of 60 k is selectively applied only to the N-type high concentration diffusion region 311.
Implant 4 × 10 ¹⁵ cm ⁻² ions with energy of eV.

(FIG. 6C) Next, the P-type well connection region 313 and the P-type high concentration diffusion region 314 of the diode B are formed.
The others are covered with a photoresist 315, and, for example, boron is ion-implanted at an energy of 40 keV at 5 × 10 ¹⁵ cm ⁻² . Furthermore, only in the P-type high-concentration diffusion region 314, for example, boron is used at an energy of 40 keV in an amount of 5 × 1.
0 ¹⁵ cm ^-2 ion implantation is performed.

(FIG. 6 (d)) Next, after removing the photoresist, silicon dioxide is formed as the field insulating film 316 by a CVD method, for example, 5000 Å.

Next, a contact hole for connecting the high-concentration diffusion layer and the wiring layer is opened. At this time, for the purpose of the present invention, the contact hole 317 connecting the pad electrode to the N-type high-concentration diffusion layer 311 and the P-type high-concentration diffusion layer 312 is
It must be located outside the pad opening. afterwards,
As the wiring electrode 318 and the pad electrode 319, for example, aluminum is formed by a 1 μm sputtering method.

At this time, it is necessary to wire so that the N-type well connection region 312 is connected to the positive power supply and the P-type well connection region 312 is connected to the negative power supply.

Next, as the passivation film 320, for example, silicon nitride is formed to a thickness of 1.2 μm by the CVD method,
A pad opening 321 is formed.

The above is the third embodiment of the present invention.

By providing the diode connected to the positive power source and the diode connected to the negative power source as in the present embodiment, no matter whether the polarity of the excessive input such as static electricity from the outside is positive or negative, The circuit can be protected.

Further, since both of the two diodes are arranged under the pad electrode, the area does not increase.

In addition to the present embodiment, the impurity concentration of the N-type high-concentration diffusion layer 311 and the P-type high-concentration diffusion layer 314 is further increased, and the P-type high-concentration diffusion layer 311 is formed on the lower surface thereof. It is needless to say that the electrostatic protection effect can be further enhanced by providing the diffusion layer in contact with the P type high concentration diffusion layer 314 or by providing the N type high concentration diffusion layer in contact with the lower surface of the P type high concentration diffusion layer 314.

[0073]

As described above, according to the present invention, an excessive input such as static electricity from the outside can be efficiently escaped from the diode provided under the pad electrode.
There is an effect that a semiconductor device having high resistance against excessive input can be realized without increasing the area.

[Brief description of drawings]

FIG. 1 is a plan view showing a first embodiment of a semiconductor device of the present invention.

FIG. 2 is a sectional view showing main steps in a method of manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 3 is a graph showing the relationship between the impurity concentration of the N-type high concentration diffusion layer and the reverse breakdown voltage in the first example of the semiconductor device of the present invention.

FIG. 4 is a plan view showing a second embodiment of the semiconductor device of the present invention.

FIG. 5 is a plan view showing a third embodiment of the semiconductor device of the present invention.

6A and 6B are cross-sectional views showing main steps in a method of manufacturing a semiconductor device according to a third embodiment of the present invention.

[Explanation of symbols]

101 P-type silicon substrate 102 P-type well region 103 Element isolation film 104 Gate electrode 105 Low-concentration drain region 106 Sidewall spacer 107 Source region 108 Drain region 109 N-type high-concentration diffusion region of electrostatic protection diode 110 P-type well connection region 111 photoresist 112 N-type high-concentration diffusion layer in the pad region 113 field insulation film 114 contact hole 115 wiring electrode 116 pad electrode 117 passivation film 118 pad opening 201 P-type silicon substrate 202 P-type well region 203 Element isolation film 204 Gate electrode 205 Low-concentration drain region 206 Sidewall spacer 207 Source region 208 Drain region 209 N-type high-concentration diffusion region of electrostatic protection diode 10 P-type well connection region 211 Photoresist 212 P-type high concentration diffusion layer 213 field insulating film 214 contact hole 215 wiring electrode 216 pad electrode 217 passivation film 218 pad opening 301 P-type silicon substrate according to the gist of the present invention 302 P-type well region 303 N-type well region 304 Element isolation film 305 Gate electrode 306 Low-concentration drain region 307 Sidewall spacer 308 Photoresist 309 Source region 310 Drain region 311 N-type high-concentration diffusion region 312 N of electrostatic protection diode A Type well connection region 313 P type well connection region 314 P type high concentration diffusion region of electrostatic protection diode B 315 photoresist 316 field insulating film 317 contact hole 318 Line electrode 319 Pad electrode 320 Passivation film 321 Pad opening

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁵ Identification number Internal reference number for FI Technical indication H01L 29/784 9170-4M H01L 27/06 311 B 9054-4M 29/78 301 K

Claims (7)

[Claims] 1. A semiconductor device having a transistor formed on a semiconductor substrate of a first conductivity type, wherein a transistor of a second conductivity type located below a bonding pad region and connected to a bonding pad electrode. A second conductivity type included in an active element other than the diode, which has a diode formed of a concentration diffusion layer and in which the impurity concentration of the high-concentration diffusion layer of the second conductivity type is formed on the same substrate. The semiconductor device is characterized by having a higher impurity concentration than the high-concentration diffusion layer of. 2. The semiconductor device according to claim 1, wherein the second-conductivity-type high-concentration diffusion layer is formed in the same pattern as the pad opening. 3. A semiconductor device having a transistor formed on a semiconductor substrate of a first conductivity type, wherein a transistor of a second conductivity type located below a bonding pad region and connected to a bonding pad electrode. A diffusion layer of a first conductivity type, wherein a diffusion layer of a first conductivity type is provided in contact with a lower surface of the high-concentration diffusion layer of the second conductivity type; A semiconductor device, wherein an impurity concentration of the layer is higher than an impurity concentration of a first conductivity type diffusion layer included in an active element other than the diode. 4. The diffusion layer of the first conductivity type, which is in contact with the lower surface of the high-concentration diffusion layer of the second conductivity type, is formed in the same pattern as the pad opening. Item 3. The semiconductor device according to item 3. 5. A MOS transistor of a second conductivity type formed on a well region having a first conductivity type on a semiconductor substrate, and a well region having a second conductivity type on the same substrate. In a complementary MOS semiconductor device having a formed first conductivity type MOS transistor, a well region of a first conductivity type and a high concentration of a second conductivity type formed on the well region are formed. A diode formed of a diffusion layer, a well region of a second conductivity type, and a diode of a high-concentration diffusion layer of a first conductivity type formed on the well region; Both the conductive type high-concentration diffusion layer and the first conductive type high-concentration diffusion layer are connected to a bonding pad electrode, and the second conductive type high-concentration diffusion layer and the first conductive type high-concentration diffusion layer are connected to the bonding pad electrode. The conductive type high-concentration diffusion layer is Located below the dead electrode region, and the impurity concentration of one or both of the second-conductivity-type high-concentration diffusion layer and the first-conductivity-type high-concentration diffusion layer is
The high-concentration diffusion layer forming an active element formed in another region is formed to have a higher impurity concentration of the same conductivity type, and the well region of the first conductivity type has a second conductivity type charge. A semiconductor device, wherein the semiconductor device is connected to a power supply for supplying a carrier, and the well region of the second conductivity type is connected to a power supply for supplying a charge carrier of the first conductivity type. 6. A diode comprising a semiconductor substrate region of a first conductivity type and a high-concentration diffusion layer of a second conductivity type formed on the semiconductor substrate region, and the second conductivity type semiconductor device. A high-concentration diffusion layer of the second conductivity type is located below the bonding pad electrode region, the high-concentration diffusion layer of the second conductivity type is connected to the bonding pad electrode, and the first conductivity type is Formed on the well region of
The first conductivity type high-concentration diffusion layer is located opposite one or more sides of the second conductivity type high-concentration diffusion layer, and the first conductivity-type high concentration diffusion layer is 6. The semiconductor device according to claim 1, wherein the semiconductor device is connected to a power supply that supplies second-conductivity-type charge carriers. 7. The contact hole connecting the bonding pad electrode and the high-concentration diffusion layer is a bonding hole.
7. The semiconductor device according to claim 1, wherein the semiconductor device is in the pad electrode region and not in the opening of the bonding pad.