JPH05102475A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To heighten an ESD breakdown voltage by adopting on LDD structure for an MOS transistor and the single diffusion layer structure for protective diodes in an input/output unit. CONSTITUTION:Between an input pad 18 and an inverter 12 in an input line 10, connected are a PMOS transistor 20 and an NMOS transistor 22 for input protection, a protective resistor 24 in serial and protective diodes 26 and 28. The input protective MOS transistors 20 and 22 are of LDD structure; constrarily, the protective diodes 26 and 28 are of single diffusion layer structure.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a MOS type input / output cell and a method of manufacturing the same.

[0002]

Various types of protection circuits for input / output cells have been proposed. For example, (a) the functions of circuits other than the protection circuit are increased by increasing the substrate concentration only in the portion where the protection resistor, the capacitor, and the diode are formed, decreasing the reverse breakdown voltage of the diode, and increasing the capacitance value of the capacitor. The protective function is strengthened without lowering (see Japanese Patent Publication No. 62-37547). (B) By making the source of the gate control diode for protection the same conductivity type as the substrate, the resistance of the current path (drain → substrate → source →) after breakdown of the drain is reduced, and the drain-substrate- It prevents the P-N-P transistor action by the source and exhibits an excellent protection function (see Japanese Patent Publication No. 62-37550).

(C) By inserting a resistor between the P well in which the protective resistance is formed by the N type diffusion layer and the low voltage power supply Vss, surge Vss → P well → N
The current flowing in the path from the mold resistance layer to the pad is limited to eliminate the adverse effects such as burnout and PN junction destruction due to a large current (see Japanese Patent Publication No. 62-33752). By the way, as miniaturization of devices progresses, in order to prevent deterioration of transistor characteristics due to hot carriers, the drain has an LDD (Lightly Doped Drain) structure. In the LDD structure, the MOS transistor in the input / output section also has the LDD structure. In the protection transistor of the LDD structure, the breakdown voltage of the junction is increased and the low breakdown voltage drain portion has a high resistance, so that the ESD breakdown voltage is significantly reduced. Therefore, in order to avoid such a problem, only the protection transistor of the input / output cell needs to have the single diffusion layer structure.

[0004]

If the protection transistor of the input / output cell has a single diffusion layer structure, and if this MOS transistor is used as an output transistor, the gate characteristics are prevented in order to prevent deterioration of transistor characteristics due to hot carriers. It becomes necessary to make the length not to cause deterioration, for example, 2.0 μm or more. If the gate length is increased, the gm of the output transistor will be significantly reduced, making it difficult to operate at high speed. In addition, since the input / output section and the internal MOS transistor must be made separately, the photoengraving process will increase at least once. , The manufacturing process becomes complicated.

LDD for the MOS transistor of the input / output cell
In the case of the structure, it is necessary to additionally attach a protection diode in order to improve the ESD withstand voltage. However, when the element isolation oxide film is formed by a selective oxidation method such as a conventional LOCOS method or a framed LOCOS method for improving the degree of integration, the element isolation oxide film rises from the substrate surface and LDD
When the sidewall spacer is formed for the structure, the diffusion region of the diode also becomes a double diffusion structure that is very similar to the LDD structure. FIG. 6 shows a protection diode manufactured by a conventional method. In the region of the substrate 1 surrounded by the isolation oxide film 2, a low concentration diffusion layer 4 is provided outside the high concentration diffusion layer 3. A diffusion layer very similar to the LDD structure is formed and becomes a diode. Reference numeral 5 is a sidewall spacer formed for manufacturing the LDD structure.
However, in such a diode, the effect of improving the ESD hardly appears. Therefore, in order to prevent the protection diode from having a double-diffused structure, at least one photolithography process should be performed.
Since it is necessary to increase the number of times to form the protection diode, the manufacturing process becomes complicated. Further, the area of the input / output cell is increased, which is against the demand for miniaturization.

According to the present invention, while the MOS transistor in the input / output section has an LDD structure similar to that of the internal circuit, and even if the protection diode is formed in a normal manufacturing process, the protection diode has a single diffusion layer structure, the ESD withstand voltage is increased. It is an object of the present invention to provide a semiconductor device having an input / output cell with improved power consumption. The present invention also provides a method of manufacturing such a semiconductor device.

[0007]

The semiconductor device of the present invention comprises:
LD as input protection transistor or output transistor
An I / O cell having a D-structure MOS transistor and a protection diode having a single diffusion layer structure in parallel with the MOS transistor is provided.

In order to manufacture such a semiconductor device,
The method of the present invention includes the following steps (A) to (H).
(A) A step of forming a silicon nitride film on a silicon substrate via a buffer oxide film to remove the silicon nitride film and the buffer oxide film in the element isolation region, and (B) etching the silicon substrate in the element isolation region to form a groove. The step of forming
(C) Oxidation step of filling the groove and forming an element isolation oxide film at the same height as the substrate surface, (D) Oxidation step of forming a gate oxide film after removing the silicon nitride film and the buffer oxide film, ( E) a step of depositing a polycrystalline silicon film and patterning it to form a gate electrode, (F) an impurity introducing step for forming a low concentration diffusion region for an LDD structure,
(G) A step of forming a sidewall spacer of an insulator only on the side surface of the gate electrode, and (H) an impurity introducing step for forming a high concentration diffusion region for the LDD structure.

The semiconductor device of the present invention also has an LDD structure MO as an input protection transistor or an output transistor.
An input / output cell having an S transistor and having a high-concentration diffusion layer having a conductivity type opposite to that of the drain diffusion layer is provided under the drain diffusion layer immediately below the contact hole on the drain side of the MOS transistor.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1A and 1B show an embodiment.
(A) shows an embodiment in which the present invention is applied to an input cell. In (A), 10 is an input line, 12 is an input first stage inverter, and the inverter 12 is composed of a PMOS transistor 14 and an NMOS transistor 16. A PMOS transistor 20 and an NMOS transistor 22 for input protection are connected between the input pad 18 and the inverter 12 on the input line 10, a protection resistor 24 is connected in series, and further protection diodes 26 and 2 are connected.
8 is connected. The source and gate electrode of the input protection transistor 20 are connected to the power supply Vcc, and the source and gate electrode of the NMOS transistor 22 are connected to the ground. The anode of the protection diode 26 is connected to Vcc, and the cathode of the protection diode 28 is connected to the ground. Input protection MOS transistor 20,
22 is MOS transistors 14 and 16 of the inverter 12
It has an LDD structure similar to. However, the protection diodes 26 and 28 have a single diffusion layer structure instead of the LDD structure.

FIG. 1B shows an embodiment in which the present invention is applied to an input / output cell. In (B), the input line 10 and the output line 30 via the output inverter 34 are connected to the input / output terminal 32. Protection diodes 26 and 28 are connected to the input line 10 between the output inverter 34 and the first-stage inverter 12. This diode 26,
28 also has a single diffusion layer structure. The output inverter 32 is composed of a PMOS transistor 36 and an NMOS transistor 38, and these MOS transistors 36 and 38 have an LDD structure.

Referring to FIG. 2, the LDD in the embodiment of FIG.
A method of manufacturing the input protection MOS transistors 20 and 22 or the output MOS transistors 36 and 38 having a structure and the protection diodes 26 and 28 having a single diffusion layer structure will be described. However, in FIG. 2, only the NMOS transistor is taken up for description, but the present invention can be applied to both the PMOS transistor and the CMOS. (A) A buffer oxide film 42 is formed on the surface of a P-type silicon substrate 40 by thermal oxidation to a thickness of about 250 Å, and a silicon nitride film 44 is deposited thereon by a CVD method to a thickness of about 1000 Å. After that, the buffer oxide film 42 and the silicon nitride film 4 are formed on a portion which will be a diffusion layer and a transistor region in the future.
Patterning is performed by photoengraving and etching so as to leave 4 to expose the substrate 40 in the element isolation region. Four
6 is a photoresist used in this patterning process.

(B) Using the photoresist 46, the silicon nitride film 44 and the buffer oxide film 42 as a mask, the silicon substrate 40 is etched to a depth of about 3000 Å to form a groove 48.
To form. (C) About 1000 ° C. after removing the photoresist 46
Is subjected to wet oxidation for about 200 minutes to form an oxide film 50 for element isolation having a thickness of about 6000Å. This oxide film 5
Since 0 is obtained by oxidizing the groove 48, the height is formed to be substantially equal to the surface of the substrate 40 without any unevenness.

(D) After removing the silicon nitride film 44 and the buffer oxide film 42, a gate oxide film having a thickness of 100 to 500 Å is formed on the entire surface by thermal oxidation. A polycrystalline silicon film is deposited thereon by CVD to a thickness of about 3500Å, and patterned by photolithography and etching to leave the gate electrode 54 and the gate oxide film 52 thereunder. LD
In order to form the lightly doped drain / source region of the D structure, for example, phosphorus is used at 2 × 1 with an acceleration energy of 60 KeV.
Ions are implanted at about 0 ¹³ / cm ² . 56 represents the implanted ions. (E) deposit a silicon oxide film on the entire surface by the CVD method,
When the entire surface is etched back by the completely anisotropic etching, the sidewall spacer 58 is formed only on the side surface of the gate electrode 54. Next, for example, 70K of arsenic is used to form a high concentration drain / source region of the LDD structure.
Ion implantation is performed at about 5 × 10 ¹⁵ / cm ^{2 with} eV. 60 represents the implanted ions.

(F) After that, when heat treatment is applied in a nitrogen atmosphere at about 1000 ° C. for about 30 minutes, an LDD structure having a low concentration region 62 and a high concentration region 64 is formed in the MOS transistor portion, and the other elements are separated. The diffusion region 66 in the region surrounded by the oxide film 50 has a single diffusion layer structure in which the low concentration region is incorporated in the high concentration region. afterwards,
By a known process, a MOS type semiconductor integrated circuit device is completed through processes such as forming an interlayer insulating film, forming a contact hole, and forming a metal wiring.

By the layout of the input / output cells in the peripheral portion as shown in FIGS. 1A and 1B by this manufacturing process, even if the MOS transistor has the LDD structure, the diode has the single diffusion layer structure. Become. Therefore, the excessive current due to the surge voltage easily escapes from the diode to the substrate, and the ESD withstand voltage improves. Further, in FIG. 1B, since the output transistor has an LDD structure, gm is high and the device is miniaturized.

FIG. 3 shows a second embodiment. (A) shows an example in which the present invention is applied to an input cell. Input line 10
And a PMOS transistor 20a and an NM connected between the input pad 18 and the first stage inverter 12 for input protection.
The OS transistor 22a has an LDD structure, and is provided with a high-concentration diffusion layer having a conductivity type opposite to that of the drain diffusion layer, which is in contact with the drain diffusion layer immediately below the contact holes on the drain side of the MOS transistors 20a and 22a.

(B) shows an example in which the present invention is applied to an input / output cell. The MOS transistors 36a and 38a of the output inverter 34a have an LDD structure, and are in contact with the drain diffusion layer immediately below the contact holes on the drain side of the MOS transistors 36a and 38a, and have a high-concentration diffusion layer opposite in conductivity type to the drain diffusion layer. Is equipped with.

FIG. 4 shows the NMO in FIGS. 3 (A) and 3 (B).
It shows an example of the drain portions of the S transistors 22a and 38a. NMOS is formed on the P-type silicon substrate 70.
A drain including an N-type low-concentration diffusion layer 72 and a high-concentration diffusion layer 74 is formed to form a transistor, and a P-type high-concentration diffusion layer 76 is formed in contact with the lower side of the high-concentration diffusion layer 74. Has been done. Reference numeral 78 is a gate oxide film, 80 is a gate electrode, and 82 is a sidewall spacer of an insulator used to form an LDD structure. 84 is an interlayer insulating film, 86 is a contact hole on the drain region,
Reference numeral 88 is a metal wiring connected to the drain through the contact hole.

A method of manufacturing the embodiment shown in FIGS. 3 and 4 will be described with reference to FIG. (A) An element isolation oxide film 90 is formed on a P-type silicon substrate (or P well) 70 by a usual method, a gate oxide film is formed, a polycrystalline silicon film is formed, and then photolithography and etching are performed. Patterning is performed to form a gate oxide film 78 and a gate electrode 80. (B) Input protection transistor of input / output cell (Fig. 3 (A)
22a) or an output transistor (38 in FIG. 3B).
A resist pattern 92 having an opening is formed in a region where a contact will be formed in the drain in a), and using the resist pattern 92 as a mask, for example, about 60 K of boron is used as P-type impurity ions.
Ion implantation is performed at an acceleration energy of eV of about 2 × 10 ¹³ / cm ² . 94 is the implanted boron ion.

(C) After removing the resist 92, about 2 × 10 ¹³ / cm ² ions of, for example, phosphorus as an N-type impurity are implanted into the entire surface at an acceleration energy of about 60 KeV. 96
Is the implanted phosphorus ion. (D) After that, a sidewall spacer 82 of an insulator is formed on the side surface of the gate electrode 80 by a known method, and, for example, arsenic as an N-type impurity is ionized at about 6 × 10 ¹⁵ / cm ² with an acceleration energy of about 50 KeV. inject. 98 is the implanted arsenic ion. After that, heat treatment is performed at about 1000 ° C. for about 30 minutes in a nitrogen atmosphere, an interlayer insulating film is deposited, contact holes are formed, and metal wiring is formed to complete the MOS transistor.

[0022]

According to the present invention, the input protection MOS of the input / output cell is provided.
Since the transistor or the output MOS transistor has an LDD structure and the protection diode has a single diffusion layer structure, an excessive current generated by applying a surge voltage easily passes through the protection diode to the ground line or Vcc.
It is possible to escape to the line, and it is possible to realize a sufficient ESD withstand voltage without causing the junction breakdown of the gate oxide film of the first stage inverter and the drain of the input protection MOS transistor. Further, since the output transistor has the LDD structure, it can be miniaturized to obtain a sufficient gm, for example, the gate length can be set to about 1.0 μm, and at the same time, the protection diode provides sufficient ESD.
Withstand voltage can be obtained.

In the manufacturing method of the present invention, since the oxide film for element isolation is formed so that the surface of the oxide film for element isolation and the surface of the silicon substrate have the same height, the MOS transistor is formed by a known method thereafter. Even if the LDD structure is formed,
Since the diffusion layers other than the source / drain do not have the double diffusion structure, the protection diode having the single diffusion layer structure can be manufactured without increasing the manufacturing process.

By providing a high-concentration diffusion layer having a conductivity type opposite to that of the drain diffusion layer under the drain diffusion layer immediately below the contact hole on the drain side of the MOS transistor, a current due to a surge entering the input pad from the outside is provided. It can be efficiently released to the substrate. Moreover, almost all of the current due to surge flows to the substrate just below the contact, so unless the structure is such that the current is concentrated at a specific place, it is not necessary to separate the contact and gate electrode more than necessary. Contribute to high integration. Also,
Since the drain structure near the gate electrode can be an LDD structure, even when this is used as an output transistor, even if the gate length is, for example, 1.5 μm or less, the transistor characteristics are not deteriorated, which is advantageous for high integration. Is.

[Brief description of drawings]

FIG. 1A and FIG. 1B are equivalent circuit diagrams showing an embodiment.

FIG. 2 is a process sectional view showing the manufacturing method in the example.

FIG. 3A and FIG. 3B are equivalent circuit diagrams showing other embodiments.

FIG. 4 is a cross-sectional view showing the vicinity of the drain of the NMOS transistor in the embodiment of FIG.

5A to 5C are process cross-sectional views showing the manufacturing method of the embodiment in FIG.

FIG. 6 is a cross-sectional view showing a diode manufactured by a conventional LDD process.

[Explanation of symbols]

20, 22, 20a, 22a Input protection transistor 26, 28 Protection diode 36, 38, 36a, 38a Output transistor 74 Drain diffusion layer 76 Diffusion region of opposite conductivity type provided under the drain diffusion layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H02H 7/20 F 7335-5G

Claims (3)

[Claims] 1. A semiconductor device comprising a MOS transistor having an LDD structure as an input protection transistor or an output transistor, and an input / output cell having a protection diode having a single diffusion layer structure in parallel with the MOS transistor. 2. A method of manufacturing a semiconductor device including the following steps (A) to (H). (A) A step of forming a silicon nitride film on a silicon substrate via a buffer oxide film and removing the silicon nitride film and the buffer oxide film in the element isolation region, (B) etching the silicon substrate in the element isolation region to form a groove And (C) an oxidation step of filling the groove and forming an element isolation oxide film at the same height as the substrate surface, (D) removing the silicon nitride film and the buffer oxide film,
Oxidation step of forming a gate oxide film, (E) step of depositing a polycrystalline silicon film and performing patterning to form a gate electrode, (F) impurity introduction for forming a low concentration diffusion region for an LDD structure Step (G) Step of forming sidewall spacers of an insulator only on the side surface of the gate electrode, (H) Step of introducing impurities for forming a high concentration diffusion region for the LDD structure. 3. A high-density MOS transistor having an LDD structure as an input protection transistor or an output transistor, being in contact with a drain diffusion layer immediately below a contact hole on the drain side of the MOS transistor and having a conductivity type opposite to that of the drain diffusion layer. A semiconductor device having an input / output cell having a concentration diffusion layer.