CN106098683A - A kind of esd protection circuit - Google Patents

Abstract

The invention discloses an ESD protection circuit. The circuit includes a PMOS tube and an NMOS tube, the PMOS tube is a large-size PMOS tube, and the NMOS tube is a large-size NMOS tube; the circuit also includes a detection circuit. The detection circuit is connected to the large-size PMOS transistor and the large-size NMOS transistor. The ESD protection circuit avoids device breakdown through large-size NMOS or large-size PMOS, can release static electricity in a timely and effective manner, and greatly enhances the ESD performance of the circuit. ESD protection.

Description

A kind of ESD protection circuit

technical field

The invention belongs to the technical field of integrated circuits, in particular to an ESD protection circuit for integrated circuits.

Background technique

Electrostatic discharge protection (ESD protection) is specially used for electrostatic discharge protection on integrated circuits. This electrostatic discharge protection provides an ESD current discharge circuit to prevent ESD current from flowing into the internal circuit of the IC and causing damage when ESD is discharged.

In some applications, relative positive and negative potentials appear between the power supply and ground of integrated circuits, or between IO ports, or between power supplies and ground wires in multi-power chips. Generally, the ESD protection shown in Figure 1 is used. structure. This structure involves device breakdown and discharge process, the trigger voltage is high, the ESD protection capability is low, and a large area is required.

For example, patent application 201110108194.3 discloses a power clamp ESD protection circuit, including: a power pin; a ground pin; an R-C circuit for sensing ESD voltage, including an impedance element connected between the power pin and the first node and A capacitive reactance element connected between the first node and the second node, wherein the second node is not directly connected to the ground pin; a trigger circuit, which is connected between the power supply pin, the ground pin and the R-C circuit, for An ESD trigger signal is generated according to the levels of the first node and the second node; a bias circuit, which is connected between the power supply pin and the ground pin, is used to provide a bias voltage for the second node; and, clamping The circuit, which is connected between the power supply pin, the ground pin and the trigger circuit, is used to provide a low-impedance channel between the power supply and the ground after receiving the ESD trigger signal, so as to discharge the electrostatic current. The circuit can effectively suppress the leakage current of the electrostatic protection circuit, and effectively protect the internal circuit from electrostatic damage. The circuit has a complex structure, many components, high cost, and consumes a large area. More importantly, this circuit cannot be applied to occasions where relative positive and negative potentials appear between nodes.

Contents of the invention

Based on this, the present invention provides an ESD protection circuit, which protects the protected circuit from electrostatic damage caused by external static electricity, solves the ESD protection problem in applications where relative positive and negative potentials occur between nodes, and solves the problem of ESD trigger voltage high problem while having a small circuit area.

Another object of the present invention is to provide an ESD protection circuit, which is simple in structure, easy to realize and low in cost.

To achieve the above object, the technical solution of the present invention is:

An ESD protection circuit, the circuit includes a PMOS tube and an NMOS tube, characterized in that the PMOS tube is a large-size PMOS tube, and the NMOS tube is a large-size NMOS tube; the circuit also includes a detection circuit, the The detection circuit is connected to the large-size PMOS transistor and the large-size NMOS transistor. The ESD protection circuit avoids device breakdown through large-size NMOS or large-size PMOS, and can release static electricity in a timely and effective manner, greatly enhancing the ESD performance of the circuit.

The detection circuit is composed of capacitors and resistors connected in series.

The capacitor includes C1 and C2, and the resistor includes R1 and R2. The resistors R1 and R2 can be in various equivalent forms, such as polycrystalline resistors, diffused resistors, pinch-off resistors, transistor equivalent resistors, and the like. Capacitors C1 and C2 can also be in various equivalent forms, such as well capacitors, MOS capacitors, polycrystalline capacitors, metal capacitors, and the like. Among them, the first ESD detection circuit composed of R1 and C1 connected in series, and the second ESD detection circuit composed of R2 and C2 connected in series, the RC time constant of the two is designed at 0.01 ~ 1.0us to distinguish ESD events from normal Power-on.

Further, resistor R1 and capacitor C1 form the first ESD detection circuit; one end of R1 is connected to the drain of large-size MP1, the other end is connected to C1, and at the same time is connected to the gate of MP1; one end of C1 is connected to potential VA, and the other end is connected to R1; MP1 The gate is connected to the connection node of R1 and C1, the source of MP1 is connected to VA, the drain of MP1 is connected to one end of R1, and is connected to the drain of large-size MN1 at the same time, and the body of MP1 is connected to its own drain.

Resistor R2 and capacitor C2 form the second ESD detection circuit; one end of R2 is connected to VB, and the other end is connected to C2; one end of C2 is connected to VA, and the other end is connected to R2; the large-size MN1 gate is connected to the connection node of R2 and C2, The source and body terminals of MN1 are connected to VB, and the drain of MN1 is connected to the drain of MP1.

In the ESD protection circuit realized by the present invention, its large-size NMOS or large-size PMOS is in a conduction state in an ESD event, which avoids device breakdown, triggers a very low voltage, and releases static electricity in a timely and effective manner, greatly enhancing the circuit Excellent ESD performance; compared with conventional methods, to achieve the same ESD level, the required NMOS and PMOS areas are greatly reduced.

The circuit can also provide ESD protection for applications where relative positive and negative potentials are present between nodes.

Description of drawings

FIG. 1 is a circuit diagram of an ESD protection circuit implemented in the prior art.

FIG. 2 is a circuit diagram of an ESD protection circuit implemented by the present invention.

detailed description

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

As shown in FIG. 2 , the ESD protection circuit realized by the present invention includes: a resistor R, a capacitor C, a large-size NMOS, and a large-size PMOS. Resistor R and capacitor C form a detection circuit capable of detecting ESD events. Large-size NMOS or large-size PMOS, in the ESD event, is in the conduction state, avoiding device breakdown, the trigger voltage is very low, and the static electricity is released in time and effectively, which greatly enhances the ESD performance of the circuit; compared with conventional methods, To achieve the same ESD level, the required NMOS and PMOS areas are greatly reduced.

The resistors R1 and R2 can be in various equivalent forms, such as polycrystalline resistors, diffusion resistors, pinch-off resistors, transistor equivalent resistors, and the like. Capacitors C1 and C2 can also be in various equivalent forms, such as well capacitors, MOS capacitors, polycrystalline capacitors, metal capacitors, and the like. The first ESD detection circuit composed of R1 and C1, and the second ESD detection circuit composed of R2 and C2, the RC time constants of the two are designed to be 0.01-1.0us to distinguish ESD events from normal power-on.

Resistor R1 and capacitor C1 form the first ESD detection circuit; one end of R1 is connected to the drain of large size MP1, the other end is connected to C1, and at the same time is connected to the gate of MP1; one end of C1 is connected to potential VA, and the other end is connected to R1. The gate of MP1 is connected to the connection node of R1 and C1, the source of MP1 is connected to VA, the drain of MP1 is connected to one end of R1, and is connected to the drain of large-size MN1, and the body of MP1 is connected to its own drain.

The resistor R2 and the capacitor C2 form a second ESD detection circuit; one end of R2 is connected to VB, and the other end is connected to C2; one end of C2 is connected to VA, and the other end is connected to R2. The gate of large-sized MN1 is connected to the connection node of R2 and C2, the source and body of MN1 are connected to VB, and the drain of MN1 is connected to the drain of MP1.

When VA has a positive ESD on VB, due to the transient action of the RC circuit, the gate of the large-size MN1 obtains a high voltage, and MN1 is in a conducting state during the ESD event, and the static electricity on VA passes through the parasitic diode of MP1 and then through The turned-on MN1 is released to VB in time and effectively.

When VA has a negative polarity ESD on VB, due to the transient effect of the RC circuit, the gate of the large-size MP1 obtains a low voltage. The parasitic diode of MN1 is released to VB in time and effectively.

To sum up, the large-size MN1 and large-size MP1 are in the conduction state during the ESD event, which avoids the device breakdown, the trigger voltage is very low, and the static electricity is released in a timely and effective manner, which greatly enhances the ESD performance of the circuit; and Compared with the conventional method, to achieve the same ESD level, the required NMOS and PMOS areas are greatly reduced.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention should be included in the protection of the present invention. within range.

Claims (6)

1. A kind of ESD protection circuit, this circuit includes PMOS tube and NMOS tube, it is characterized in that described PMOS tube is a large size PMOS tube, and described NMOS tube is a large size NMOS tube; Described circuit also includes detection circuit, The detection circuit is connected to the large-size PMOS transistor and the large-size NMOS transistor. 2. The ESD protection circuit according to claim 1, wherein the detection circuit is composed of a capacitor and a resistor connected in series. 3. The ESD protection circuit according to claim 2, wherein the capacitor includes C1 and C2, and the resistor includes R1 and R2. 4. ESD protection circuit as claimed in claim 3 is characterized in that the first ESD detection circuit that wherein R1 and C1 are connected in series forms, and the second ESD detection circuit that R2 and C2 are connected in series together, the RC of both The time constant is designed at 0.01 ~ 1.0us to distinguish between ESD events and normal power-on. 5. ESD protection circuit as claimed in claim 4, is characterized in that resistance R1 capacitance C1 forms the first ESD detection circuit; R1 one end is connected with large-size MP1 drain, the other end is connected with C1, and is connected with MP1 gate simultaneously; One end of C1 is connected to potential VA, and the other end is connected to R1; the gate of MP1 is connected to the connection node of R1 and C1, the source of MP1 is connected to VA, the drain of MP1 is connected to one end of R1, and the drain of large-sized MN1 is connected at the same time, MP1 The body terminal is connected to its own drain. 6. ESD protection circuit as claimed in claim 4, is characterized in that resistance R2 and electric capacity C2 form the second ESD detection circuit; R2 one end is connected with VB, and the other end is connected with C2; C2 one end is connected with VA, and the other end is connected with R2 Connection; the large-size MN1 gate is connected to the connection node of R2 and C2, the MN1 source and body terminals are connected to VB, and the MN1 drain is connected to the MP1 drain.