JPH06244892A - Phase comparator - Google Patents

Abstract

PURPOSE:To reduce the scale of a hardware by providing a means for calculating any specified parameter X, means for calculating a phase theta from the parameter X by solving any specified approximate formula and means for calculating phase difference between the phase theta and any prescribed phase. CONSTITUTION:The real number part data and imaginary number part data of complex multiplied results are introduced to input terminals 40 and 41 and inputted to an area converter 42. The area converter 42 converts input signals, which exist in areas from 40 deg. to 360 deg. in the vector figure, to the parameter X in areas from 0 deg. to 45 deg. and supplies them to an approximate circuit 43. On the other hand, which area, where the input signal exists, among respective areas 1-8 is decided and the result is supplied to a phase detection circuit 44. The approximate circuit 43 converts the parameter X to the phase theta by the approximate formula, which is calculated by performing the Taylor expansion of theta-ArctanX around X=1, and supplies the approximately calculated phase thetato the phase difference detection circuit 44. According to the area decided result of the area converter 42, the phase difference detection circuit 44 compares the phase with the prescribed phase and outputs difference DELTAtheta. Thus, the capacity of a ROM can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase comparator used in a carrier recovery circuit of a transmission / reception system using a multi-phase modulation system or a quadrature amplitude modulation system.

[0002]

2. Description of the Related Art In recent years, practical studies on transmission of large-capacity digital data such as image information have been conducted, and a multi-phase modulation method or a quadrature amplitude modulation method is used for these digital data transmission methods. . In these modulation methods, when reproducing a carrier wave from a modulated wave, a carrier wave reproducing circuit using a digital phase locked loop (PLL) circuit is used to reproduce a stable carrier wave. Hereinafter, a digital PLL circuit using a complex number signal will be described.

The modulation method is QPSK. FIG. 7B is a vector diagram of the QPSK signal. In QPSK, a symbol exists in one of the phases of 45 °, 135 °, 225 °, and 315 ° as shown in the figure, and data is transmitted according to the phase of the symbol. The received signal is quasi-coherently detected, where the phases of the symbols are orthogonal to each other in the I axis and the Q axis.
Converted to an amplitude value in the axial direction. These amplitude data are called I signal and Q signal.

FIG. 7A is a block diagram of a general digital PLL circuit. The complex number signals (I signal and Q signal) converted into digital signals are input to the terminals 10 and 11, and the I signal and Q signal are input to the complex multiplier 12. The complex multiplier 12 receives the I signal and the Q signal input from one side.
Signal and si from the data converter 16 input from the other
Complex multiplication is performed with the signals having the n and cos characteristics, and the result is given to the phase comparator 13. The phase comparator 13 detects the phase of the symbol from the real part data and the imaginary part data of the multiplication result of the complex multiplier 12 based on the inverse characteristic (Arctan) of the tangent (tan). Then, the phase difference between the detected phase and the predetermined phase (45 °, 135 °, 225 °, 315 °) is obtained (see FIG. 7B), and the phase error signal Δθ proportional to the phase difference is obtained in the PLL loop. Supply to the filter 14. The PLL filter 14 smoothes the phase error signal to obtain a control signal and supplies it to the control terminal of the numerically controlled oscillator 15.

The numerically controlled oscillator 15 obtains a phase signal whose oscillation frequency is controlled based on the control signal and supplies the phase signal to the data converter 16. The data converter 16 sins the phase signal
And a signal having two cos characteristics, and supplied to the other terminal of the complex multiplier 12 described above.

As described above, the complex multiplier 12, the phase comparator 13, the PLL loop filter 14, the numerically controlled oscillator 1
Frequency pulling and phase synchronization is provided by a fully digital control loop back to the complex multiplier 12 via 5 and the data converter 16.

As described above, the symbols transmitted by QPSK are 45 °, 135 °, and 225 in FIG. 7B.
One of the four phases of 315 ° and 315 ° is taken, but the symbol 21 in the phase pull-in operation state has a phase difference of Δθ with a predetermined phase (45 ° in the figure). Phase comparator 13
Detects this phase difference Δθ and outputs it as a phase error signal Δθ. The predetermined phase means that the input symbol phase is 0 ° to
45 ° at 90 °, 135 ° at 90 ° to 180 °, 1
It is 225 ° at 80 ° to 270 ° and 315 ° at 270 ° to 360 °, and the phase difference Δθ is detected in the range of −45 ° to + 45 °. Since the detection accuracy of the phase difference has a great influence on the performance of the PLL, the accuracy of the phase difference detection is required. As can be seen from FIG. 7B, the phase θ of the modulation symbol can be calculated by θ = Arctan (Q / I). Therefore, in order to maintain the phase detection accuracy, the conventional phase comparator is composed of a ROM having the addresses of the real part I and the imaginary part Q of the complex multiplication result as shown in FIG. 7C. The ROM has real part data I and imaginary part data Q.
Is stored as an address, and the value of the phase error signal Δθ corresponding to the phase θ calculated from the data I and the data Q is stored in each address. Since the phase error signal Δθ is output by giving data I and data Q to the ROM as addresses,
The detection accuracy depends on the number of bits of the address. However, when the number of bits of the address increases, the capacity of the ROM increases, so that the hardware scale increases, which is disadvantageous when integrated into an IC.

[0008]

As described above, in the phase comparator which inputs the signal of the complex number representation, the ROM
Was used to detect the phase difference. However, in order to improve the detection accuracy, there is a problem that the hardware scale becomes large. Therefore, an object of the present invention is to provide a phase comparator capable of reducing the scale of hardware.

[0009]

The phase comparator of the present invention is a phase comparator in which an input signal is represented by a complex number consisting of a real part I and an imaginary part Q, and the real part I and the imaginary part Q are used.
From 0 to X (X = Q / I or I / Q) ≦ 1, and a function θ = ArctanX to calculate the approximate expression obtained by series expansion to obtain the phase θ from the variable X Means and means for obtaining a phase difference between the phase θ and a predetermined phase.

[0010]

By the means described above, the approximation error of the approximate expression can be reduced by performing Taylor expansion of θ = Arctan X centering on X = 1, and using this approximate expression, the phase difference Δ
Since the capacity of the ROM used in the process of obtaining θ can be significantly reduced, the overall hardware scale can be reduced.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention and shows a block of a phase comparator 13 to which a complex number signal is input. The real part data I and the imaginary part data Q of the complex multiplication result are introduced into the input terminals 40 and 41, and are input to the domain converter 42. The domain converter 42 transforms the input signal existing in the region of 45 ° to 360 ° in the vector diagram shown in FIG. 2A into the variable X in the region of 0 ° to 45 °, and the approximation circuit 43.
Supply to. Further, it determines which of the areas 1 to 8 shown in FIG. 9A, and supplies the result to the phase difference detection circuit 44. The approximation circuit 43 sets the variable X to θ = Arct
AnX is converted into a phase θ by an approximate expression obtained by Taylor expansion centering on X = 1, and the approximate calculated phase θ is supplied to the phase error detection circuit 44. The phase difference detection circuit 44 compares the phase θ with a predetermined phase according to the area determination result of the area converter 42, and outputs the difference Δθ.
Next, examples of the domain converter 42, the approximation circuit 43, and the phase difference detection circuit 44 will be described.

FIG. 3 is a block diagram showing a specific example of the domain converter 42. The real part data I and the imaginary part data Q of the complex multiplier are input to the absolute value circuits 60 and 61 and the area determination circuit 66, respectively. Here, the area determination circuit 66
Only the codes of I and Q are input to. Absolute value i of real part I
And the absolute value q of the imaginary part Q are compared by the comparison circuit 62,
The comparison result is the selection circuits 63 and 64 and the area determination circuit 66.
Entered in. Further, i and q are also input to the selection circuits 63 and 64, respectively.

When the absolute value i of the real part data I and the absolute value q of the imaginary part data Q are i> q, the selection circuit 63 outputs q.
The selection circuit 64 selects i and outputs it to the divider 65. When q> i, the selection circuit 63
And the selection circuit 64 outputs q. Divider 65
Performs division with the input from the selection circuit 63 as the numerator and the input from the selection circuit 64 as the denominator, and outputs the result as a variable X.

That is, as shown in FIG. 2A, it is assumed that the real part and the imaginary part of the complex multiplication result which is the input signal indicate one of the positions marked by black circles in each region. Then i
> Q and the comparison circuit 62 outputs the result of i> q, the selection circuit 63 selects the imaginary part data q, and the selection circuit 64 selects and outputs the real part data i. Therefore, in the divider 65, the variable X becomes X = q / i, and the input is converted to the position of the double circle mark in the area 1. As a result, X = i / q or q / i is always 0 ≦ numerator ≦ denominator, so 0 ≦ X ≦
It becomes 1. The area determination circuit 66 determines the area of the input signal according to the table shown in FIG. In the case of QPSK modulation, −45 ° to +45 for each symbol indicated by a white circle.
Since it suffices to detect the phase difference in the range of °, the area determination circuit 66 outputs L in areas 1, 3, 5 and 7 and outputs H in areas 2, 4, 6 and 8. Figure 4 (a)
A concrete example of the approximation circuit 43 is shown in FIG.

Shown here is θ = Arctan X where X = 1.
Approximate equation θ = π / 4 of Taylor expansion centered on
+ (X-1) / 2- (X-1) ² This is a specific example for realizing / 4. First, the variable X is input to the subtractor 81 and subtracted by 1.0. The output of the subtractor 81 is input to the multiplier 83 and the coefficient unit 82. The multiplier 83 multiplies the outputs of the subtractor 81, and the coefficient unit 82 multiplies the output of the subtractor 81 by half. Here, the coefficient unit 82 may be a bit shifter. The output of the multiplier 83 is multiplied by a quarter in the coefficient unit 84, and its output is added to the output of the coefficient unit 82 by the adder 85. The coefficient unit 84 here may also be a bit shifter. The output of the adder 85 is added with π / 4 by the adder 86, and becomes the phase output θ of the approximation circuit.

In the above example, the procedure for obtaining the phase θ is the same as the procedure for calculating without forming the quadratic approximate expression described above, but the calculation for modifying the approximate expression as described later. It is obvious that the circuit may have a procedure.

FIG. 5 shows a block diagram of the phase difference detection circuit 44. The approximated phase θ is differentiated from 45 ° by the difference circuit 70 and supplied to the selection circuit 71 and the sign inversion circuit 72. The sign inversion circuit 72 supplies a value obtained by inverting the positive and negative signs of the value of the difference calculation result to the selection circuit 71. The selection circuit 71 outputs the output of the difference calculation circuit 70 when the area determination signal is L and the area determination results are 1, 3, 5 and 7, and the area determination signal is H and the area determination result is 2 ,
In the case of 4, 6 and 8, the output of the sign inverting circuit 72 is output as the phase difference Δθ. As shown in FIG. 2A, when the input signal is in the regions 1, 3, 5 and 7, the phase difference with each symbol is 0 ° to −45 °, and 2, 4, 6 and 8 are given.
In this case, since the phase difference with each symbol is 0 to 45 °, the phase difference with each symbol in each region is obtained by switching the sign of the phase difference with the region determination signal as described above. FIG. 4B shows another embodiment of the approximation circuit 43. In this example, 1 centered on X = 1 of θ = ArctanX
The following approximate expression θ = π / 4 + (X-1) / 2 is modified and θ = {π / 4 + (X-1)} / 2

The phase θ is calculated according to the calculation procedure of.
That is, first, the variable X is added to the variable X by (π / 2 −
1.0) is added, and the output of the adder 87 is the coefficient unit 8
It is halved by 8. This coefficient unit 88 may be a bit shift. FIG. 4C shows an embodiment in which the same approximation formula is not modified and the calculation circuit is used as it is in the procedure of θ = π / 4 + (X−1) / 2, and Therefore, the circuit scale becomes larger by the amount of the subtractor 89. When the circuit scale can be expected to be reduced by modifying the approximate expression in this way, the approximate circuit 41 may be a circuit that calculates the phase θ by the procedure of the modified approximate expression.

In addition, the above-mentioned primary, secondary and higher three
It is needless to say that the phase approximation calculation circuit can be configured in the same manner by using an approximation formula having orders such as quintic and quintic, and in that case, the approximation error of the phase θ can be reduced according to the order. Nor.

FIG. 6 shows a graph of the approximation error between θ = Arctan X and the approximate calculation formula with respect to X. The approximation error in the case of the first-order approximation is 91, and the approximation error in the case of the second-order approximation is 92, 3.
The case of the next approximation is 93. Although the approximation error decreases as the approximation order increases, the approximation order when actually configuring a calculation circuit depends on the bit accuracy of the circuit, the approximation error, the scale of the hardware, and the required phase calculation accuracy. Should be taken into consideration.

As described above, in the phase comparator which receives the complex-represented signal as an input, it is possible to detect a phase difference with a small error by a simple approximation formula without using a ROM having a large hardware scale. It is possible to realize a phase comparator which is advantageous for IC integration. Of course, the phase comparator according to the present invention can be used for other than the PLL.

[0023]

As described above, according to the present invention,
A phase comparator with small hardware scale can be realized.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

2A and 2B are an explanatory diagram and a region explanatory diagram of an input data phase shown for explaining the operation of the circuit of FIG.

FIG. 3 is a diagram showing a specific configuration example of the domain converter of FIG.

FIG. 4 is a diagram showing a specific example of the approximation circuit shown in FIG.

5 is a diagram showing a specific example of the phase difference detection circuit in FIG.

FIG. 6 is an explanatory diagram of an error between a value based on an approximate expression and an actual phase.

FIG. 7 is a circuit diagram of a carrier recovery circuit, an explanatory diagram for explaining a phase determination operation of a phase comparator used therein, and a diagram showing a configuration example of a phase comparator.

[Explanation of symbols]

42 ... Domain converter, 43 ... Approximation circuit, 44 ... Phase difference detection circuit

Front Page Continuation (72) Noboru Inventor Noboru Shiga, 3-3-9 Shinbashi, Minato-ku, Tokyo Within Toshiba Abu E. Ltd. (72) Susumu Komatsu 3-3-9 Shimbashi, Minato-ku, Tokyo Toshiba Abu E Co., Ltd.

Claims (4)

[Claims] 1. A phase comparator in which an input signal is represented by a complex number consisting of a real part I and an imaginary part Q, wherein 0 ≦ X (X = Q / I or I / Q) from the real part I and the imaginary part Q. Means for obtaining a variable X of ≦ 1, means for calculating a phase θ from the variable X by calculating an approximate expression obtained by series expansion of the function θ = ArctanX, and a phase difference between the phase θ and a predetermined phase. A phase comparator comprising: means for obtaining. 2. A phase comparator in which an input signal is represented by a complex number composed of a real part I and an imaginary part Q, wherein 0 ≦ X (X = Q / I or I / Q) from the real part I and the imaginary part Q. A means for obtaining a variable X such that ≦ 1 and an approximate expression θ = π / 4 + (X-1) / 2- (X-1) ² obtained by Taylor expansion of the function θ = ArctanX centered around X = 1. / 4 + (X
-1) ³ A phase comparator comprising: approximating means for calculating / 12 ... and obtaining a phase θ from the variable X; and means for obtaining a phase difference between the phase θ and a predetermined phase. 3. The approximation means is a first-order approximation formula by four arithmetic operations obtained as a result of Taylor expansion of a function θ = ArctanX centering around X = 1, and θ = π / 4 + (X-1) / 2. , Or a quadratic approximation θ = π / 4 + (X-1) / 2- (X-1) ² /
4. The phase comparator according to claim 1, which is means for calculating an approximate calculation formula having an order of 4, or higher. 4. The approximation means obtains an approximation formula θ = π / 4 + (X-1) / 2- (X-1) ² obtained by Taylor expansion of a function θ = ArctanX centered around X = 1. / 4 + (X
-1) ³ 2. The phase comparator according to claim 1, further comprising means for calculating a calculation formula obtained by mathematically transforming / 12 ...