JPH05347643A - Phase comparator - Google Patents

Abstract

(57) [Summary] [Purpose] To detect a phase difference with a small error in a circuit with a small hardware scale. The phase represented by the real part data and the imaginary part data is converted into a variable x in the range of 0 to + 45 ° in the area converter 101 by a data calculation process, and the approximation circuit 10
In 2, the phase data θ is approximated by a preset arithmetic expression. Then, the phase data θ is input to the phase difference detection circuit 103 together with the area data obtained by the area converter 101, and the phase error is obtained by the difference calculation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase comparator used in a carrier recovery circuit such as a multi-phase phase modulation system or a quadrature amplitude modulation system.

[0002]

2. Description of the Related Art In recent years, researches and practical applications regarding large-capacity digital data transmission such as image information have been actively conducted. This digital data transmission system includes a multi-phase modulation system and a quadrature amplitude modulation system. In these modulation methods, when the carrier wave is reproduced from the modulated wave, the digital PL
It has been considered to reproduce a stable carrier wave using an L carrier wave reproduction circuit. Hereinafter, a digital PLL circuit using a complex number signal will be described with reference to the drawings.

FIG. 6A is a block diagram of a general digital PLL circuit. The complex signals (I signal, Q signal) converted into digital signals are supplied to the input terminals 20 and 21. The I signal and the Q signal are input to the complex multiplier 22.

The complex multiplier 22 inputs I to one side.
Signal, Q signal, and data converter 2 input to the other side
The signal having the sin and cos characteristics from 6 is multiplied, and the result is output to the phase comparator 23.

The phase comparator 23 detects the phase from the real part data and the imaginary part data of the multiplication result of the complex multiplier 22 by the inverse characteristic (TAN ^-1 ) of the tangent (TAN). Then, the detected phase and a predetermined phase (QPS
In case of K modulated wave, 45 °, 135 °, 225 °, 315
Phase difference signal is obtained, and a phase error signal Δθ proportional to the phase difference is output to the PLL loop filter 24. PL
The L loop filter 24 smoothes the phase error signal to obtain a control signal, and supplies the control signal to the numerically controlled oscillator 25.

The numerically controlled oscillator 25 obtains a phase signal whose oscillation frequency is controlled based on the control signal and supplies it to the data converter 26. The data conversion device 26 divides the phase signal into two signals, converts the signals into sin and cos characteristic signals, and supplies the signals to the other end of the complex multiplier 22.

The above-mentioned complex multiplier 22, phase comparator 23,
Frequency pulling and phase synchronization are performed by a loop having a completely digital structure that returns to the complex multiplier 22 via the PLL loop filter 24, the numerically controlled oscillator 25, and the data converter 26.

FIG. 6B shows a vector diagram when the input signal is a QPSK modulated wave. The transmitted symbol has four phases of 45 °, 135 °, 225 °, and 315 °, but the phases are out of phase in the phase pull-in operation state, and the phase comparator 23 determines the detected phase and the predetermined phase. (45 ° in the example in the figure) is detected and the phase error signal Δ
Output as θ. The predetermined phase has a detection phase of 0 ° to 90
45 ° for °, 135 ° for 90 ° to 180 °, 1
It is 225 ° at 80 ° to 270 ° and 315 ° at 270 ° to 360 °, and the phase difference is detected in the range of -45 ° to 45 °. Here, the detection accuracy of the phase difference is PLL
Since it affects the performance of, the highly accurate phase detection is required. As shown in the figure, the phase θ of the modulation symbol is θ = arc t
Since it can be obtained by an (Q / I) and the phase comparator 23 maintains its phase detection accuracy, conventionally, as shown in FIG. 6 (C), R having the real part and the imaginary part of the complex multiplication result as addresses is used.
It was composed of OM. The ROM determines the phase θ from the real part data and the imaginary part data input as an address and stores the phase error signal Δθ corresponding to the phase θ.
The phase detection accuracy is determined by the number of bits of the address. However, as the number of bits of the address increases, the capacity of the ROM also increases, which increases the hardware scale, which is disadvantageous for IC implementation.

[0009]

As described above, in the phase comparator which inputs the signal of the complex number expression, when the ROM is used to improve the phase detection accuracy, the hardware scale becomes large. There is. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a phase comparator with a small hardware scale that is advantageous for IC implementation without lowering the phase detection accuracy.

[0010]

According to the present invention, in a phase comparator which inputs real part data and imaginary part data of a signal represented by a complex number, from the real part data I and the imaginary part data Q, -I < x (= Q / I or I / Q) <I, a means for obtaining the phase θ from the x by a straight line approximate to the characteristic of θ = arc tanx, and a means for obtaining the phase θ and a predetermined phase. And a means for obtaining a phase difference.

[0011]

By the above means, the variable x such that -I <x <I is obtained from the real part data and the imaginary part data of the signal in the complex number representation. It is possible to detect θ within the range.
Therefore, it can be realized by a circuit with a small hardware scale without relatively lowering the phase detection accuracy.

[0012]

Embodiments of the present invention will be described below with reference to the drawings in the case of QPSK modulation. FIG. 1 shows an embodiment of the present invention and shows a block of a phase comparator which inputs a complex number signal.

The real part data I and the imaginary part data Q of the complex multiplication result are input to the domain converter 101. The domain converter 101 has 45 ° to 36 ° of the vector diagram shown in FIG.
Input signal in the 0 ° range is used as a variable x in the 0 ° to 45 ° range.
And is supplied to the approximation circuit 102. Also, FIG.
It is determined which one of the areas 1 to 8 shown in (1) is present and the result is supplied to the phase difference detection circuit 103. Approximation circuit 10
2 is a straight line which approximates the variable x to the characteristic of θ = arc tanx, and converts it into a phase θ, and the approximated phase θ is detected by the phase difference detection circuit 103.
Supply to. The phase difference detection circuit 103 includes a domain converter 10
According to the region determination result in 1, the phase θ is compared with a predetermined phase and the difference Δθ is output. Next, the domain converter 10
1, a specific example of the approximation circuit 102 and the phase difference detection circuit 103 will be described.

FIG. 2 is a block diagram showing a concrete example of the domain converter 101. The real part data and the imaginary part data of the complex multiplication result are input to the absolute value circuits 301 and 302 and the area determination circuit 307, respectively. The area determination circuit 30
Only the code is supplied to 7. The absolute value of the real number part and the imaginary number part are compared by the comparison circuit 303, and the comparison result is the selection circuit 30.
4, 305 and the area determination circuit 307. The absolute values of the real part data and the imaginary part data are also supplied to the selection circuits 304 and 305, respectively. When the absolute value of the real part data and the imaginary part data is larger in the real part (a
> B), the selection circuit 304 outputs the absolute value of the imaginary part data (b) to the divider 306, and the selection circuit 305 outputs the absolute value of the real part data (a) to the divider 306. When the absolute value of the real part data and the imaginary part data is larger in the imaginary part (b>
a), the selection circuit 304 selects and outputs the absolute value of the real part data (a), and the selection circuit 305 selects and outputs the absolute value of the imaginary part data (b).

The divider 306 performs division using the input from the selection circuit 304 as the numerator and the input from the selection circuit 305 as the denominator, and outputs it as a variable x. That is, as shown in FIG. 1B, if the real part and the imaginary part of the complex multiplication result that is the input signal indicate the positions of the black circles (a> b) in each region,
The comparator 303 outputs the result of a> b. Then, the selection circuit 304 selects the imaginary part data (b), and the selection circuit 305 selectively derives the real part data (a). Therefore, in the divider 306, the variable x becomes x = b / a and the region 1 Of 2
It is converted to the position of the double circle. The area determination circuit 307 determines the area of the input signal according to the table shown in FIG.
In the case of QPSK modulation, each symbol indicated by a white circle and -45
Since it suffices to detect the phase difference in the range of ° to 45 °, it is only necessary to make determinations in two ways: areas 1, 3, 5 and 7 and areas 2, 4, 6 and 8.

FIG. 3A is a block diagram showing a specific example of the approximation circuit 102. The variable x is supplied to the comparator 401, the coefficient unit 402, and the selection circuit 404. The variable x is multiplied by 0.5 in the coefficient unit 402, and 0.2 in the adder 403.
5 is added and supplied to the selection circuit 404. The coefficient unit 4
02 need only be bit-shifted in this case. Comparator 4
01 compares whether the variable x is larger than 0.5 and supplies the comparison result to the selection circuit 404. Selection circuit 404
Directly selects and derives the variable x when the variable x is smaller than 0.5, and adds 403 when the variable x is larger than 0.5.
The variable x after calculation from is output as the phase θ. Thereby, the phase θ in each region can be obtained in the region 1. The comparator 401 is a value that determines the break point of the line graph that approximates the arctangent characteristic. The coefficient unit 402 and the adder 403 are units that set the slope of the polygonal line.

FIG. 3B is a graph showing an approximate expression of the approximate circuit 102 shown in FIG. The curve is θ = arc tan
x represents a straight line, and a straight line represents a graph based on an approximate expression. The approximate expression is θ = x when the variable x is smaller than 0.5, and θ = 0.5x + when the variable x is larger than 0.5.
It is 0.25. Here, the phase θ is 0 ° to 45 ° when the variable x is in the range of 0 to 1. With this approximate expression, the error can be kept within 2 °. Therefore, the input 0.5 of the comparison circuit 401 in FIG. 9A is the value of the variable x at the switching point of the approximate straight line, and the 0.5 of the coefficient unit 402 and the input 0.25 of the adder 403 are the approximate straight line. θ = 0.5x + 0.
25 slope and intercept.

FIG. 4A shows a block of the phase difference detection circuit 103. The approximated phase θ is subtracted from the difference circuit 601 by 0.79 radian (45 °) and is supplied to the selection circuit 602 and the inversion circuit 603. Inversion circuit 60
3 inverts the difference calculation result, and selects the inversion result in the selection circuit 602.
Supply to. The selection circuit 602 determines that the area determination is area 1,
The difference calculation result is output as 3, 5, and 7, and the inversion result is output as the phase difference Δθ when the region determination result is the regions 2, 4, 6, and 8. As shown in FIG. 1B, when the input signal is in the areas 1, 3, 5 and 7, the phase difference with each symbol is 0 ° to −45 °, and the phase difference between the areas 2, 4, 6 and 8 is as follows. Since the phase difference with each symbol is 0 ° to 45 ° at the time, the region 1,
At the time of 3, 5 and 7, Δθ = θ-45 °, regions 2, 4, 6
And .DELTA..theta. =-(. Theta.-45.degree.), The phase difference with each symbol in each area can be obtained.

FIG. 4B shows another embodiment of the approximating circuit 102, in which θ = arc tanx is approximated by three straight lines. The variable x is the comparators 701 and 702, the coefficient unit 704,
705 and the selection circuit 703. Comparator 70
In 1 and 702, the values are compared with 0.3 and 0.72 which are the values of the variable x at the switching point of the approximate straight line, and the respective comparison results are supplied to the selection circuit 703. The coefficient unit 704 and the adder 706 use the approximate expression θ = 0.76x + 0.07, and the coefficient unit 705 and the adder 707 use the approximate expression θ = 0.6x + 0.19.
And the respective calculation results are supplied to the selection circuit 703. The selection circuit 703 follows the comparison result of the comparators 701 and 702, and when the variable x is 0 to 0.3, the variable x (θ = x).
When 0.3 to 0.72, the approximate expression θ = 0.76x +
When the calculation result of 0.07 is 0.72 to 1, the approximate expression θ =
The calculation result of 0.6x + 0.19 is output as the phase θ. FIG. 4C shows a graph of an approximation formula by the approximation circuit of FIG. 4B, and the error of the phase θ due to the approximation is within 1 °.

FIG. 5 shows another embodiment of the present invention, θ
= arc tanx is approximated within a range of 0 ° ≦ θ ≦ 22.5 ° with a small error. 101 is a domain converter, 102
Is an approximation circuit, and 103 is a phase difference detection circuit.

The real and imaginary parts of the complex multiplication result are supplied to the same circuit 308 as the domain converter shown in FIG. 2, and the domain-transformed variable x and the domain determination result are output. Here, the variable x is in the range of 0 to 1, and the region determination result is the regions 1, 3,
5 and 7 and regions 2, 4, 6 and 8 are represented. Variable x
Is supplied to the comparator 901, the difference circuit 902, and the selection circuit 903. In the difference circuit 902, the variable x and 0.41 (2
2.5 ° = arc tan 0.41) is calculated and the calculation result is supplied to the selection circuit 903. In the comparator 901, the variable x is compared with 0.41 (22.5 ° = arc tan 0.41), and the comparison result is supplied to the selection circuits 903 and 906. According to the comparison result, the selection circuit 903 supplies the variable x to the approximation circuit 102 when the variable x is smaller than 0.41 and the difference calculation result when the variable x is larger than 0.41. As a result, the variable x is further 0 to 0.41 (0 ° ≦ θ ≦ 2
2.5 °) range.

The approximation circuit 102 is specifically a coefficient unit 904.
It is composed of 0 to 0.41 (0 ° ≦ θ ≦ 22.5
The variable x converted into the range of (.degree.) Is multiplied by 0.96. That is, it is an approximation with a straight line θ = 0.96x, and 0 ≦
θ = a in the range of x ≦ 0.41 (0 ° ≦ θ ≦ 22.5 °)
The error between rc tanx and θ = 0.96x is within 0.4 °. The approximated phase θ is determined by the selection circuit 906 and the adder 90.
5 is supplied. The adder 905 adds 0.39 radian (22.5 °) to the variable x, and selects the addition result as a selection circuit 906.
Supply to. The selection circuit 906 supplies the approximated phase θ to the phase difference detection circuit 604 when the variable x is smaller than 0.41 and the addition result when the variable x is larger than 0.41 according to the comparison result output from the comparison circuit 901. To do. Therefore, if the variable x is in the range of 0 to 0.41 (0 ° ≤ θ ≤ 22.5 °), it is approximated as it is, and in the range of the variable x is 0.41 to 1 (22.5 ° ≤ θ ≤ 45 °). , 0 to 0.41 (0 ° ≤
(θ ≦ 22.5 °), and the approximation is performed. After the approximation, the range is returned to 22.5 ° ≦ θ ≦ 45 °. As described above, the phase difference detection unit 907 obtains the phase difference Δθ with each symbol in each region from the phase θ converted and detected in the region 1. Although the variable x is set in the range of 0 to 1 or 0 to 0.41 in the present embodiment, the similar approximation performance can be obtained by using the range of -1 to 0. In addition to this, it goes without saying that the present invention can be modified in various ways without departing from the scope of the invention.

As described above, in the phase comparator which inputs the signal of the complex expression, it is possible to detect a phase difference with a small error by a simple approximation formula without using a ROM having a large hardware scale, which is advantageous for IC implementation. It is possible to realize various phase comparators. It goes without saying that the phase comparator according to the present invention can be used in addition to the PLL.

[0024]

As described above, according to the present invention, it is possible to detect a phase difference having a small error with a circuit having a small hardware scale.

[Brief description of drawings]

FIG. 1 is a circuit diagram and an operation explanatory diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific example of the domain converter shown in FIG.

FIG. 3 is a diagram showing a specific example of the approximation circuit of FIG. 1 and its characteristics.

FIG. 4 is a diagram showing a specific example of the phase difference detection circuit of FIG. 1, a diagram showing another example of an approximation circuit, and a diagram showing the characteristics of this approximation circuit.

FIG. 5 is a circuit diagram showing still another embodiment of the present invention.

FIG. 6 is a block diagram of a conventional carrier recovery circuit and an operation explanatory diagram thereof.

[Explanation of symbols]

101 ... Domain converter, 102 ... Approximation circuit, 102 ... Phase difference detection circuit, 301, 302 ... Absolute value circuit, 303 ... Comparator, 304, 305 ... Selection circuit, 306 ... Divider, 3
07 ... Area determination circuit, 401 ... Comparator, 402 ... Coefficient device, 403 ... Adder, 404 ... Selection circuit, 601 ... Difference device, 602 ... Selection circuit, 603 ... Inversion circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location H04L 27/38 9297-5K H04L 27/00 H (72) Inventor Noboru Shiga, Minato-ku, Tokyo 3 3-3 9 Toshiba Abu E Co., Ltd. (72) Inventor Yasushi Sugita 8 Shinsugita-cho, Isogo-ku, Yokohama, Kanagawa Pref.

Claims (2)

[Claims] 1. A real number part I and an imaginary number part Q of a complex number signal.
In the phase comparator that receives as input, a means for obtaining a variable x such that −1 <x (= Q / I or I / Q) <1 from the real part I and the imaginary part Q, and a phase θ from the variable x A phase comparator comprising: an approximation unit that obtains on a straight line that approximates the characteristic of θ = arc tanx; and a unit that obtains a phase difference between the phase θ and a predetermined phase. 2. The approximation means calculates the straight line by θ = arc t
2. The phase comparator according to claim 1, further comprising means for dividing the characteristic of anx and forming it by a plurality of approximated straight lines.