JPH06243695A - Peak hold device - Google Patents

Abstract

PURPOSE:To enable obtaining a normal peak hold output by providing a first and a second peak hold circuit and selecting an output of a peak hold circuit which is not reset by a reset signal. CONSTITUTION:An impulse high frequency signal 12 generated randomly is inputted to a buffer amplifier 11, and an output signal 13 of the buffer amplifier is sent out to a first and a second peak hold circuits 14, 15. On the other hand, reset signals 19, 20 are alternately sent out from a first timing generating circuit 18 to the circuits 14, 15, while a reset information signal 21 indicating that either of the circuits 14 and 15 is reset is sent out to a multiplexer 22. The circuit 14, 15 peak-holds the signal 13 in accordance with signals 19, 20, and send out respectively peak hold output signals 16, 17. The multiplexer 22 selects the peak hold signal 16 sent out from the circuit 14 (for example) which is not reset, and outputs it as a low frequency signal 23.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a peak hold device used for processing randomly generated impulse high frequency signals as low frequency signals.

[0002]

2. Description of the Related Art FIG. 5 shows, for example, "Data Book 1991 /
1992 (Analog Devices Inc. April 1991)
FIG. 6 is a time chart for explaining the operation of the peak hold device shown in FIG. In the figure, 1 is a buffer amplifier, 2 is a peak-holding of a randomly generated impulse high frequency signal 3 input via the buffer amplifier 1 based on a reset signal 5 sent from a reset timing generation circuit 4,
It is a peak hold circuit that sends a peak hold output signal 6.

In FIG. 6, a waveform (a) is an impulse high frequency signal 3 input to the buffer amplifier 1, a waveform (b) is a buffer amplifier output signal sent from the buffer amplifier 1, and a waveform (c) is reset. The reset signal 5 sent from the timing generation circuit 3 and the waveform (d) show the peak hold output signal 6 sent from the peak hold circuit 2.

In the conventional peak hold device configured as described above, the randomly generated impulse high frequency signal 3 (waveform a) is first input to the buffer amplifier 1, processed by the buffer amplifier 1 and output from the buffer amplifier. The signal (waveform b) is output. On the other hand, the reset signal 5 (waveform c) is output from the reset timing generation circuit 4. Then, the peak hold circuit 2 peak-holds the buffer amplifier output signal (waveform b) according to the reset signal 5 (waveform c), and sends the peak-hold output signal 6 (waveform d).

[0005]

Since the conventional peak hold device is configured as described above, the reset signal 5 output from the reset timing generation circuit 4 and the input impulse high frequency signal 3 are synchronized. Then, as indicated by the broken line in the waveform d shown in FIG. 6, there is a problem that the peak hold output signal 6 is not properly transmitted without being properly peak-held.

The present invention has been made in order to solve the above-mentioned problems. Even when the input impulse high frequency signal and the reset signal are synchronized with each other, the correct peak hold is performed and the normal peak hold output is obtained. It is an object of the present invention to provide a peak hold device capable of obtaining a signal.

[0007]

[Means for Solving the Problems] Claim 1 according to the present invention
Of the peak hold device of the first and second peak hold circuits for simultaneously inputting and holding the impulse high frequency signals, and for outputting the reset signals for alternately resetting to both peak hold circuits and for both peaks. A low-frequency signal is generated by sequentially selecting a peak timing output from a first timing generation circuit that sends a reset information signal indicating which one of the hold circuits is reset and a peak hold circuit that is not reset by the reset information signal. And a multiplexer for outputting as.

According to a second aspect of the present invention, the peak hold device alternately receives first and second peak hold circuits for simultaneously inputting the impulse high frequency signals and holding and outputting the peak hold signals, respectively. And a priority circuit that sequentially selects a larger one of the peak hold outputs from both peak hold circuits and outputs it as a low frequency signal. is there.

[0009]

The multiplexer of the peak hold device according to the first aspect of the present invention sequentially selects the peak hold output from the peak hold circuit which is not reset by the reset information signal from the first timing generation circuit, and the low frequency Output as a signal.

The priority circuit of the peak hold device according to the second aspect of the present invention sequentially selects the larger one of the peak hold outputs from both peak hold circuits and outputs it as a low frequency signal.

[0011]

【Example】

Example 1. Embodiments of the present invention will be described below with reference to the drawings. 1 is a block diagram showing the configuration of a peak hold device according to Embodiment 1 of the present invention, and FIG. 2 is a time chart for explaining the operation of the peak hold device in FIG. In the figure, reference numeral 11 designates a buffer amplifier for inputting a randomly generated impulse high frequency signal 12, and after processing, outputs a buffer amplifier output signal 13.
Reference numeral 5 is a buffer amplifier output signal 13 which is input and peak-held, and peak-hold output signal 1
First and second peak-hold circuits for sending 6 and 17, reset signal 19 for alternately resetting to these first and second peak-hold circuits 14 and 15,
A first timing generation circuit 22 for sending 20 respectively and a reset information signal 21 for indicating which one of the first and second peak hold circuits 14, 15 has been reset Select the peak hold output signal from the peak hold circuit that has not been reset in order to select the low frequency signal 2
3 is a multiplexer for sending out.

Further, in FIG. 2, a waveform (a) is an impulse high frequency signal 12 inputted to the buffer amplifier 11,
The waveform (b) is transmitted from the buffer amplifier 11 to the buffer amplifier output signal 13, and the waveforms (c) and (d) are transmitted from the first timing generation circuit 18 to the first and second peak hold circuits 14 and 15. Reset signal 19 and 2
0, waveforms (e) and (f) are peak hold output signals 16 and 17 output from the first and second peak hold circuits 14 and 15, respectively, and waveform (g) is from the first timing generation circuit 18 to the multiplexer. The reset information signal 21 and the waveform (h) sent to the multiplexer 22 are
Each of the low frequency signals 23 is shown from FIG.

In the peak hold apparatus according to the first embodiment having the above-described structure, the randomly generated impulse high frequency signal 12 (waveform a) is input to the buffer amplifier 11 and processed by the buffer amplifier 11. The buffer amplifier output signal 13 (waveform b) is sent to the first and second peak hold circuits 14 and 15. On the other hand, from the first timing generation circuit 18, reset signals 19 and 20 (waveforms c and d) that are alternately reset are sent to the first and second peak hold circuits 14 and 15, and at the same time, the first and second Second peak hold circuit 1
The reset information signal 21 (waveform g) indicating which of the four and 15 has been reset is sent to the multiplexer 22.

Then, the first and second peak hold circuits 14 and 15 are reset signals 19 and 20 (waveform c, respectively) sent from the first timing generation circuit 18.
In accordance with d), the buffer amplifier output signal 13 (waveform b) output from the buffer amplifier 11 is peak-held, and peak-hold output signals 16 and 17 (waveforms e and f) are transmitted, respectively. The multiplexer 22 receives the reset information signal 2 sent from the first timing generation circuit 18.
On the basis of 1 (waveform g), for example, the peak hold output signal 16 transmitted from the first peak hold circuit 14 on the non-reset side is selected. Then, by repeating this selection operation in sequence, the low-frequency signal 23 (waveform h)
As.

As described above, according to the first embodiment, both peak hold circuits 14 and 1 are driven by the reset signals 19 and 20.
5 are not reset at the same time, and the reset information signal 21
Thus, the peak hold output signal output from the peak hold circuit which is not reset is selected and the low frequency signal 23 is output by repeating this selection operation. Even if either one of the reset signals 19 and 20 is synchronized, the peak hold is accurately performed.

Example 2. FIG. 3 is a block diagram showing the configuration of a peak hold device according to the second embodiment of the present invention, and FIG.
3 is a time chart for explaining the operation of the peak hold device in FIG. In FIG.
The same parts as those of the peak hold device in FIG. Reference numeral 24 is a second timing generation circuit for sending reset signals 25 and 26 for alternately resetting to the first and second peak hold circuits 14 and 15, and 27 is the first and second peak hold circuits 14 and 15,
Peak hold output signal 1 sent from each 15
This is a priority circuit which compares 6 and 17 and sequentially selects the larger output and outputs it as the low frequency signal 28.

Further, in FIG. 4, a waveform (a) shows an impulse high frequency signal 12 inputted to the buffer amplifier 11,
The waveform (b) is sent from the buffer amplifier 11 to the buffer amplifier output signal 13, and the waveforms (c) and (d) are sent from the second timing generation circuit 24 to the first and second peak hold circuits 14 and 15. Reset signal 25, 2
6, waveforms (e) and (f) are peak hold output signals 16 and 17 output from the first and second peak hold circuits 14 and 15, respectively, and waveform (g) is a low frequency signal sent from the priority circuit 27. Signals 28 are shown respectively.

In the peak hold device according to the second embodiment having the above-described structure, first, as in the case of the first embodiment, the impulsive high frequency signal 1 randomly generated is generated.
2 (waveform a) is input to the buffer amplifier 11 and processed by the buffer amplifier 11 to output the buffer amplifier output signal 13
(Waveform b) is the first and second peak hold circuit 1
It is sent to 4 and 15. On the other hand, from the second timing generation circuit 24, a reset signal 25 for alternately resetting,
26 (waveforms c, d) are sent to the first and second peak hold circuits 14, 15.

Then, the first and second peak hold circuits 14 and 15 have reset signals 25 and 26 (waveform c, respectively) sent from the second timing generation circuit 24.
In accordance with d), the buffer amplifier output signal 13 (waveform b) output from the buffer amplifier 11 is peak-held, and peak-hold output signals 16 and 17 (waveforms e and f) are transmitted, respectively. The priority circuit 27 compares the peak hold output signals 16 and 17 sent from the first and second peak hold circuits 14 and 15, respectively, and selects the larger output. Then, by repeating this selection operation in sequence, the low-frequency signal 28 (waveform g) is transmitted.

As described above, according to the second embodiment, the same effect as that of the first embodiment can be obtained, and the peak hold output signals 16 and 17 sent from the peak hold circuits 14 and 15 can be compared with each other. Since the low-frequency signal 28 is transmitted by performing the selection by the priority circuit 27, the circuit can be very simple and the cost can be reduced.

Example 3. Incidentally, in each of the first and second embodiments,
Although the case where the buffer amplifier 11 is arranged in the input section has been described, the same effect as that of each of the first and second embodiments can be obtained even if the buffer amplifier 11 is omitted.

[0022]

As described above, according to claim 1 of the present invention, to the first and second peak hold circuits for simultaneously inputting the impulse high frequency signals and respectively holding and outputting the peak hold signals, and to both the peak hold circuits. A first timing generation circuit for transmitting a reset signal for alternately resetting and a reset information signal indicating which of the two peak hold circuits is being reset;
And a multiplexer that sequentially selects the peak hold output from the peak hold circuit that is not reset by the reset information signal and outputs it as a low frequency signal,

Further, according to a second aspect of the present invention, first and second peak hold circuits for simultaneously inputting the impulse high frequency signals and holding and outputting the respective peak hold signals,
A second timing generation circuit that sends out reset signals for alternately resetting to both peak hold circuits, and a priority circuit that sequentially selects the larger of the peak hold outputs from both peak hold circuits and outputs it as a low frequency signal. Therefore, it is possible to provide a peak hold device capable of correctly performing peak hold and obtaining a normal peak hold output signal even when the input impulse high frequency signal and the reset signal are synchronized. .

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a peak hold device according to a first embodiment of the present invention.

FIG. 2 is a time chart for explaining the operation of the peak hold device in FIG.

FIG. 3 is a block diagram showing a configuration of a peak hold device according to a second embodiment of the present invention.

FIG. 4 is a time chart for explaining the operation of the peak hold device in FIG.

FIG. 5 is a block diagram showing a configuration of a conventional peak hold device.

FIG. 6 is a time chart for explaining the operation of the peak hold device in FIG.

[Explanation of symbols]

 1, 11 Buffer amplifier 3, 12 Impulsive high frequency signal 13 Buffer amplifier output signal 14 First peak hold circuit 15 Second peak hold circuit 16, 17 Peak hold output signal 18 First timing generation circuit 19, 20, 25 , 26 reset signal 21 reset information signal 22 multiplexer 23, 28 low frequency signal 24 second timing generation circuit 27 priority circuit

Claims (2)

[Claims] 1. A first and second peak hold circuit for simultaneously inputting randomly generated impulsive high frequency signals and respectively holding and outputting the peak hold signals, and a reset signal for alternately resetting the peak hold circuits. In addition, the peak hold output from the first timing generation circuit that sends out the reset information signal indicating which of the two peak hold circuits is reset and the peak hold output from the peak hold circuit that is not reset by the reset information signal. A peak hold device, comprising: a multiplexer that sequentially selects and outputs as a low-frequency signal. 2. A first and a second peak hold circuit for simultaneously inputting randomly generated impulse high frequency signals and respectively holding and outputting the peak hold signals, and a reset signal for alternately resetting the peak hold circuits. A peak hold device, comprising: a second timing generating circuit, and a priority circuit that sequentially selects the larger one of the peak hold outputs from the two peak hold circuits and outputs it as a low frequency signal.