JPH06243682A - Dynamic RAM and data processing system thereof - Google Patents

Abstract

(57) [Summary] (Modified) [Purpose] In the differential amplifier of DRAM, coupling
MOS transistor by improving the capacitance
Low cost and large capacity
Can be applied to the main memory in the data processing system
DRAM AND DATA PROCESSING SYSTEM THEREOF-Patent application
And a memory cell having a first capacitor for storing information
A dynamic RAM having a memory array including
The MOS transistor pair in the differential amplifier is
The source side has a first capacitor and a second MOS transistor, respectively.
A transistor is provided and the second capacitor is
The same structure as the first capacitor of the molybdenum cell
By connecting the counter electrode of the second capacitor provided by
The capacitance is controlled by controlling the voltage applied to the counter electrode.
Make pulling.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential amplifier, and in particular, it is an effective technique when applied to a data processing system using a large capacity dynamic RAM as a main memory.

[0002]

2. Description of the Related Art Generally, in the process of forming a transistor, the threshold voltage V _th of the transistor varies depending on each transistor. For this reason, a dynamic RAM (hereinafter referred to as DR) that is used as a memory or is built in like a microcomputer.
In a transistor generally used in AM), a switching speed of MOS transistors forming a differential amplifier such as a sense amplifier and a main amplifier varies, so that a malfunction easily occurs. Figure 2
FIG. 2A shows a circuit diagram of a conventional CMOS sense amplifier as an example of this differential amplifier, and FIG. 2B shows an operation waveform diagram of this sense amplifier. Here, in FIG.
Based on the threshold voltage V _th of the MOS transistor Q2, it will be described with reference to the operation waveform diagram shown in FIG. 2 (b) this problem where the threshold voltage V _th of the NMOS transistor Q1 is low as an example. Now, it is assumed that a signal amount is output from the memory cell on the bit line BL side. In the operation of the CMOS sense amplifier, a high level voltage is applied to the input terminal PP and a low level voltage is applied to the input terminal PN, so that the signal is amplified on the bit line BL. At this time, if there is no variation in the threshold voltage V _th , the above N
The MOS transistor Q2 is the above-mentioned NMOS transistor Q.
The signal is turned on before 1 and the signal is amplified by a normal CMOS sense amplifier. However, this CMOS
In the sense amplifier, the NMOS transistor Q1
Since the threshold voltage V _th is low, the switching speed of the NMOS transistor Q1 is increased.
The NMOS transistor Q1 is an NMOS
It will be turned on before the transistor Q2. Therefore, as shown in FIG.
The potential of L first becomes Low level, the bit line BLB becomes High level, and the input or output data is inverted. Therefore, the sense amplifier or the main amplifier using the MOS transistor having the variation in the threshold voltage. A malfunction occurs in a memory such as a DRAM including the above.

In order to solve such problems, M
A differential amplifier incorporating a circuit for controlling the variation in the threshold voltage V _th of the OS transistor has been proposed. As an example, in FIG. 3A, C composed of MOS transistors having variations in threshold voltage is used.
A circuit diagram when the MOS sense amplifier is applied to a DRAM and an operation waveform diagram of this circuit are shown in FIG. This CMOS sense amplifier has a capacitor C at each source of NMOS transistors Q1 and Q2 that form an N-type sense amplifier NSA in a conventional CMOS sense amplifier.
1, C2 and switch MOS transistors Q5, Q6
Is provided. The gates of the switch MOS transistors Q5 and Q6 and the gate of the transfer MOS transistor Q4 are controlled by the switching SW signal. The coupling operation of the capacitors C1 and C2 is controlled by the coupling COM signal. Next, the operation of this circuit will be described below with reference to FIG. First, the precharge PCB signal is L
By setting it to the ow level, the NMOS transistors Q7, Q8, Q9 are turned off, the precharge operation is completed, and the compensation operation for the voltage corresponding to the threshold voltage V _th is completed. After that, the COM signal is set to the Low level to end the coupling operation,
After that, the SW signal is set to the High level to turn on the switch MOS transistors Q5, Q6, and Q4.
Then, the N-type sense amplifier NSA amplifies the data. Then, by setting the sense amplifier control PPB signal to the low level, the PMOS transistor Q10
Is turned on, the P-type sense amplifier PSA is activated, and the signal amplified in the CMOS sense amplifier composed of the N-type sense amplifier NSA and the P-type sense amplifier PSA is transmitted to the bit lines BL and BLB. . In this way, in the DRAM, the potential on the source side of the NMOS transistors Q1 and Q2 is applied with the potential of V _th difference in advance, and the pre-sense by the coupling is performed, whereby the normal operation as the differential amplifier is compensated.

Here, FIG. 4A shows the relationship between the amount of noise and the coupling capacitance due to variations in the threshold voltage V _th . In this graph, the horizontal axis shows the coupling capacitance / bit line capacitance as a parameter, and the vertical axis shows the noise amount (mV) due to the variation of the threshold voltage V _th as a parameter. As shown in the figure, if the coupling capacitance / bit line capacitance is small, noise increases, so the coupling capacitance / bit capacitance must be increased to some extent. However, in the CMOS sense amplifier shown in FIG. 3A, no consideration has been given to making the coupling capacitance sufficiently larger than the bit line capacitance. Further, similarly, the switch MOS transistor Q in FIG.
Also in Q5 and Q6, there is a fear of malfunction due to variations in the threshold voltage V _th . Here, FIG. 4B shows the relationship between the noise amount and the variation of the coupling capacitance due to the variation of the threshold voltage V _th . In this graph, the horizontal axis shows the coupling capacitance variation (%) as a parameter, and the vertical axis shows the noise amount (mV) due to the variation of the threshold voltage V _th.
Is shown as a parameter, and the coupling capacitance / bit line capacitance shown in FIG. 3A is changed for each case. As shown in the figure, in a constant coupling capacitance variation, the larger the coupling capacitance / bit line capacitance, the more the noise amount due to the variation in the threshold voltage V _th can be reduced. Further, as shown in FIG. 4B, as the coupling capacitance is larger with respect to the bit line, the threshold voltage V _th is compensated by the compensation operation of the threshold voltage V _th even if the coupling capacitance varies. The amount of noise due to variations can be reduced. However, in the conventional method, since the means for obtaining the coupling capacitance has not been studied, the ratio of the coupling capacitance to the bit line capacitance becomes small. For example, when the coupling capacitance is formed by a MOS transistor, the capacitance value depends on the voltage between the electrodes, so that there is a limit to the noise amount reduction, and it is difficult to avoid malfunction when the signal amount is small.
Furthermore, if the voltage amplitude during the coupling operation is large, NM
Since the node on the source side of the OS transistor Q1 has a negative potential, there is a problem that minority carriers are generated. Thus, the conventional threshold voltage V _th
The sense amplifier of the type that compensates for is not practically applicable other than the conventional DRAM having a small number of bits. Further, in the conventional sense amplifier, the coupling capacitance value has to be made larger than the bit line capacitance, and the main amplifier has not been examined in the same way, and the shared MOS transistor or the switch MOS transistor is not provided. In this case, a sufficiently large coupling capacitance is required for both the bit line capacitance outside the sense amplifier and the bit line capacitance inside the sense amplifier, which increases the chip area.

On the other hand, in recent years, an increase in the chip area due to the increase in the capacity of semiconductor memories, especially DRAM, has become a problem, which causes a problem that the cost increases. FIG. 5 shows, as an example, the long side direction 2 of the conventional DRAM.
A layout diagram for every 56 bits is shown. Since the sense amplifier is laid out in the center of the memory array and the number of bits increases, the number of sense amplifiers also increases, so the occupation ratio of the sense amplifier to the chip area increases and the chip area becomes very large. . As described above, in the conventional layout, the semiconductor memory has a large capacity, so that the chip area of the semiconductor memory and the microcomputer including the semiconductor memory increases, and the cost increases, and the memory board also increases in size and cost. Becomes a problem, and the cost increase of the main memory becomes a problem even when it is used as a data processing system requiring a large capacity. Therefore, the present inventor is currently studying the reduction of the chip area and the reduction of the cost even when the number of bits connected to one sense amplifier is increased. As an example, FIG. 6 shows an ordinary 16 MDRAM.
And a comparison of the signal amount with 16MDRAM when the number of bit lines for one sense amplifier is increased.
Although the number of bits connected to one sense amplifier is 256 bits in 16 MDRAM, the case where the number of bits is quadrupled will be described. In this case, the number of bits connected to one sense amplifier is 1024,
The amount of signal output from the memory cell is reduced to about 1/4. Here, the description will be continued below assuming that the signal amount at this time is 87 mV. In order to operate this DRAM normally, the noise amount for the variation of the threshold voltage V _th is 8 mV.
Must be reduced to. However, in the conventional method, since the method of obtaining the coupling capacitance with respect to the bit line capacitance has not been studied, 44 mV, which is noise due to the variation of the threshold voltage V _th in the transistors forming the sense amplifier, is quadrupled in bit number. In that case, there is a problem that the noise target cannot be reduced to 8 mV. Therefore, when the number of bits connected to one sense amplifier is quadrupled, the coupling capacitance / bit line capacitance becomes about 1/4 as shown in the graph of FIG. It is necessary to increase this coupling capacity by about 4 times. This increases the area for the coupling capacitance. Therefore, it is necessary to devise to reduce the bit line capacitance. However, the DRAM of FIG. 3 does not have a circuit for separating the CMOS sense amplifier from the bit line portion, and therefore the bit line capacitance becomes large. Will end up. Furthermore, the capacitor C
When transistor capacitances are used in 1 and C2, the coupling capacitance / bit line capacitance is reduced due to the large voltage dependency of the capacitance, noise cannot be reduced, and the noise of the threshold voltage V _th of the total signal amount is reduced. The ratio occupies more than half, and if the noise due to the coupling and the leak current is taken into consideration, the DRAM cannot operate. This sense amplifier cannot be used in such a DRAM having a large number of bits for one sense amplifier from two points, and in a conventional differential amplifier of the type that controls the threshold voltage of a MOS transistor, The problem of data inversion cannot be solved.

[0006]

In the differential amplifier of DRAM, by improving the coupling capacity, the variation of the threshold voltage of the MOS transistor is compensated, and the main memory in a low cost and large capacity data processing system. An object is to provide a DRAM applicable to a memory and a data processing system thereof.

[0007]

In a dynamic RAM having a differential amplifier having a MOS transistor pair and a memory array including a memory cell having a first capacitor for storing information, a MOS in the differential amplifier is provided.
A second capacitor and a second MOS transistor are respectively provided on the source side of the transistor pair, the second capacitor has the same structure as the first capacitor of the memory cell, and the opposite electrodes of the second capacitors provided opposite to each other are connected. Then, capacitive coupling is performed by controlling the voltage applied to the counter electrode.

[0008]

[Function] The coupling capacitance with respect to the bit line capacitance or the coupling capacitance with respect to the input / output line of the main amplifier can be increased, and minority carrier outflow from the counter electrode node due to the coupling can be prevented, and the sensitivity of the sense amplifier and / or the main amplifier is improved In addition, malfunction can be prevented. Therefore, 1
It is possible to increase the number of bit lines connected to the two sense amplifiers, reduce the number of sense amplifiers, reduce the DRAM chip area, and reduce the size and cost of the data processing system. Can be achieved.

[0009]

【Example】

(Embodiment 1) FIG. 1 is a partial circuit diagram of a DRAM including a sense amplifier of the present invention and its control circuit, and FIG. 7 shows its operation waveform. This embodiment will be described as compensating for variations in the threshold voltage of NMOS transistors. First, the configuration of the circuit diagram of FIG. 1 will be described below. A plurality of bit lines BL, BLB and a plurality of word lines WL are formed, and at the intersections of the bit lines BL and word lines WL, as shown in the memory cell 1 and the memory cell 2 connected to the word lines WL1 and WL2. A plurality of memory cells are configured. Since these memory cells are DRAMs, the memory cells 1 and 2 have the NMOS transistor Q1 respectively.
0 and a capacitor C3, an NMOS transistor Q19 and a capacitor C4. Also, this DR
When the AM is formed by the two-layer wiring structure, the Y select line YS and the common data lines CD and CDB are the word lines W.
It is laid out on the right side of L2. Therefore, the writing of the inversion information to the memory cell becomes slow. To prevent this, the PMOS transistor Q is used as the sense amplifier.
P-type sense amplifiers PSA1 and PM by 1 and Q2
The OS transistors Q3 and Q4 form a P-type sense amplifier PSA2. Also, the NMOS transistor Q
5, Q6 form an N-type sense amplifier NSA,
NMOS transistors Q9, Q12, Q are provided between the P-type sense amplifier PSA1 and the N-type sense amplifier NSA.
A precharge circuit PC is composed of 13. In order to share the P-type sense amplifiers PSA1 and PSA2 and the N-type sense amplifier NSA, the NMOS transistor Q
14, Q15 and NMOS transistors Q16, Q1
By using 7 as a shared MOS transistor, the left and right memory arrays can be selected. Here, based on the threshold voltage V _th of the NMOS transistor Q6, to the threshold voltage V _th of the NMOS transistor Q5 is low, to compensate for the voltage of the threshold voltage V _th difference in NMOS transistors Q5 Circuit is configured. This sense amplifier is the above-mentioned NMOS
The node on the source side of the transistor Q5 has V _th in advance.
Normal operation is guaranteed by applying a potential of a difference and performing preamplification by coupling using the capacitors C1 and C2.

The data read operation after the data write operation of this DRAM will be described below with reference to the operation waveform diagram of FIG. After the data writing operation, the bit line BL is set to the High level and the bit line BLB is set to the Low level. Here, the word line WL1 is set to the Low level. As a result, the NMOS transistor Q10 in the memory cell 1 is turned off,
The electric charge is held in the capacitor C3. After that, the PPB signal is set to the high level to turn off the PMOS transistor Q24, and the COM
The NMOS transistor Q26 is turned off by setting the signal to the low level. In addition, the PN signal is L
ow level, and the NMOS transistor Q27 is OF
When it is set to F, the amplification operation of the bit line pair BL, BLB by the CMOS sense amplifier is completed. afterwards,
The PCB signal is set to the high level, the NMOS transistors Q11, Q18 are turned on, the NMOS transistors Q9, Q12, Q13 are turned on, and the precharge circuit PC operates to operate the bit line pair BL, BLB.
The potential is set to 1/2 V _cc . Furthermore, if the CSS signal is Hi
The NMOS transistors Q22 and Q23 are turned on by setting the gh level. As a result, the common source lines of Q1, Q2 and Q3, 4 of the P-type sense amplifier PSA1 and the common source lines of Q7, Q8 of the NSA are short-circuited. At this time, the NMOS transistors Q6 and Q
Nodes a and b are held at a potential lower than 1/2 V _cc by the currents flowing through 8, Q28 and Q5, Q7, Q28. After that, the SW signal is set to Low level and the PNL signal is set to Low level,
Control circuit CNTR for compensating for difference in threshold voltage V _th
L1 operates. In this operation, first, the SW signal is Lo
By setting it to the w level, the NMOS transistors Q7 and Q8 are turned off, and when PNL is set to the LoW level, the NMOS transistor Q28 is turned off.
To be done. At this time, a current for charging the nodes a and b flows through the NMOS transistors Q5 and Q6, and the node a becomes a potential lower than 1/2 V _cc by V _{th of the} NMOS transistor Q5 and the node b becomes 1/2 V. _The currents flow until the potential becomes lower than _cc by the _{Vth of the} NMOS transistor Q6.
The potential difference between them is the same as the threshold voltage V _th difference. Prior to the next read operation, the shared signal SHR is Low.
The bit line that is set to the level and is not selected (in this case, the memory array on the right side) is separated, and the CSS signal is set to the Low level, so that the N-type sense amplifier NSA signal and the common source short circuit of PSA1 and PSA2 are shorted. To finish. After that, the PCB signal is set to the low level to complete the voltage compensating operation for the threshold voltage V _th . After that, the word line WL1 is High
By setting the level, the memory cell 1 is brought into a selected state, and a signal as accumulated data is taken out from the memory cell 1 composed of the NMOS transistor Q10 and the capacitor C3. After that, the shared signal SHL is set to the Low level, the shared MOS transistors Q14 and 15 are turned off, and the left bit line pair BL and BLB is disconnected. After that, the COM signal is set to High, so that the NMOS
The transistor Q26 is turned on, and the pre-sense operation is performed. At this time, the fixed capacitance having the same structure as the memory cell is used as the coupling capacitance, and the counter electrode of the coupling capacitance is changed from HVC2 (1/2 V _cc ) to 0 V, so that the potential difference between the bit lines BL0 and BL0B is changed. Can be large. Here, the counter electrode of the coupling capacitor is not limited to 0 V, and the same object can be achieved by fixing the counter electrode to a potential smaller than the power supply voltage. Further, by setting the PN signal and the PNL signal to the high level, the NMOS transistors Q27 and Q28 are turned on. After that, the SW signal is set to the high level to turn on the NMOS transistors Q7 and Q8.
And the PPB signal is set to Low level,
The PMOS transistor Q24 is turned on, and the potential of the sense amplifier common source is set to Low on the NMOS transistor side.
The PMOS transistor side is set to High level to latch the potential difference between the bit line pair BL0 and BL0B. Further, thereafter, the shared signals SHR and SH
By setting L to High level, the signal amplified in the sense amplifier is transmitted to the bit line BL. And
By setting the YS signal to the high level, the NMO
The S transistors Q20 and Q21 are turned on, and signals are transmitted to the common data lines CD and CDB.

FIG. 8 is a partial circuit diagram of a DRAM including a sense amplifier to which the present invention is applied and its control circuit, and FIG. 9 shows its operation waveform. This embodiment will be described as compensating for variations in threshold voltage of PMOS transistors. First, the configuration of the circuit diagram of FIG. 8 will be described below. Multiple bit lines BL, BLB and multiple word lines WL
And a plurality of memory cells are formed at the intersections of the bit lines BL and the word lines WL, as shown by memory cells 1 and 2 connected to the word lines WL1 and WL2. Since these memory cells are DRAMs, the memory cells 1 and 2 are composed of the NMOS transistor Q10 and the capacitor C3, and the NMOS transistor Q19 and the capacitor C4, respectively. When this DRAM is formed with a two-layer wiring structure, the Y select line YS and the common data lines CD, CDB
Are laid out on the right side of the word line WL2. For this reason, the writing of the inversion information to the memory cell becomes slow. To prevent this, an NMOS is used as the sense amplifier.
The N-type sense amplifier NS is formed by the transistors Q1 and Q2.
N by A1 and NMOS transistors Q3 and Q4
The type sense amplifier NSA2 is configured. Also, the PMOS
A P-type sense amplifier PS is formed by the transistors Q5 and Q6.
A is configured, and an NMOS transistor Q is provided between the P-type sense amplifier PSA and the N-type sense amplifier NSA1.
A precharge circuit PC is composed of 9, Q12 and Q13. In order to share the P-type sense amplifier PSA and the N-type sense amplifiers NSA1 and NSA2, an NMOS is used.
The left and right memory arrays can be selected by using the transistors Q14 and Q15 and the NMOS transistors Q16 and Q17 as shared MOS transistors. Here, based on the threshold voltage V _th of PMOS transistor Q6, to the threshold voltage V _th of PMOS transistor Q5 is low, to compensate for the voltage of the threshold voltage V _th difference in the PMOS transistor Q5 Circuit is configured. This sense amplifier is
A normal operation is guaranteed by applying a potential of _Vth difference to the node on the source side of the PMOS transistor Q5 in advance and performing preamplification by coupling.

The data read operation after the data write operation of this DRAM will be described below with reference to the operation waveform diagram of FIG. After the data writing operation, the bit line BL is set to the High level and the bit line BLB is set to the Low level. Here, the word line WL1 is set to the Low level. As a result, the NMOS transistor Q10 in the memory cell 1 is turned off,
The electric charge is held in the capacitor C3. After that, the PN signal is set to the Low level, so that N
The MOS transistor Q24 is turned off, and the COM signal is set to the high level to turn off the PMOS transistor Q26. Furthermore, the PP signal is High
Set to the h level and the PMOS transistor Q27 is turned off
As a result, the amplification operation of the bit line pair BL, BLB by the CMOS sense amplifier is completed. Then P
The CB signal is set to the high level, the NMOS transistors Q11, Q18 are turned on, the NMOS transistors Q9, Q12, Q13 are turned on, and the precharge circuit PC operates, so that the potential of the bit line pair BL, BLB is 1/2 V. _{cc is} assumed. Furthermore, if the CSS signal is High
Since it is set to the h level, the NMOS transistor Q
22 and Q23 are turned on. As a result, Q1 and Q2 of N-type sense amplifier NSA1 and Q3 and N3 of NSA2
The common source line of No. 4 and the common source lines of Q7 and Q8 of PSA are short-circuited. At this time, the nodes a and b are held at a potential higher than 1/2 V _cc by the currents flowing through the PMOS transistors Q28, Q7, Q5 and Q28, Q8, Q6. After that, the SW signal is set to the high level and the PPLB signal is set to the high level, so that the control circuit CNTRL1 for compensating the threshold voltage V _th operates. In this operation, first, the SW signal is set to the high level to turn off the PMOS transistors Q7 and Q8 and set PPLB to the high level.
By setting it to the h level, the PMOS transistor Q28 is turned off. At this time, the current that discharges the nodes a and b through the PMOS transistors Q5 and Q6 is
The node a has a potential higher than 1/2 V _cc by the Vth of the PMOS transistor Q5, and the node b has a potential of 1 /
By flowing until the potential becomes higher than 2V _cc by Vth of the PMOS transistor Q6, the nodes a and b are
The potential difference between them is the same as the threshold voltage V _th difference. Prior to the next read operation, the shared signal SHR is Low.
The bit line that is set to the level and is not selected (the memory array on the right side in this case) is separated, and the CSS signal is set to the Low level, thereby ending the common source short between the N-type sense amplifiers NSA1 and NSA2 and PSA. Let At the same time, by setting the PCB signal to the Low level, the voltage compensating operation for the threshold voltage V _th is completed. After that, the word line WL1 is set to the High level, so that the memory cell 1 is in the selected state,
The signal as the accumulated data is the NMOS transistor Q.
Memory cell 1 composed of 10 and capacitor C3
Taken from. After that, the shared signal SHL becomes L
By setting it to the ow level, the shared MOS transistors Q14, 15 are turned off, and the left bit line pair BL, BLB is disconnected. Then, the COM signal is set to Low, so that the PMOS transistor Q26 is turned on, and the pre-sense operation is performed. At this time, a fixed capacitor having the same structure as the memory cell is used as the coupling capacitor, and the counter electrode of the coupling capacitor is set to HVC2.
By changing (1/2 V _cc ) to V _cc , the potential difference between the bit lines BL0 and BL0B can be increased. Here, the counter electrode of the coupling capacitor is not limited to V _cc, and the same purpose can be achieved by fixing it to a potential lower than the power supply voltage. Furthermore, the PP
When the B signal and the PPLB signal are set to the Low level, the PMOS transistors Q27 and Q28 are turned on. After that, when the SW signal is set to the Low level, the PMOS transistors Q7 and 8 are turned on, and the PN
When the signal is set to the high level, the NMOS transistor Q24 is turned on, the potential of the sense amplifier common source is set to the high level on the PMOS transistor side and set to the low level on the NMOS transistor side, and the potential difference between the bit line pair BL0, BL0B is latched. . Further, thereafter, the shared signals SHR and SHL are turned on, so that the signal amplified in the sense amplifier is transmitted to the bit line BL. Then, by setting the YS signal to the high level, the NMOS transistors Q20 and Q2
1 is turned on, and a signal is transmitted to the common data lines CD and CDB.

FIG. 10 (a) is a schematic view of a main part of a sectional structure of capacitors C1 and C2 used as a coupling capacitor. This capacitor is formed by the FIN-STC (fin-stacked trench capacitor) structure like the capacitor of the memory cell in the memory array. FIG. 10 (b) shows the DRAM of the present invention with FIN-STC.
The layout diagram when is used is shown. In this case, since the capacitor with the same structure as the memory cell is used,
The coupling capacitance can be obtained in a smaller area than the transistor capacitance. This is advantageous because the increase of the chip area can be prevented and the number of process steps does not increase. FIG. 10C shows a table comparing the case where the MOS capacitor is used as the coupling capacitor of the DRAM of the present invention and the case where the fixed capacitor having the same structure as the memory cell is used. When the MOS capacitor is used, not only the chip area greatly increases, but also the voltage dependency of the capacitor increases as described above, and the noise amount with respect to the coupling capacitor / bit line capacitance is unstable. The threshold voltage V
_{It is} also difficult to control the _th compensation operation. On the other hand, when the fixed capacitance having the same structure as the memory cell is used, the increase of the chip area can be prevented as described above, the voltage dependency of the capacitance is small, and the noise amount with respect to the coupling capacitance / bit line capacitance is also reduced. It becomes stable, and the control of the compensation operation of the threshold voltage V _th becomes easy. As described above, in the present invention, the structure similar to that of the memory cell is used as the coupling capacitor, the shared MOS transistor is provided to separate the sense amplifier from the bit line, and the coupling operation in the threshold voltage control circuit is reduced to 1 as described above. / 2V _cc to 0V
The threshold voltage V _th is compensated by changing the value to. Further, a coupling capacitor is similarly formed in a differential amplifier in a main amplifier described later.

FIG. 11 is a schematic view of the essential parts of the layout of the DRAM of the present invention. In the DRAM of the present invention, the number of bits that can be connected to one sense amplifier can be increased, the variation in the threshold voltage of the sense amplifier can be compensated, and the normal operation of the sense amplifier can be maintained. Therefore, the chip area is greatly reduced. Therefore, a large-capacity and small-sized DRAM can be realized.

Next, FIG. 12 shows a circuit diagram and FIG. 13 shows an operation waveform diagram in the case where this differential amplifier is applied to a main amplifier of a DRAM. This embodiment will be described as an example for compensating for variations in the threshold voltage of the NMOS transistor. First, the configuration of the circuit diagram of FIG. 11 will be described below. In this embodiment, as a main amplifier, a P-type main amplifier PMA1 is composed of the PMOS transistors Q1 and Q2, and a P-type main amplifier PMA2 is composed of the PMOS transistors Q3 and Q4. Further, an N-type main amplifier NMA is constituted by the NMOS transistors Q5 and Q6, and between the P-type main amplifier PMA1 and the N-type main amplifier NMA,
A precharge circuit PC is composed of the NMOS transistors Q9, Q12 and Q13. Then, by using the NMOS transistors Q16 and Q17 as switch MOS transistors, the common data line CD,
It becomes possible to control the connection between the CDB and the main amplifier input / output lines MAT and MAB. Here, based on the threshold voltage V _th of the NMOS transistor Q6, to the threshold voltage V _th of the NMOS transistor Q5 is low, to compensate for the voltage of the threshold voltage V _th difference in NMOS transistors Q5 Circuit is configured. This main amplifier guarantees a normal operation by applying a potential of _Vth difference to the source side node of the NMOS transistor Q5 in advance and performing preamplification by coupling using the capacitors C1 and C2.

The data read operation after the data write operation of this DRAM will be described below with reference to the operation waveform diagram of FIG. After the data write operation, the main amplifier input / output line MAT is set to the high level and the main amplifier input / output line MAB is set to the low level. Here, the Y select line YS is set to the low level. After that, the MPPB signal is set to the High level to turn off the PMOS transistor Q24,
When the MCOM signal is set to Low level, NM
The OS transistor Q26 is turned off. Furthermore, MP
The N signal is set to low level, and the NMOS transistor Q
When 27 is turned off, the amplification operation of the main amplifier input / output line pair MAT, MAB by the main amplifier is completed. After that, the MPCB signal is set to the high level, the NMOS transistors Q11, Q18 are turned on, the NMOS transistors Q9, Q12, Q13 are turned on, and the precharge circuit PC operates to operate the main amplifier input / output line pair MAT, MAB. Potential is 1/2 V _cc
It is said that Further, by setting the MCSS signal to the high level, the NMOS transistors Q22, Q23
Is turned on. As a result, the P-type main amplifier P
MA1, Q1, Q2 and Q3, 4 common source line and N
The common source lines of MA Q7 and Q8 are short-circuited.
At this time, the currents flowing through the NMOS transistors Q6, Q8, Q28 and Q5, Q7, Q28 cause the node a,
b is held at a potential lower than 1/2 V _cc . Then M
When the SW signal is set to the Low level and the MPNL signal is set to the Low level, the control circuit CNTRL1 for compensating for the difference in the threshold voltage V _th operates. In this operation, first, the MSW signal is set to the Low level, so that the NMOS transistors Q7 and Q8 are
Is turned off and MPNL is set to LoW level, whereby the NMOS transistor Q28 is turned off.
At this time, a current for charging the nodes a and b flows through the NMOS transistors Q5 and Q6, and the node a is 1 /
Than 2V _cc to a Vth of only low potential of the NMOS transistors Q5, also the node b is 1 / 2V _cc above by more current flows until the Vth of only low potential of the NMOS transistor Q6 nodes a, between b Difference of the threshold voltage V _{th is} generated. Prior to the next read operation, the input / output IOC signal is set to Low level, and the main amplifier input / output lines MAT, M not selected are not selected.
Separate the AB and common data lines CD, CDB,
By setting the MCSS signal to the low level, the N-type main amplifier NMA signal and PMA1, PM
End the common source short of A2. At the same time, M
By setting the PCB signal to the low level, the voltage compensating operation for the threshold voltage V _th is completed. Then Y
When the select line YS is set to High level, the common data lines CD and CDB are activated and data is taken out. After that, the input / output signal IOC is set to the Low level to turn off the switch MOS transistors Q16, 17 and disconnect the left main amplifier input / output line pair MAT, MAB from the common data lines CD, CDB. After that, the MCOM signal is set to High to turn on the NMOS transistor Q26.
Then, the pre-sense operation is performed. At this time, a fixed capacitor having the same structure as the memory cell is used as the coupling capacitor, and the counter electrode of the coupling capacitor is set to HVC2 (1 / 2V).
It is possible to increase the potential difference between the main amplifier input / output lines MAT and MAB by changing from ( _cc ) to 0V. Here, the counter electrode of the coupling capacitor is not limited to 0V, and the same purpose can be achieved by setting the potential to be lower than the power supply voltage. Further, by setting the MPN signal and the MPNL signal to the high level, the NMOS transistors Q27 and Q28 are set to the high level. After that, when the MSW signal is turned on, the NMOS transistors Q7 and 8 are turned on, and M
By setting the PPB signal to the low level, the PMO
The S transistor Q24 is turned on, and the potential of the common source of the sense amplifier is set to Low level on the NMOS transistor side and High level on the PMOS transistor side to latch the potential difference between the main amplifier input / output line pair MAT and MAB. Further, after that, the input / output signals MAT and MAB are turned on to transmit the signal amplified in the main amplifier to the main amplifier input / output line MAT. And Y
By setting the select YS signal to the high level, the NMOS transistors Q20 and Q21 are turned on,
A signal is transmitted to the common data lines CD and CDB. In this embodiment, the case where the threshold voltage of the NMOS transistor is compensated has been described, but the same can be applied to the case where the threshold voltage of the PMOS transistor is compensated. Further, it is possible to provide a circuit for compensating the threshold voltage at the same time in the sense amplifier and the main amplifier, and it is possible to maintain reliability as a DRAM. Here, when three-layer wiring is used,
In FIG. 12, the precharge MOS transistor Q1
1 and Q18 are not required, and Y select line, switch MOS transistors Q20 and Q21, common data line C
Since D and CDB can be arranged beside the NMOS transistors Q1 and Q2 and do not affect the speed for writing the inversion information, the P-type sense amplifier configured by the PMOS transistors is used in FIGS. PSA
2 can be omitted, and in FIG. 8, the N-type sense amplifier configured by the NMOS transistor can be omitted.

FIG. 14 shows a D to which the differential amplifier of the present invention is applied.
The functional block diagram of RAM is shown. First, the data writing / reading operation of this DRAM will be described. First, the data write operation to the memory cell is performed by the input / output circuit I.
Data is externally input to / O, and then the write enable signal WEB becomes Low, whereby the switch SWT is turned off and the connection with the main amplifier MA is cut off. On the other hand, the row address strobe signal RAS as a clock signal generated from the central processing unit CPU
B, the column address strobe signal CASB and the address signal externally specified are the address buffer A
Input to DB. Then, the bit line BL is selected via the Y decoder YDCR, and a voltage is applied to the gate electrode of the transfer MOS transistor to turn on the transfer MOS transistor to transfer data, and the sense amplifier SA amplifies the input data. . On the other hand, the address signal input to the address buffer ADB is pre-decoded in synchronization with the clock signal described above, the word line WL is selected via the X decoder XDCR, and the signal is amplified by the word driver WLDRIVE to specify the specified address. Data input from the outside is written in the memory cell. The operation of reading data from the memory cell will be described below. Clock signal RAS generated from the central processing unit CPU
B, CASB and an externally designated address signal are input to the address buffer ADB. Meanwhile, light
When the enable signal WEB becomes High level and the switch SWT is turned on, the transfer M
The OS transistor and the main amplifier MA are connected.
Then, the bit line BL is selected via the Y decoder YDCR and the transfer MOS transistor is turned on.
Then, the output buffer OB is turned on. On the other hand, the address signal input to the address buffer ADB is predecoded and input to the X decoder to select the word line WL and the word driver WLd.
The signal is amplified by the live. As a result, the accumulated data is read from the memory cell at the address designated from the outside, and the data is stored in the bit line B.
It is read from L via the transfer MOS transistor. Since the switch SWT is turned on, the main amplifier MA amplifies the data, and the output buffer OB reads the data from the input / output circuit I / O. In this way, data reading from and data writing to the DRAM of the present invention are performed. Whether or not to use a differential amplifier provided with a circuit for compensating the threshold value for each of the sense amplifier SA and the main amplifier MA in this DRAM can be arbitrarily set. When the differential amplifier of the present invention is applied as a sense amplifier, the DRAM has a large number of bits, and malfunctions such as data inversion are unlikely to occur even if the capacity is large, and the area occupied by the sense amplifier SA is reduced. Therefore, the chip area can be significantly reduced and the layout efficiency can be improved. Further, when the differential amplifier of the present invention is applied as the main amplifier, malfunction can be prevented,
The reliability is greatly improved.

(Embodiment 2) FIG. 15 shows a functional block diagram of a memory board using the DRAM of the present invention. This system includes a DRAM IC ARRAY, a central processing unit CPU, the DRAM, and an interface circuit I / F for interfacing with the central processing unit CPU. This DRAM IC ARRAY
Is composed of the mounted DRAM of the present invention. First, this DRAM system and central processing unit CP
Input / output signals to and from U will be described. Address signals A0-Ak generated by the central processing unit CPU select the addresses of the DRAM of the present invention. The refresh instruction signal REFGRNT is a control signal for refreshing the memory information of the DRAM of the present invention. The write enable signal WEB is a data read / write control signal in the DRAM of the present invention. The memory activation signal MS is a control signal for starting the memory operation of the DRAM of the present invention. Input / output data D1 to DB on the data bus are transmitted between the central processing unit CPU and the DRAM. Further, the refresh request signal REFR
EQ is a control signal for requesting refresh of the memory information of the DRAM of the present invention. Interface circuit I
/ F, the row address receiver RAR outputs the address signals A0 to A sent from the central processing unit CPU.
Of k, the address signals A0 to Ai are received and converted into address signals at timings suitable for the operation of the DRAM of the present invention. The column address receiver CAR receives the address signal Ai + of the address signals A0-Ak.
1 to AJ are received. Then, the address signal is converted into a timing signal suitable for the operation of the DRAM of the present invention. Also,
The address receiver ADR receives the address signals Aj + 1 to Ak among the address signals A0 to Ak. Further, it is converted into an address signal of a timing suitable for the operation of the DRAM of the present invention. Decoder DCR
A chip selection control signal (hereinafter, referred to as CS1 to CSm) for selecting a chip of the DRAM of the present invention is transmitted by. RAS control circuit RAS-CNTRL
Causes the chip select signal and the row address fetching signal to be sent at the timing suitable for the DRAM operation of the present invention. The address multiplexer ADMPX multiplexes the address signals A0 to Ai and Ai + 1 to Aj in time series and sends them to the DRAM of the present invention. The data bus driver DBD includes the central processing unit CPU and the DRA of the present invention.
Input / output of data to / from M is switched by the WEB signal. The control circuit CNTRL sends out signals for controlling the address multiplexer ADMPX, RAS control circuit RAS-CNTRL, data bus driver DBD, DRAM of the present invention and the like. Next, the function of the address signal in this DRAM system will be described. The address signals A0-Ak sent from the central processing unit CPU are separated into two functions of address signals A0-Aj and address signals Aj + 1-Ak in the DRAM system. That is, the address signals A0 to Aj are used as the row and column address signals of the memory matrix in each chip of the DRAM of the present invention. That is, the address signals A0 to Ai are the ICs of the DRAM of the present invention.
It is designed to assign Ai + 1 to Aj to the row selection of the chip array and the column selection of the IC chip array.

Next, the circuit operation in this DRAM system will be described. First, address signals A0 to Ai, Ai
+1 to Aj are row address receivers RAR,
It is applied to the address multiplexer ADMPX via the column address receiver CAR. Then, in the address multiplexer ADMPX, when the RASbB signal reaches a certain level, row address signals A0 to Ai are transmitted and applied to the address terminals in the DRAM of the present invention. At this time, the column address signals Ai + 1 to A
j is not sent from the address multiplexer ADMPX. Next, when the RASbB signal becomes a level opposite to the above, column address signals Ai + 1 to Aj are sent from the address multiplexer ADMPX,
It is applied to the address terminal. At this time, the row address signals A0 to Ai are the address multiplexer ADM.
It is not sent from the PX. Thus, the address signals A0 to Ai and Ai + 1 to Aj are DR of the present invention in time series according to the level of the RASbB signal.
It is applied to the address terminal of AM. The chip selection signals Aj + 1 to Ak mainly select the chip in the DRAM of the present invention through the decoder DCR. Then, it is converted into chip select signals CS1 to CSm and used as a chip select signal and a row address fetch signal.

Next, the address setting operation in the chip in each row of the DRAM of the present invention will be described. First, the row address signals A0 to Ai are all I of the DRAM of the present invention.
It is applied to the address terminal of the C chip. Then RAS
One of the 1B to RASmB signals, for example RAS
It is assumed that the top B ICs are selected when the 1B signal reaches a certain level. At this time, the IC (IC11,
IC12, ..., IC1B) The row address signal A0 is applied to the row address of the memory matrix array in the chip.
~ Ai is applied to the IC before the RAS1B signal. The reason is that if the RAS1B signal is applied before the row address signals A0 to Ai, signals other than the row address signal may be taken in. Next, the column address signals Ai + 1 to Aj are applied to the address terminals of all IC chips of the DRAM of the present invention. After that, when the CASB signal delayed from the RAS1B signal reaches a certain level, the column address signals Ai + 1 to Aj are fetched into the column addresses of the memory matrix arrays in the nM and B IC chips in the uppermost stage. here,
The reason why the column address signals Ai + 1 to Aj are applied to the IC before the CASB signal is the same as the above reason. The function of the CASB signal is that the row address signals A0 to Ai or the column address signals Ai + 1 to A
It is to distinguish which signal of j is being sent. By the above operation, the uppermost nM, B in-chip addresses of the DRAM of the present invention are set. Also,
ICs other than the uppermost stage of the DRAM of the present invention are RAS2B to R
Since the ASmB signal has a level opposite to the level of RAS1B, it is not selected.

Next, a data write operation and a data read operation at the above set address will be described. The data write operation and data read operation are designed to be determined by the high level or low level of the WEB signal. The data write operation is performed by applying the data DI1 to DIB from the central processing unit CPU to the set address when the WEB signal is at a certain level. The read operation is performed by outputting the data Do1 to DoB of the respective addresses for which the writing has been completed in B bits when the WEB signal has a level opposite to the above. Control circuit C
NTRL receives a command signal, that is, a REFGRNT signal, a WEB signal, and an MS signal from the central processing unit CPU, and receives a CASB signal, a RASaB signal, a RASbB signal,
WEB signals are transmitted respectively. The function of these transmitted control signals will be described. The CASB signal is a signal for distinguishing which of the row address signals A0 to Ai or the column address signals Ai + 1 to Aj is being sent to each chip in the DRAM of the present invention and a signal for fetching the column address signal of the IC chip. Is. The RASaB signal is a signal for supplying the CS1 to CSm signals to the IC chip array in the DRAM of the present invention at the same timing. The WEB signal is the DR of the present invention.
This is a signal for determining the reading of data from the memory cell in the IC chip in the AM and the writing of data to the memory cell. The RASbB signal is a switching timing signal for converting the row address signals A0 to Ai and the column address signals Ai + 1 to Aj from the address multiplexer ADMPX into time series multiplexed signals. And
Further, when one of the RASB (RASB1 to RASBm) signals is selected, the address multiplexer ADM
As the row address signals A0 to Ai are output from the PX, the switching timing of the row address signals A0 to Ai and the column address signals Ai + 1 to Aj is delayed from the RASaB signal.

Next, the relationship between the WEB signal and the data bus driver DBD will be described. Control circuit CNTRL
The WEB signal sent from is applied to the DRAM and the data bus driver DBD of the present invention. For example, the above WE
When the B signal is at a high level, the read mode is set, and the data of the DRAM of the present invention is output and sent to the central processing unit CPU via the data bus driver DBD. At this time, the input data is controlled by the WEB signal so as not to be taken into the DRAM of the present invention from the DBD. When the WEB signal is low level, the write mode is set, and the input data from the central processing unit CPU is input to the data input terminal of the DRAM of the present invention by the data bus driver DB.
The data is applied via D and data is written to the set address. At this time, the data output of the DRAM of the present invention is controlled by the WEB signal so as not to be output from the data bus driver DBD. As described above, by configuring the DRAM IC ARRAY with the DRAM of the present invention, it is possible to realize a memory board that is small in size, low in cost, large in capacity, and reliable in data.

(Embodiment 3) FIG. 16 is a schematic view of an essential part of an IC card using the DRAM of the present invention. The DRAM and the microcontroller of the present invention are mounted on a plastic substrate. The above microcontroller is the D of the present invention.
A RAM control circuit for controlling the operation of the DRAM of the present invention. The internal wiring of the DRAM and the microcontroller of the present invention and the wiring on the plastic substrate are connected to each other. Further, the connector and the wiring on the plastic substrate are electrically connected, and the connector and the interface circuit in the external system are connected. As a result, the IC card can be used as information of various systems. Further, in this embodiment, an example in which the microcontroller as the DRAM control circuit of the present invention is built in the IC card has been shown, but the microcontroller may be formed independently instead of being provided in the IC card. If this IC card is used as a replaceable auxiliary storage medium in a small-sized portable computer system below a workstation like a conventional floppy disk, it is not necessary to rotate the disk, and the overall size and weight of the system can be reduced. In addition, the power consumption can be reduced and a large amount of information can be read and written at high speed, and the processing capability of the entire system is improved.

(Embodiment 4) FIG. 17 is a schematic view of a main part of a computer system using the DRAM of the present invention. This computer system includes a central processing unit CPU as an information device, an I / O bus constructed in the information processing system, a BUS Unit, a memory control unit Memo for accessing a high speed memory such as a main memory or an extended memory.
ry Control Unit, DRAM as main memory, RO storing basic control program
M, a keyboard controller KBDC having a keyboard connected to its tip, and the like. Further, a display adapter as a display adapter is connected to the I / O bus, and a display is connected to the tip of the display adapter. The parallel port Parallel Po is connected to the I / O bus.
Serial port serial for rtI / F, mouse, etc.
Port I / F, floppy disk drive FD
D, a buffer controller HDD buffer for converting HDD I / F from the I / O bus is connected.
In addition, the memory control unit Memory Cont
The expansion RAM and the DRAM as the main memory are connected to the bus from the roll unit. Here, the operation of this computer system will be described. When the power is turned on and the operation is started, the central processing unit CPU first accesses the ROM through the I / O bus to perform initial diagnosis and initial setting. And
A system program is loaded from an auxiliary storage device into a DRAM as a main storage memory. The central processing unit CPU operates to access the HDD to the HDD controller through the I / O bus. And
When the loading of the system program is completed, the processing proceeds according to the processing request of the user. It should be noted that the user proceeds with the work while inputting and outputting the processing by the keyboard controller KBDC and the display adapter Display adapter on the I / O bus. And, if necessary, the parallel port Parallel Port
I / F, serial port Serial Port I /
Utilize the input / output device connected to F. Further, when the main memory capacity of the DRAM as the main memory on the main body is insufficient, the main memory is supplemented by the expanded RAM. If the user wants to read or write files, the user must
Request access to the auxiliary storage device as if the DD were the auxiliary storage device. Then, the file system constituted by the DRAM of the present invention receives it and accesses the file data. Thus, the DR of the present invention
By applying AM to computer systems,
It can be applied to the portable computer system as described above. As a result, it is not necessary to rotate a conventional disk, the overall size and weight of the system can be reduced, the power consumption can be reduced, and a large amount of information can be read and written at high speed. The processing capacity of can be improved. Further, since the conventional disk is replaced by the DRAM of the present invention, impact resistance, which is a problem in a portable computer, can be improved, and reliability in a computer system can be improved.

[0025]

The sensitivity of the differential amplifier of the DRAM is improved, and the number of bit lines that can be connected to one sense amplifier can be increased. Therefore, the number of sense amplifiers can be reduced and the DRAM chip area can be reduced. The reliability of the operation is improved by applying the arc differential amplifier to the amplifier. Further, the size of the memory board using the DRAM as the main storage memory becomes small, so that the cost of the data processing system can be reduced. Further, by using the semiconductor disk device instead of the magnetic disk, it is possible to realize a more compact computer system with improved reliability.

[Brief description of drawings]

FIG. 1 is a schematic diagram of a circuit of a DRAM including a sense amplifier having a circuit for compensating a threshold value of an NMOS transistor and a control circuit thereof according to the present invention.

FIG. 2 is a circuit diagram of a conventional CMOS sense amplifier and an operation waveform diagram thereof.

FIG. 3 is a conventional CMO that compensates a threshold voltage.
6 is a circuit diagram of an S sense amplifier and an operation waveform diagram thereof.

Figure 4 is a diagram showing a relationship between the variation in the amount of noise and the coupling capacitance due to variations in the figures and the threshold voltage V _th indicates a relationship between the noise amount and the coupling capacitance due to variation in the threshold voltage V _th.

FIG. 5 is a schematic diagram of a layout of a conventional DRAM.

FIG. 6 is a quarter sense amplifier in a DRAM to which a CMOS sense amplifier for compensating a threshold voltage V _th is applied.
The figure which compared the noise amount in the DRAM made into and the conventional DRAM.

FIG. 7 is an operation waveform diagram of a DRAM including a sense amplifier having a circuit for compensating a threshold value of an NMOS transistor and a control circuit thereof according to the present invention.

FIG. 8 is a schematic diagram of a circuit of a DRAM including a sense amplifier having a circuit for compensating a threshold value of a PMOS transistor of the present invention and a control circuit thereof.

FIG. 9 is an operation waveform diagram of a DRAM including a sense amplifier having a circuit for compensating a threshold value of a PMOS transistor and a control circuit thereof according to the present invention.

FIG. 10 is a layout diagram when a memory cell structure is used for a capacitor in the sense amplifier or main amplifier of the present invention.

FIG. 11 is a layout diagram of the DRAM of the present invention.

FIG. 12 is a schematic diagram of a circuit of a DRAM including a main amplifier having a circuit for compensating a threshold value of an NMOS transistor and a control circuit thereof according to the present invention.

FIG. 13 is an operation waveform diagram of a DRAM including a main amplifier having a circuit for compensating a threshold value of an NMOS transistor and a control circuit thereof according to the present invention.

FIG. 14 is a functional block diagram of a DRAM using a sense amplifier and / or a main amplifier of the present invention.

FIG. 15 is a functional block diagram of a memory board using the DRAM of the present invention.

FIG. 16 is a functional block diagram of an IC card using the DRAM of the present invention.

FIG. 17 is a functional block diagram of a computer system using the DRAM of the present invention.

[Explanation of symbols]

BL, BLB ... bit line, WL ... word line, CNTR
L1, 2 ... V _th control circuit, SA ... Sense amplifier, PC
... Precharge circuit, ADB ... Address buffer, C
D, CDB ... Common data line, DCR ... Decoder, M
AT, MAB ... Main amplifier input / output line, DRIVE ...
Driver, OB ... Output buffer, MA ... Main amplifier, SWT switch, CPU ... Central processing unit, I / F.
..Interface circuits, RAR ... Row address receivers, CAR ... Column address receivers, ADR
..Address receiver, DCR ... Decoder, RAS-
CNTRL ... RAS control circuit, CNTRL ...
Control circuit, DBD ... Data bus driver, R
EFREQ ... Refresh request signal, MS ... Memory start signal, REGRN ... Refresh instruction signal, AD
MPX ... Address multiplexer, DP ... Display, FDD ... Floppy disk drive, FD ... Flappy disk, file M ... File memory,
KB ... keyboard, KBDC ... keyboard controller, HDD ... hard disk drive, main M.
..Main memory

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Hideyuki Miyazawa 2326 Imai, Ome-shi, Tokyo Hitachi, Ltd. Device Development Center

Claims (4)

[Claims] 1. A plurality of bit line pairs, a plurality of word lines,
A dynamic RAM having a differential amplifier having a MOS transistor pair and a memory array including a memory cell having a first capacitor for storing information, wherein a second RAM is provided on the source side of the MOS transistor pair in the differential amplifier. A capacitor and a second MOS transistor are provided, the second capacitor has the same structure as the first capacitor of the memory cell, and the counter electrodes of the second capacitors provided facing each other are connected and applied to the counter electrode. A dynamic RAM characterized in that capacitive coupling is performed on the source side of the MOS transistor by controlling a voltage. 2. A differential MOS transistor for switching is provided between the differential amplifier and the memory array to separate the memory array and the differential amplifier from each other. Dynamic RAM. 3. The dynamic RAM according to claim 1, wherein capacitive coupling is performed by making the voltage applied to the counter electrode of the second capacitor smaller than the power supply voltage. 4. A bus, a peripheral device control unit, a main memory and its control unit, and an SR as a backup memory.
AM and its control unit, a power supply unit for supplying power to internal circuits, a ROM in which a program is stored,
A data processing system comprising a display system including a VRAM and a central processing unit for controlling operation timing of each memory by forming a signal for controlling each memory, wherein the peripheral device control section is The display system is connected to an external storage device and an input device, and the display system is connected to an output device to display stored information in the display system, and the main storage memory includes a plurality of bit line pairs and a plurality of bit line pairs. A dynamic RAM having a word line, a differential amplifier having a MOS transistor pair, and a memory array including a memory cell having a first capacitor for storing information, wherein the MO in the differential amplifier is
A second capacitor and a second MOS transistor are provided on the source side of the S-transistor pair, and the second capacitor has the same structure as the first capacitor of the memory cell, and the counter electrodes of the second capacitors provided opposite to each other are provided. A data processing system, characterized in that the data processing system is a dynamic RAM which is connected and controls the voltage applied to the counter electrode to perform capacitive coupling on the source side of the transistor pair.