JP3293219B2 - Dynamic RAM and its data processing system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential amplifier, and more particularly, to a technique effective when applied to a data processing system using a large-capacity dynamic RAM as a main memory.

[0002]

2. Description of the Related Art Generally, in the process of forming a transistor, the threshold voltage _Vth of the transistor varies depending on each transistor. For this reason, a dynamic RAM (hereinafter referred to as DR) which is used as a memory or built in like a microcomputer or the like is used.
In the case of a transistor generally used in AM, a switching speed of a MOS transistor constituting a differential amplifier such as a sense amplifier and a main amplifier varies, so that a malfunction easily occurs. FIG.
2A shows a circuit diagram of a conventional CMOS sense amplifier as an example of the differential amplifier, and FIG. 2B shows an operation waveform diagram of the sense amplifier. Here, in FIG.
This problem will be described with reference to the operation waveform diagram of FIG. 2B, taking as an example a case where the threshold voltage _Vth of the NMOS transistor Q1 is low based on the threshold voltage _Vth of the MOS transistor Q2. Now, it is assumed that a signal amount has been output from the memory cell to the bit line BL. In the operation of the CMOS sense amplifier, a high-level voltage is applied to the input terminal PP and a low-level voltage is applied to the input terminal PN, so that a signal is amplified to the bit line BL. At this time, if there is no variation in the threshold voltage _Vth , the N
The MOS transistor Q2 is connected to the NMOS transistor Q
The signal is turned on prior to 1 and the signal is amplified by a normal CMOS sense amplifier. However, this CMOS
In the sense amplifier, the NMOS transistor Q1
For the low threshold voltage V _th, the switching speed of the NMOS transistor Q1 becomes faster.
Then, the NMOS transistor Q1 is an NMOS transistor.
It will be turned on before the transistor Q2. For this reason, as shown in FIG.
Since the potential of L becomes low level first, the bit line BLB becomes high level and input or output data is inverted, a sense amplifier or a main amplifier using a MOS transistor having a variation in threshold voltage. Malfunctions occur in memories such as DRAMs including

In order to solve such a problem, M
There has been proposed a differential amplifier in which a circuit for controlling variation in the threshold voltage _Vth of an OS transistor is incorporated. FIG. 3A shows, as an example, a C composed of MOS transistors having a variation in threshold voltage.
FIG. 3B is a circuit diagram in the case where a MOS sense amplifier is applied to a DRAM, and FIG. 3B shows an operation waveform diagram of this circuit. In this CMOS sense amplifier, a capacitor C is connected to each source of NMOS transistors Q1 and Q2 constituting an N-type sense amplifier NSA in a conventional CMOS sense amplifier.
1, C2 and switch MOS transistors Q5, Q6
Is provided. The gates of the switch MOS transistors Q5 and Q6 and the gate of the transfer MOS transistor Q4 are controlled by a switching SW signal. The coupling operation of the capacitors C1 and C2 is controlled by the coupling COM signal. Next, the operation of this circuit will be described below with reference to FIG. First, the precharge PCB signal is L
The low level turns off the NMOS transistors Q7, Q8, and Q9, ending the precharge operation and ending the compensation operation for the threshold voltage _Vth . Thereafter, when the COM signal is set to the low level, the coupling operation ends.
Thereafter, the switch MOS transistors Q5, Q6, and Q4 are turned ON by setting the SW signal to High level.
Then, the data is amplified by the N-type sense amplifier NSA. When the sense amplifier control PPB signal is set to Low level, the PMOS transistor Q10
Is turned on, the P-type sense amplifier PSA is activated, and the signal amplified in the CMOS sense amplifier constituted by the N-type sense amplifier NSA and the P-type sense amplifier PSA is transmitted to the bit lines BL and BLB. . In this way, in the DRAM, the potential of the _Vth difference is applied in advance to the nodes on the source side of the NMOS transistors Q1 and Q2, and pre-sense is performed by coupling, whereby normal operation as a differential amplifier is compensated.

Here, FIG. 4A shows the relationship between the amount of noise due to the variation of the threshold voltage _Vth and the coupling capacitance. In this graph, the horizontal axis shows coupling capacitance / bit line capacitance as parameters, and the vertical axis shows noise amount (mV) due to variation in threshold voltage _Vth as a parameter. As shown in the figure, if the coupling capacitance / bit line capacitance is small, noise increases, so that the coupling capacitance / bit capacitance must be increased to some extent. However, in the CMOS sense amplifier shown in FIG. 3A, there is no study on making the coupling capacitance sufficiently larger than the bit line capacitance. Further, similarly, the switch MOS transistor Q in FIG.
5 and Q6, a malfunction due to the variation of the threshold voltage _Vth is a concern. Here, FIG. 4B shows the relationship between the noise amount and the variation in the coupling capacitance due to the variation in the threshold voltage _Vth . In this graph, the horizontal axis represents the coupling capacitance variation (%) as a parameter, and the vertical axis represents the noise amount (mV) due to the variation in the threshold voltage _Vth.
Is shown as a parameter, and the coupling capacitance / bit line capacitance shown in FIG. 3A is changed for each case. As shown in the figure, at a constant coupling capacitance variation, the larger the coupling capacitance / bit line capacitance, the more the noise amount due to the variation in the threshold voltage _Vth can be reduced. Further, as shown in FIG. 4B, as the coupling capacitance becomes larger with respect to the bit line, even when the coupling capacitance varies, the threshold voltage _Vth is compensated by the threshold voltage _Vth. The amount of noise due to the variation can be reduced. However, in the conventional method, the means for obtaining the coupling capacitance has not been studied, so that the ratio of the coupling capacitance to the bit line capacitance is small. For example, when the coupling capacitance is formed by a MOS transistor, the capacitance value depends on the voltage between the electrodes, so that there is a limit in reducing the amount of noise. When the amount of signal is small, it is difficult to avoid malfunction.
Further, when the voltage amplitude during the coupling operation is large, NM
Since the node on the source side of the OS transistor Q1 has a negative potential, there is a problem that minority carriers are generated. Thus, the conventional threshold voltage V _th
A sense amplifier of the type that compensates for cannot be applied in practical use except for a conventional DRAM having a small number of bits. Further, in the conventional sense amplifier, the coupling capacitance value must be larger than the bit line capacitance, and the main amplifier has not been studied similarly, and no shared MOS transistor or switch MOS transistor is provided. In this case, a sufficiently large coupling capacitance is required for both the bit line capacitance outside the sense amplifier and the bit line capacitance inside the sense amplifier, and the chip area increases.

On the other hand, in recent years, an increase in chip area due to an increase in the capacity of a semiconductor memory, particularly a DRAM, has become a problem, and this has the problem of increasing the cost. FIG. 5 shows an example of the conventional DRAM in the long side direction 2.
The layout diagram for every 56 bits is shown. Since the number of bits increases because the sense amplifier is laid out at the center of the memory array, the number of sense amplifiers also increases, so that the occupation ratio of the sense amplifier to the chip area increases, and the chip area becomes extremely large. . As described above, in the conventional layout, the semiconductor memory has a large capacity, so that the chip area of the semiconductor memory and the microcomputer including the semiconductor memory increases, the cost increases, and the memory board becomes larger and the cost increases. The problem is that the cost of the main memory increases when used as a data processing system requiring a large capacity. For this reason, even if the number of bits connected to one sense amplifier is increased, reduction in chip area and reduction in cost are currently being studied by the present inventors. FIG. 6 shows an example of a normal 16M DRAM.
7 shows a comparison between the signal amount of the 16-M DRAM and the signal amount when the number of bit lines for one sense amplifier is increased.
In the 16MDRAM, the number of bits connected to one sense amplifier is 256 bits, but the case where the number of bits is quadrupled will be described. In this case, the number of bits connected to one sense amplifier is 1024,
The signal amount output from the memory cell is reduced to about 1/4. Here, the signal amount at this time is 87 mV, and the description will be continued below. In order to operate this DRAM normally, the amount of noise with respect to the variation of the threshold voltage _Vth must be 8 mV.
Must be reduced to However, in the conventional method, the method of obtaining the coupling capacitance with respect to the bit line capacitance was not studied, so that 44 mV, which was the noise due to the variation of the threshold voltage _Vth in the transistors constituting the sense amplifier, was increased by four times the number of bits. In this case, there is a problem that the noise cannot be reduced to the noise target of 8 mV. Therefore, when the number of bits connected to one sense amplifier is quadrupled, the coupling capacitance / bit line capacitance is reduced to about 1/4 as shown in the graph of FIG. This coupling capacity needs to be increased about four times. This increases the area for coupling capacitance. For this reason, it is necessary to take measures to reduce the bit line capacitance. However, in the DRAM of FIG. 3, since a circuit for separating the CMOS sense amplifier and the bit line portion is not provided, the bit line capacitance increases. Would. Further, the capacitor C
1 With the transistor capacitance at, C2, has a large voltage dependency of the capacitance, the coupling capacitance / bit line capacitance is reduced, the noise can not be reduced, the threshold voltage V _th of the noise of the total signal amount The ratio occupies more than half, and when the noise due to coupling and leakage current is taken into consideration, the DRAM does not operate. In such a DRAM having a large number of bits for one sense amplifier from two points, this sense amplifier cannot be used, and as a result, in a conventional differential amplifier that controls the threshold voltage of a MOS transistor, The problem of data inversion cannot be solved.

[0006]

SUMMARY OF THE INVENTION In a DRAM differential amplifier, the coupling capacitance is improved to compensate for variations in the threshold voltage of MOS transistors, and the main memory in a low-cost and large-capacity data processing system. It is an object to provide a DRAM applicable to a memory and a data processing system thereof.

[0007]

SUMMARY OF THE INVENTION In a dynamic RAM having a differential amplifier having a pair of MOS transistors and a memory array including a memory cell having a first capacitor for storing information, a MOS transistor in the differential amplifier is provided.
A second capacitor and a second MOS transistor are provided on the source side of the transistor pair, respectively, and the second capacitor has the same structure as the first capacitor of the memory cell, and is connected to a counter electrode of the second capacitor provided opposite to the memory cell. Then, capacitive coupling is performed by controlling the voltage applied to the counter electrode.

[0008]

[Function] It is possible to increase the coupling capacitance with respect to the bit line capacitance or the coupling capacitance with respect to the input / output line of the main amplifier, and to prevent the minority carrier from flowing from the opposite electrode node due to the coupling, thereby improving the sensitivity of the sense amplifier and / or the main amplifier. In addition, malfunction can be prevented. Therefore, 1
The number of bit lines connected to the two sense amplifiers can be increased, the number of the sense amplifiers can be reduced, the chip area of the DRAM can be reduced, and the size and cost of the data processing system can be reduced. I can do it.

[0009]

【Example】

(Embodiment 1) FIG. 1 shows a partial circuit diagram of a DRAM including a sense amplifier of the present invention and its control circuit, and FIG. 7 shows operation waveforms thereof. This embodiment is described as compensating for variations in the threshold voltage of the NMOS transistor. First, the configuration of the circuit diagram of FIG. 1 will be described below. A plurality of bit lines BL and BLB and a plurality of word lines WL are formed, and at the intersection of the bit line BL and the word line WL, as shown in the memory cells 1 and 2 connected to the word lines WL1 and WL2. A plurality of memory cells are configured. Since these memory cells are DRAMs, the memory cells 1 and 2 respectively have NMOS transistors Q1 and Q2.
0, a capacitor C3, an NMOS transistor Q19 and a capacitor C4. Also, this DR
When the AM is formed in a two-layer wiring structure, the Y select line YS and the common data lines CD and CDB are connected to the word line W
It is laid out on the right side of L2. For this reason, writing of the inversion information into the memory cell is delayed. To prevent this, the PMOS transistor Q is used as a sense amplifier.
1 and Q2, the P-type sense amplifiers PSA1 and PM
The OS transistors Q3 and Q4 form a P-type sense amplifier PSA2. Also, the NMOS transistor Q
5, Q6 constitute an N-type sense amplifier NSA,
Between the P-type sense amplifier PSA1 and the N-type sense amplifier NSA, NMOS transistors Q9, Q12, Q
13 constitutes a precharge circuit PC. In order to share the P-type sense amplifiers PSA1 and PSA2 and the N-type sense amplifier NSA, the NMOS transistor Q
14, Q15 and NMOS transistors Q16, Q1
By using 7 as a shared MOS transistor, the left and right memory arrays can be selected. Here, since the threshold voltage _Vth of the NMOS transistor Q5 is assumed to be low based on the threshold voltage _Vth of the NMOS transistor Q6, the voltage of the threshold voltage _Vth difference is compensated for the NMOS transistor Q5. Circuit is configured. This sense amplifier is based on the NMOS
V _{th is previously connected to} the node on the source side of the transistor Q5.
Normal operation is assured by giving a potential difference and performing preamplification by coupling using the capacitors C1 and C2.

The data read operation after the data write operation of the DRAM will be described below with reference to the operation waveform diagram of FIG. After the data write operation, the bit line BL is amplified to a high level and the bit line BLB is amplified to a low level. Here, the word line WL1 is set to a low level. As a result, the NMOS transistor Q10 in the memory cell 1 is turned off,
The state is such that charge is held in the capacitor C3. Thereafter, when the PPB signal is set to the high level, the PMOS transistor Q24 is turned off, and the
The NMOS transistor Q26 is turned off when the signal goes low. Further, when the PN signal is L
, and the NMOS transistor Q27 is turned off.
By this, the amplification operation of the pair of bit lines BL and BLB by the CMOS sense amplifier is completed. afterwards,
The PCB signal is set to the high level, the NMOS transistors Q11 and Q18 are turned on, the NMOS transistors Q9, Q12 and Q13 are turned on, and the precharge circuit PC operates to operate the bit line pair BL and BLB.
The potential is set to 1/2 _Vcc . Further, when the CSS signal is Hi
The gh level turns on the NMOS transistors Q22 and Q23. As a result, the common source lines of Q1, Q2 and Q3, 4 of the P-type sense amplifier PSA1 and the common source lines of Q7, Q8 of the NSA are short-circuited. At this time, the NMOS transistors Q6 and Q
8, Q28 and currents flowing through Q5, Q7 and Q28 keep nodes a and b at a potential lower than 1/2 _Vcc . Thereafter, the SW signal is set to Low level and the PNL signal is set to Low level,
Control circuit CNTR for compensating for threshold voltage _Vth difference
L1 operates. In this operation, first, the SW signal is Lo.
The NMOS transistors Q7 and Q8 are turned off by setting to w level, and the NMOS transistor Q28 is turned off by setting PNL to LoW level.
Is done. At this time, a current for charging the nodes a and b flows through the NMOS transistors Q5 and Q6, until the potential of the node a becomes lower than 1/2 _Vcc by _{Vth of the} NMOS transistor Q5, and the potential of the node b becomes 1/2 V. _The current flows until the potential becomes lower than _Vcc by _{Vth of the} NMOS transistor Q6.
A potential difference between them occurs by a threshold voltage _Vth difference. Prior to the next read operation, the shared signal SHR is set to Low.
The bit line which is not selected (in this case, the memory array on the right side) is cut off, and the CSS signal is set to the Low level. Terminate. After that, the level of the PCB signal is changed to the Low level, thereby completing the compensation operation for the threshold voltage _Vth . After that, the word line WL1 becomes High.
By setting the level, the memory cell 1 is selected, and a signal as stored data is extracted from the memory cell 1 including the NMOS transistor Q10 and the capacitor C3. Thereafter, when the shared signal SHL is set to Low level, the shared MOS transistors Q14 and Q15 are turned off, and the left bit line pair BL and BLB is disconnected. After that, when the COM signal is set to High, the NMOS
The transistor Q26 is turned on, and a pre-sense operation is performed. At this time, by using a fixed volume of the same structure as the memory cell in the coupling capacitance, by changing to 0V from the counter electrode of the coupling capacitor HVC2 (1 / 2V _cc), the potential difference between the bit lines BL0, BL0B Can be bigger. Here, the same object can be achieved by fixing the counter electrode of the coupling capacitor to a potential lower than the power supply voltage, not limited to 0V. Further, when the PN signal and the PNL signal are set to the High level, the NMOS transistors Q27 and Q28 are turned on. Thereafter, when the SW signal is set to the high level, the NMOS transistors Q7 and 8 are turned on.
And the PPB signal is set to Low level,
The PMOS transistor Q24 is turned on, and the potential of the common source of the sense amplifier is set to Low on the NMOS transistor side.
The level of the PMOS transistor is set to High level to latch the potential difference between the pair of bit lines BL0 and BL0B. Further, thereafter, the shared signals SHR, SH
When L is set to High level, the signal amplified in the sense amplifier is transmitted to the bit line BL. And
By setting the YS signal to the high level, the NMO
S transistors Q20 and Q21 are turned on, and a signal is transmitted to common data lines CD and CDB.

FIG. 8 is a partial circuit diagram of a DRAM including a sense amplifier to which the present invention is applied and its control circuit, and FIG. 9 shows operation waveforms. This embodiment will be described as compensating for variations in the threshold voltage of the PMOS transistor. First, the configuration of the circuit diagram of FIG. 8 will be described below. A plurality of bit lines BL, BLB and a plurality of word lines WL
At the intersection of the bit line BL and the word line WL, a plurality of memory cells are formed as shown in the memory cells 1 and 2 connected to the word lines WL1 and WL2. Since these memory cells are DRAMs, each of the memory cells 1 and 2 includes an NMOS transistor Q10 and a capacitor C3, and an NMOS transistor Q19 and a capacitor C4, respectively. When this DRAM is formed with a two-layer wiring structure, the Y select line YS and the common data lines CD, CDB
Are laid out on the right side of word line WL2. For this reason, writing of the inversion information to the memory cell is delayed.
N-type sense amplifier NS by transistors Q1 and Q2
N1 by A1 and NMOS transistors Q3 and Q4
A type sense amplifier NSA2 is configured. Also, PMOS
P-type sense amplifier PS by transistors Q5 and Q6
A, and an NMOS transistor Q is connected between the P-type sense amplifier PSA and the N-type sense amplifier NSA1.
A precharge circuit PC is constituted by 9, Q12 and Q13. In order to share the P-type sense amplifier PSA and N-type sense amplifiers NSA1 and NSA2,
By using the transistors Q14 and Q15 and the NMOS transistors Q16 and Q17 as shared MOS transistors, the left and right memory arrays can be selected. Here, based on the threshold voltage V _th of PMOS transistor Q6, to the threshold voltage V _th of PMOS transistor Q5 is low, to compensate for the voltage of the threshold voltage V _th difference in the PMOS transistor Q5 Circuit is configured. This sense amplifier,
A normal operation is guaranteed by applying a potential of _Vth difference in advance to a node on the source side of the PMOS transistor Q5 and performing preamplification by coupling.

The data read operation after the data write operation of the DRAM will be described below with reference to the operation waveform diagram of FIG. After the data write operation, the bit line BL is amplified to a high level and the bit line BLB is amplified to a low level. Here, the word line WL1 is set to a low level. As a result, the NMOS transistor Q10 in the memory cell 1 is turned off,
The state is such that charge is held in the capacitor C3. Thereafter, when the PN signal is set to the Low level, N
The MOS transistor Q24 is turned off, and the PMOS signal Q26 is turned off by setting the COM signal to the high level. Further, when the PP signal is Hig
to the h level, and the PMOS transistor Q27 is turned off.
This completes the operation of amplifying the pair of bit lines BL and BLB by the CMOS sense amplifier. Then, P
The CB signal is set to the high level, the NMOS transistors Q11 and Q18 are turned on, the NMOS transistors Q9, Q12 and Q13 are turned on, and the precharge circuit PC operates, so that the potentials of the bit line pair BL and BLB are reduced to 1 / 2V. _cc . Further, when the CSS signal is Hig
The NMOS transistor Q
22, Q23 are turned ON. As a result, Q1, Q2 of the N-type sense amplifier NSA1 and Q3,
4 and the common source lines Q7 and Q8 of the PSA are short-circuited. At this time, the nodes a and b are kept at a potential higher than 1/2 _Vcc by the current flowing through the PMOS transistors Q28, Q7, Q5 and Q28, Q8, Q6. Thereafter, the control signal CNTRL1 for compensating the threshold voltage _Vth operates by setting the SW signal to the high level and the PPLB signal to the high level. In this operation, first, when the SW signal is set to the high level, the PMOS transistors Q7 and Q8 are turned off, and the PPLB is set to the high level.
By setting the level to the h level, the PMOS transistor Q28 is turned off. At this time, the current discharging nodes a and b through the PMOS transistors Q5 and Q6 becomes
Node a is at a potential higher than 1/2 _Vcc by Vth of PMOS transistor Q5, and node b is at 1 / _Vcc.
The nodes a and b flow by flowing until the potential becomes higher than _Vcc by Vth of the PMOS transistor Q6.
A potential difference between them occurs by a threshold voltage _Vth difference. Prior to the next read operation, the shared signal SHR is set to Low.
The bit line which is not selected (the memory array on the right side in this case) is cut off and the CSS signal is set to Low level, thereby terminating the common source short circuit between the N-type sense amplifiers NSA1 and NSA1 and PSA. Let it. At the same time, the compensation operation of the voltage corresponding to the threshold voltage V _th is completed by setting the PCB signal to the low level. Thereafter, when the word line WL1 is set to the high level, the memory cell 1 is in the selected state,
The signal as the stored data is the NMOS transistor Q
Memory cell 1 composed of capacitor 10 and capacitor C3
Taken out of After that, the shared signal SHL becomes L
By setting it to the low level, the shared MOS transistors Q14 and Q15 are turned off, and the left bit line pair BL and BLB is disconnected. Thereafter, when the COM signal is set to Low, the PMOS transistor Q26 is turned on, and the pre-sense operation is performed. At this time, a fixed capacitor having the same structure as the memory cell is used as the coupling capacitor, and the counter electrode of the coupling capacitor is connected to the HVC2.
By changing to V _cc from (1 / 2V _cc), it is possible to increase the potential difference between the bit lines BL0, BL0B. Here, the counter electrode of the coupling capacitor is not limited to V _cc, can achieve the same purpose may by secured to the lower potential than the power supply voltage. Furthermore, the above PP
When the B signal and the PPLB signal are set to Low level, the PMOS transistors Q27 and Q28 are turned on. Thereafter, when the SW signal is set to Low level, the PMOS transistors Q7 and 8 are turned on, and the PN
When the signal is set to the high level, the NMOS transistor Q24 is turned on, and the potential of the sense amplifier common source is set to the high level on the PMOS transistor side and set to the low level on the NMOS transistor side to latch the potential difference between the pair of bit lines BL0 and BL0B. . Further, thereafter, when the shared signals SHR and SHL are turned ON, the signal amplified in the sense amplifier is transmitted to the bit line BL. When the YS signal goes high, the NMOS transistors Q20, Q2
1 is turned on, and a signal is transmitted to the common data lines CD and CDB.

FIG. 10A is a schematic view of a main part of a sectional structure of capacitors C1 and C2 used as coupling capacitors. This capacitor is formed by a FIN-STC (fin-stacked trench capacitor) structure like the capacitor of the memory cell in the memory array. FIG. 10B shows a FIN-STC in the DRAM of the present invention.
FIG. 3 shows a layout diagram in the case of using. In this case, since a capacitor having the same structure as the memory cell is used,
Coupling capacitance can be obtained with a smaller area than the transistor capacitance. This is advantageous because the increase in chip area can be prevented and the number of steps in the process does not increase. FIG. 10C is a table comparing a case where a MOS capacitor is used as a coupling capacitor of the DRAM of the present invention with a case where a fixed capacitor having the same structure as a memory cell is used. When a MOS capacitor is used, not only does the chip area greatly increase, but also as described above, the voltage dependency of the capacitor increases, and the amount of noise with respect to the coupling capacitance / bit line capacitance becomes unstable. The threshold voltage V
_{It is} also difficult to control the _th compensation operation. On the other hand, when a fixed capacitor having the same structure as the memory cell is used, an increase in the chip area can be prevented as described above, the voltage dependency of the capacitor is small, and the noise amount with respect to the coupling capacitance / bit line capacitance is also reduced. It is stable and the control of the compensating operation of the threshold voltage _Vth becomes easy. As described above, in the present invention, the same structure as that of the memory cell is used as the coupling capacitance, the shared MOS transistor is provided to disconnect the sense amplifier from the bit line, and the coupling operation in the threshold voltage control circuit is performed as described above. / 2V _cc to 0V
To compensate for the threshold voltage _Vth . Also, a coupling capacitance is formed in a similar manner for a differential amplifier in a main amplifier described later.

FIG. 11 is a schematic diagram showing a main part of a layout of a DRAM of the present invention. In the DRAM of the present invention, the number of bits that can be connected to one sense amplifier can be increased, the variation in the threshold voltage of the sense amplifier can be compensated, and the normal operation of the sense amplifier can be maintained. A large-capacity and small DRAM can be realized.

Next, FIG. 12 shows a circuit diagram and FIG. 13 shows an operation waveform diagram when the differential amplifier is applied to a main amplifier of a DRAM. This embodiment will be described as an example in which the variation of the threshold voltage of the NMOS transistor is compensated. First, the configuration of the circuit diagram of FIG. 11 will be described below. In this embodiment, as the main amplifier, a P-type main amplifier PMA1 is formed by the PMOS transistors Q1 and Q2, and a P-type main amplifier PMA2 is formed by the PMOS transistors Q3 and Q4. An N-type main amplifier NMA is constituted by the NMOS transistors Q5 and Q6, and is provided between the P-type main amplifier PMA1 and the N-type main amplifier NMA.
A precharge circuit PC is constituted by the NMOS transistors Q9, Q12, and Q13. By using the NMOS transistors Q16 and Q17 as switch MOS transistors, the common data lines CD and
The connection between the CDB and the main amplifier input / output lines MAT, MAB can be controlled. Here, since the threshold voltage _Vth of the NMOS transistor Q5 is assumed to be low based on the threshold voltage _Vth of the NMOS transistor Q6, the voltage of the threshold voltage _Vth difference is compensated for the NMOS transistor Q5. Circuit is configured. In this main amplifier, a normal operation is assured by applying a potential of _Vth difference in advance to a node on the source side of the NMOS transistor Q5 and performing preamplification by coupling using the capacitors C1 and C2.

The data read operation after the data write operation of the DRAM will be described below with reference to the operation waveform diagram of FIG. After the data write operation, the main amplifier input / output line MAT is amplified to a high level, and the main amplifier input / output line MAB is amplified to a low level. Here, the Y select line YS is set to a low level. Thereafter, when the MPPB signal is set to High level, the PMOS transistor Q24 is turned off,
When the MCOM signal is set to Low level, NM
The OS transistor Q26 is turned off. Furthermore, MP
The N signal is set to Low level, and the NMOS transistor Q
By turning off 27, the amplification operation of the main amplifier input / output line pair MAT, MAB by the main amplifier is terminated. Thereafter, the MPCB signal is set to the high level, the NMOS transistors Q11, Q18 are turned on, the NMOS transistors Q9, Q12, Q13 are turned on, and the precharge circuit PC is operated, whereby the main amplifier input / output line pair MAT, MAB is turned on. potential 1 / 2V _cc
It is said. Further, by setting the MCSS signal to the high level, the NMOS transistors Q22 and Q23
Is turned on. This allows the P-type main amplifier P
Common source lines of Q1, Q2 and Q3, 4 of MA1 and N
The common source lines of MA Q7 and Q8 are short-circuited.
At this time, currents flowing through the NMOS transistors Q6, Q8, Q28 and Q5, Q7, Q28 cause the nodes a,
b is held at a potential lower than 1/2 _Vcc . Then M
When the SW signal is set to the low level and the MPNL signal is set to the low level, the control circuit CNTRL1 for compensating for the threshold voltage _Vth difference operates. This operation is performed by first setting the MSW signal to Low level, thereby setting the NMOS transistors Q7 and Q8.
Is turned off and MPNL is set to the Low level, whereby the NMOS transistor Q28 is turned off.
At this time, a current for charging the nodes a and b flows through the NMOS transistors Q5 and Q6.
Than 2V _cc to a Vth of only low potential of the NMOS transistors Q5, also the node b is 1 / 2V _cc above by more current flows until the Vth of only low potential of the NMOS transistor Q6 nodes a, between b Is generated by the threshold voltage _Vth difference. Prior to the next read operation, the input / output IOC signal is set to Low level, and the unselected main amplifier input / output lines MAT, M
AB and the common data lines CD and CDB are separated,
By setting the MCSS signal to a low level, the N-type main amplifier NMA signal and PMA1, PMA1
Terminate the common source short circuit of A2. At the same time, M
By setting the PCB signal to Low level, the compensation operation for the threshold voltage _Vth is completed. Then Y
When the select line YS is set to High level, the common data lines CD and CDB are activated and data is taken out. Thereafter, when the input / output signal IOC is set to Low level, the switch MOS transistors Q16 and Q17 are turned off, and the left main amplifier input / output line pair MAT and MAB is disconnected from the common data lines CD and CDB. Thereafter, the MCOM signal is set to High, so that the NMOS transistor Q26 is turned ON.
Then, a pre-sense operation is performed. At this time, a fixed capacitor having the same structure as that of the memory cell is used as the coupling capacitor, and the counter electrode of the coupling capacitor is connected to HVC2 (1/2 V).
_cc ), the potential difference between the main amplifier input / output lines MAT and MAB can be increased. Here, the same object can be achieved by setting the opposite electrode of the coupling capacitor to a potential lower than the power supply voltage, not limited to 0V. Further, by setting the MPN signal and the MPNL signal to the high level, the NMOS transistors Q27 and Q28 are set to the high level. Thereafter, when the MSW signal is turned on, the NMOS transistors Q7 and 8 are turned on, and M
When the PPB signal is set to Low level, PMO
When the S transistor Q24 is turned on, the potential of the sense amplifier common source is set to the Low level on the NMOS transistor side and set to the High level on the PMOS transistor side to latch the potential difference between the main amplifier input / output line pair MAT and MAB. Further, thereafter, when the input / output signals MAT and MAB are turned on, the signal amplified in the main amplifier is transmitted to the main amplifier input / output line MAT. And Y
When the select YS signal is set to the high level, the NMOS transistors Q20 and Q21 are turned on,
Signals are transmitted to common data lines CD and CDB. In this embodiment, the case where the threshold voltage of the NMOS transistor is compensated is described. However, the same can be applied to the case where the threshold voltage of the PMOS transistor is compensated. Further, it is possible to provide a circuit for compensating the threshold voltage in the sense amplifier and the main amplifier at the same time, and it is possible to maintain the reliability as a DRAM. Here, when three-layer wiring is used, FIGS.
In FIG. 12, a precharge MOS transistor Q1
1 and Q18 become unnecessary, and the Y select line and the switch MOS transistors Q20 and Q21 and the common data line C
Since D and CDB can be arranged beside the NMOS transistors Q1 and Q2, they do not affect the speed of writing the inverted information, and therefore, in FIGS. PSA
2, the N-type sense amplifier constituted by the NMOS transistor can be omitted in FIG.

FIG. 14 shows a D to which the differential amplifier of the present invention is applied.
FIG. 2 shows a functional block diagram of a RAM. First, the data write / read operation of this DRAM will be described. First, a data write operation to a memory cell is performed by the input / output circuit I / O.
Data is externally input to / O, and thereafter, when the write enable signal WEB becomes Low, the switch SWT is turned off and the connection with the main amplifier MA is cut off. On the other hand, a row address strobe signal RAS as a clock signal generated from the central processing unit CPU
B, the column address strobe signal CASB and an externally designated address signal
Input to DB. Then, the bit line BL is selected via the Y-decoder YDCR, and the transfer MOS transistor is turned on by applying a voltage to the gate electrode of the transfer MOS transistor to transfer data, and the input data is amplified by the sense amplifier SA. . On the other hand, the address signal input to the address buffer ADB is pre-decoded in synchronization with the above-described clock signal, selects a word line WL via the X decoder XDCR, amplifies the signal by the word driver WLDRIVE, and outputs the designated address. Data input from outside is written to the memory cell. The operation of reading data from a memory cell is described below. The clock signal RAS generated from the central processing unit CPU
B, CASB and an externally designated address signal are input to the address buffer ADB. On the other hand,
When the enable signal WEB becomes High level and the switch SWT is turned on, the transfer M
The OS transistor and the main amplifier MA are connected.
Then, the bit line BL is selected via the Y decoder YDCR and the transfer MOS transistor is turned on.
To turn on the output buffer OB. On the other hand, the address signal input to the address buffer ADB is predecoded, and is input to the X decoder to select the word line WL and to select the word driver WLd.
The signal is amplified by the live. As a result, the stored data is read from the memory cell at the address specified from the outside, and the data is read out from the bit line B.
L is read out through the transfer MOS transistor. Then, since the switch SWT is ON, the data is amplified by the main amplifier MA, and the data is read from the input / output circuit I / O from the output buffer OB. In this manner, data is read from the memory and data is written to the DRAM of the present invention. Whether or not to use a differential amplifier provided with a circuit for compensating a threshold value for each of the sense amplifier SA and the main amplifier MA in the DRAM can be arbitrarily set. When the differential amplifier of the present invention is applied as a sense amplifier, the DRAM has a large number of bits, and even if the DRAM has a large capacity, malfunction such as data inversion hardly occurs, and the area occupied by the sense amplifier SA decreases. Therefore, the chip area can be significantly reduced and the layout efficiency can be improved. Also, when the differential amplifier of the present invention is applied as a main amplifier, malfunction can be prevented,
The reliability is greatly improved.

(Embodiment 2) FIG. 15 shows a functional block diagram of a memory board using the DRAM of the present invention. This system comprises a DRAM IC ARRAY and a central processing unit CPU, the above-mentioned DRAM, and an interface circuit I / F for interfacing with the central processing unit CPU. This DRAM IC ARRAY
Are constituted by the DRAM of the present invention in a mounted state. First, the DRAM system and the central processing unit CP
Input / output signals to and from U will be described. Address signals A0 to Ak generated by the central processing unit CPU select addresses of the DRAM of the present invention. The refresh instructing signal REGRNT is a control signal for refreshing the memory information of the DRAM of the present invention. The write enable signal WEB is a data read / write control signal in the DRAM of the present invention. The memory start signal MS is a control signal for starting a memory operation of the DRAM of the present invention. The input / output data D1 to DB on the data bus are transmitted between the central processing unit CPU and the DRAM. Further, the refresh request signal REFR
EQ is a control signal for requesting refresh of memory information of the DRAM of the present invention. The above interface circuit I
/ F, the row address receiver RAR outputs address signals A0 to A transmitted from the central processing unit CPU.
Among k, the address signals A0 to Ai are received and converted into address signals at timings suitable for the operation of the DRAM of the present invention. The column address receiver CAR outputs the address signal Ai + among the address signals A0 to Ak.
1 to AJ are received. Then, the signal is converted into an address signal at a timing suitable for the operation of the DRAM of the present invention. Also,
The address receiver ADR receives the address signals Aj + 1 to Ak among A0 to Ak among the address signals. Then, the signal is converted into an address signal at a timing suitable for the operation of the DRAM of the present invention. Decoder DCR
Causes a chip selection control signal (hereinafter referred to as CS1 to CSm) for selecting a chip of the DRAM of the present invention to be transmitted. RAS control circuit RAS-CNTRL
Causes a chip select signal and a row address fetch signal to be transmitted at a timing suitable for the DRAM operation of the present invention. The address multiplexer ADMPX multiplexes the address signals A0 to Ai and Ai + 1 to Aj in a time series and sends out to the DRAM of the present invention. The data bus driver DBD includes the central processing unit CPU and the DRA of the present invention.
The input and output of data to and from M are switched by the WEB signal. The control circuit CNTRL sends out signals for controlling the address multiplexer ADMPX, the RAS control circuit RAS-CNTRL, the data bus driver DBD, the DRAM of the present invention and the like. Next, the function of the address signal in the DRAM system will be described. The address signals A0 to Ak sent from the central processing unit CPU are separated into two functions in this DRAM system: address signals A0 to Aj and address signals Aj + 1 to Ak. That is, the address signals A0 to Aj are used as row and column address signals of the memory matrix in each chip of the DRAM of the present invention. That is, the address signals A0 to Ai correspond to the IC of the DRAM of the present invention.
Ai + 1 to Aj are designed to be assigned to column selection of the IC chip array for row selection of the chip array.

Next, the circuit operation in the DRAM system will be described. First, address signals A0 to Ai, Ai
+1 to Aj are the row address receivers RAR,
The signal is applied to the address multiplexer ADMPX via the column address receiver CAR. In the address multiplexer ADMPX, when the RASbB signal reaches a certain level, row address signals A0 to Ai are sent out and applied to the address terminals in the DRAM of the present invention. At this time, the column address signals Ai + 1 to Ai + 1
j is not transmitted from the address multiplexer ADMPX. Next, when the RASbB signal goes to the opposite level, the column address signals Ai + 1 to Aj are sent from the address multiplexer ADMPX,
It is applied to the address terminal. At this time, the row address signals A0 to Ai are applied to the address multiplexer ADM.
It is not sent from the PX. In this way, the address signals A0 to Ai and Ai + 1 to Aj are time-series according to the level of the RASbB signal.
AM is applied to the address terminal. The chip selection signals Aj + 1 to Ak mainly select a chip in the DRAM of the present invention through the decoder DCR. Then, the signals are converted into chip selection signals CS1 to CSm and used as a chip selection signal and a row address fetch signal.

Next, an operation of setting an address in a chip in each row of the DRAM of the present invention will be described. First, the row address signals A0 to Ai are applied to all I / Os of the DRAM of the present invention.
It is applied to the address terminal of the C chip. Then RAS
One of the 1B-RASmB signals, for example, RAS
It is assumed that the topmost B ICs are selected when the 1B signal reaches a certain level. At this time, the IC (IC11, IC11,
IC12,..., IC1B) The row address signal A0 is added to the row address of the memory matrix array in the chip.
Ai is applied to the IC before the RAS1B signal. The reason is that if the RAS1B signal is applied before the row address signals A0 to Ai, signals other than the row address signal may be fetched. Next, the column address signals Ai + 1 to Aj are applied to the address terminals of all the IC chips of the DRAM of the present invention. Thereafter, when the CASB signal delayed from the RAS1B signal reaches a certain level, the column address signals Ai + 1 to Aj are taken into the column addresses of the memory matrix array in the uppermost nM, B IC chips. here,
The reason why the column address signals Ai + 1 to Aj are applied to the IC before the CAS signal is the same as the reason described above. The CASB signal functions as a row address signal A0 to Ai or a column address signal Ai + 1 to Ai.
j, which signal is being sent. By the above operation, the nM, B in-chip addresses of the uppermost stage of the DRAM in the present invention are set. Also,
ICs other than the top stage of the DRAM of the present invention are RAS2B-R
The ASmB signal is not selected because it has a level opposite to that of RAS1B.

Next, a data write operation and a data read operation at the set address will be described. The data write and read operations are designed to be determined by the high level or low level of the WEB signal. The data write operation is performed by applying data DI1 to DIB from the central processing unit CPU to the set address when the WEB signal is at a certain level. The read operation is performed by outputting the data Do1 to DoB of the respective addresses, which have been written, when the WEB signal is at the opposite level to the above, in B bits. Control circuit C
The NTRL receives command signals from the central processing unit CPU, that is, the REFGRN signal, the WEB signal, and the MS signal, and receives the CASB signal, the RASaB signal, the RASbB signal,
Transmits WEB signals. The function of these transmitted control signals will be described. The CASB signal is a signal for distinguishing which of the row address signals A0 to Ai or the column address signals Ai + 1 to Aj is sent to each chip in the DRAM of the present invention and a signal for taking in the column address signal of the IC chip. It is. The RASaB signal is a signal for supplying the CS1 to CSm signals to the IC chip array in the DRAM of the present invention at the same timing. The WEB signal is the DR of the present invention.
It is a signal for determining reading of data from a memory cell in an IC chip in the AM and writing of data to the memory cell. The RASbB signal is a switching timing signal for converting the row address signals A0 to Ai and the column address signals Ai + 1 to Aj from the address multiplexer ADMPX into time-series multiplexed signals. And
Further, when one of the RASB (RASB1 to RASBm) signals is selected, the address multiplexer ADM is used.
The switching timing of the row address signals A0 to Ai and the column address signals Ai + 1 to Aj is delayed from that of the RASaB signal so that the row address signals A0 to Ai are output from the PX.

Next, the relationship between the WEB signal and the data bus driver DBD will be described. Control circuit CNTRL
Is applied to the DRAM and the data bus driver DBD of the present invention. For example, the above WE
When the B signal is at a high level, the read mode is set, and the data of the DRAM of the present invention is output and sent to the central processing unit CPU via the data bus driver DBD. At this time, the input data is controlled by the WEB signal so as not to be taken in from the DBD to the DRAM of the present invention. When the WEB signal is at a low level, a write mode is set, and input data from the central processing unit CPU is supplied to the data input terminal of the DRAM of the present invention by the data bus driver DB.
The data is applied through D and data is written to the set address. At this time, the data output of the DRAM of the present invention is controlled by the WEB signal so as not to be output from the data bus driver DBD. As described above, by configuring the DRAM IC ARRAY with the DRAM of the present invention, a small, low-cost, large-capacity memory board with high data reliability can be realized.

(Embodiment 3) FIG. 16 is a schematic view of a main part of an IC card using a DRAM of the present invention. The DRAM and the microcontroller of the present invention are mounted on a plastic substrate. The microcontroller is a D controller of the invention.
A control circuit for a RAM, which controls the operation of the DRAM of the present invention. The internal wiring of the DRAM and the microcontroller of the present invention and the wiring on the plastic substrate are connected to each other. Further, the connector is electrically connected to the wiring on the plastic substrate, and connects the connector to an interface circuit in an external system. Thus, an IC card can be used as information of various systems. Further, in this embodiment, an example in which the microcontroller as the control circuit for the DRAM of the present invention is incorporated in the IC card is shown. However, the microcontroller may be formed independently without being provided in the IC card. If this IC card is used as a replaceable auxiliary storage medium in a small and portable computer system below a workstation like a conventional floppy disk, there is no need to rotate the disk, and the whole system is reduced in size and weight. In addition to being thinner and thinner, power consumption can be reduced, and large-capacity information can be read and written at high speed, so that the processing capacity of the entire system is improved.

(Embodiment 4) FIG. 17 is a schematic diagram showing a main part of a computer system using a DRAM of the present invention. This computer system includes a central processing unit CPU as an information device, an I / O bus built in the information processing system, a BUS Unit, and a memory control unit Memo for accessing a high-speed memory such as a main memory or an extended memory.
ry Control Unit, DRAM as main memory, RO storing basic control program
M, a keyboard controller KBDC or the like having a keyboard connected to the tip. Further, a display adapter as a display adapter is connected to the I / O bus, and a display is connected to a tip of the display adapter. The parallel port Parallel Po is connected to the I / O bus.
Serial port Serial for rtI / F, mouse, etc.
Port I / F, floppy disk drive FD
D, a buffer controller HDD buffer for converting to an HDD I / F from the I / O bus is connected.
In addition, the memory control unit Memory Cont
An extended RAM and a DRAM as a main memory are connected to a bus from the rol unit. Here, the operation of the computer system will be described. When the power is turned on and the operation is started, first, the central processing unit CPU accesses the ROM through the I / O bus, and performs initial diagnosis and initial setting. And
The system program is loaded from the auxiliary storage device to the DRAM as the main storage memory. Further, the central processing unit CPU operates to access the HDD to the HDD controller through the I / O bus. And
When the loading of the system program is completed, the processing proceeds according to the processing request of the user. The user proceeds with inputting and outputting processing by using the keyboard controller KBDC and the display adapter Display adapter on the I / O bus. Then, if necessary, the parallel port Parallel Port
I / F, serial port Serial Port I /
Utilize the input / output device connected to F. When the main memory capacity of the DRAM as the main memory in the main body is insufficient, the main memory is supplemented by the extended RAM. If the user wants to read and write the file,
The DD requests access to the auxiliary storage device assuming that the DD is the auxiliary storage device. Then, the file system constituted by the DRAM of the present invention receives the request and accesses the file data. Thus, the DR of the present invention
By applying AM to computer systems,
It can be applied to the portable computer system as described above. This eliminates the need to rotate the conventional disk, thus making it possible to reduce the size, weight, and thickness of the entire system, reduce power consumption, and read and write a large amount of information at high speed. Can be improved. Further, since the conventional disk is replaced with the DRAM of the present invention, the shock resistance, which is a problem in a portable computer, can be improved, and the reliability in a computer system can be improved.

[0025]

The sensitivity of the differential amplifier of the DRAM is improved, and the number of bit lines that can be connected to one sense amplifier can be increased. Therefore, the number of sense amplifiers can be reduced, and the chip area of the DRAM can be reduced. The operation reliability is improved by applying an arc differential amplifier to the amplifier. Further, the size of a memory board using a DRAM as a main storage memory is reduced, so that the cost as a data processing system can be reduced. Further, by using a semiconductor disk device instead of a magnetic disk, it is possible to realize a more compact computer system with improved reliability.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of a sense amplifier having a circuit for compensating a threshold value of an NMOS transistor of the present invention and a DRAM circuit including a control circuit thereof.

FIG. 2 is a circuit diagram of a conventional CMOS sense amplifier and an operation waveform diagram thereof.

FIG. 3 shows a conventional threshold voltage compensation type CMO.
FIG. 2 is a circuit diagram of an S sense amplifier and an operation waveform diagram thereof.

Figure 4 is a diagram showing a relationship between the variation in the amount of noise and the coupling capacitance due to variations in the figures and the threshold voltage V _th indicates a relationship between the noise amount and the coupling capacitance due to variation in the threshold voltage V _th.

FIG. 5 is a schematic diagram of a layout of a conventional DRAM.

FIG. 6 shows a 1/4 sense amplifier in a DRAM to which a CMOS sense amplifier for compensating a threshold voltage V _th is applied.
FIG. 6 is a diagram comparing the amount of noise between a DRAM and a conventional DRAM.

FIG. 7 is an operation waveform diagram of a DRAM including a sense amplifier having a circuit for compensating a threshold value of an NMOS transistor and a control circuit thereof according to the present invention;

FIG. 8 is a schematic diagram of a sense amplifier having a circuit for compensating a threshold value of a PMOS transistor of the present invention and a DRAM circuit including a control circuit thereof.

FIG. 9 is an operation waveform diagram of a DRAM including a sense amplifier having a circuit for compensating a threshold value of a PMOS transistor and a control circuit thereof according to the present invention;

FIG. 10 is a layout diagram when a memory cell structure is used for a capacitor in a sense amplifier or a main amplifier of the present invention.

FIG. 11 is a layout diagram of a DRAM of the present invention.

FIG. 12 is a schematic diagram of a main amplifier having a circuit for compensating a threshold value of an NMOS transistor and a DRAM circuit including a control circuit thereof according to the present invention;

FIG. 13 is an operation waveform diagram of a DRAM including a main amplifier having a circuit for compensating a threshold value of an NMOS transistor and a control circuit thereof according to the present invention;

FIG. 14 is a functional block diagram of a DRAM using a sense amplifier and / or a main amplifier of the present invention.

FIG. 15 is a functional block diagram of a memory board using the DRAM of the present invention.

FIG. 16 is a functional block diagram of an IC card using the DRAM of the present invention.

FIG. 17 is a functional block diagram of a computer system using the DRAM of the present invention.

[Explanation of symbols]

BL, BLB: bit line, WL: word line, CNTR
L1, ... _Vth control circuit, SA ... sense amplifier, PC
... Precharge circuit, ADB ... Address buffer, C
D, CDB: common data line, DCR: decoder, M
AT, MAB: Main amplifier input / output line, DRIVE ...
Driver, OB: output buffer, MA: main amplifier, SWT switch, CPU: central processing unit, I / F
..Interface circuit, RAR: Row address receiver, CAR: Column address receiver, ADR
..Address receivers, DCRs ... decoders, RAS-
CNTRL ... RAS control circuit, CNTRL ...
Control circuit, DBD: Data bus driver, R
EFREQ: refresh request signal, MS: memory activation signal, REGRN: refresh instruction signal, AD
MPX: address multiplexer, DP: display, FDD: floppy disk drive, FD: floppy disk, file M: file memory,
KB: Keyboard, KBDC: Keyboard controller, HDD: Hard disk drive, main M
..Main memory.

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Hideyuki Miyazawa 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (56) References JP-A-56-105389 (JP, A) JP-A-52 149449 (JP, A) JP-A-59-167896 (JP, A) JP-A-64-10493 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11C 11/409 H01L 21/822 H01L 21/8242 H01L 27/04 H01L 27/108

Claims (4)

(57) [Claims] 1. A memory array including a plurality of memory cells provided at intersections of a plurality of bit line pairs and a plurality of word lines, each of which has a first capacitor for storing information, and a plurality of bit line pairs. A sense amplifier for amplifying a signal read from a memory cell to a first potential or a second potential, and the plurality of bit line pairs,
A dynamic RAM having precharge means for precharging a third potential which is an intermediate potential between said potential and said second potential, wherein each of said plurality of sense amplifiers has a source connected in common and a gate And a first MOS transistor pair of a first conductivity type having a gate and a drain crossed and coupled to each other.
An OS transistor pair, a second capacitor having a first electrode connected to the source of one transistor of the second MOS transistor pair, and a third capacitor having a third electrode connected to the source of the other transistor of the second MOS transistor pair.
Includes a capacitor, a pre-Symbol first 4MOS transistor pair whose source-drain path to each source provided in correspondence with one and the other of the first 2MOS transistor pair is connected, and a second electrode remainder of the second capacitor, said third fourth electrode remains the capacitor are connected to a common, dynamic RAM, the first connected to the common
A first driving means for the second electrode and the fourth electrode to drive the first potential or the third potential, the source of the first 2MOS transistor pair before Symbol plurality of sense amplifiers via the first 4MOS transistor pair And a second driving means operable independently of the first driving means for driving the memory cell to the first potential. The second and third capacitors are connected to the first of the memory cells.
A dynamic RAM which has the same structure as a capacitor or is formed in the same process step, and wherein the first to fourth electrodes have a capacitor structure which is not a MOS capacitor formed on a semiconductor substrate. 2. The dynamic type R according to claim 1, wherein
A dynamic type, comprising: a plurality of fifth MOS transistor pairs provided between the corresponding bit line pairs of the plurality of sense amplifiers for separating the sense amplifiers from the bit line pairs. RA
M. 3. The dynamic RAM according to claim 1, wherein said first capacitor has a fin-stacked trench capacitor structure. 4. The dynamic RAM according to claim 1, wherein said first conductivity type is P-type, and said second conductivity type is N-type.