JPH06242819A - Signal state control system for programmable controller - Google Patents

Abstract

PURPOSE:To easily and surely perform the forced ON/OFF operations for debugging of a sequence program, etc., in a PC(programmable controller) signal state control system which forcibly controls the ON/OFF states of the input signals, etc., which are treated by the PC. CONSTITUTION:An internal work area 44 is added to a signal data memory in addition to the conventional input signal area 41, output signal area 42, and internal relay signal area 43. The data on a signal A, for example, is stored in a bit area 2 of an address 411 of the area 41. When the signal A is forcibly turned on or off, an operator gives an instruction on a screen, etc. Then, a part which designates a bit of a machine word instruction treating the signal A is rewritten into a bit area 0 (storing signal 0 showing an OFF state) or a bit area 1 (storing signal 1 showing an ON state) of the address 441 of the area 44 in response to the contents of designation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal state control system for a PC, and more particularly to a signal state control system for a PC for forcibly controlling the on / off state of input signals handled by the PC.

[0002]

2. Description of the Related Art Generally, in a PC (programmable controller), it is sometimes desired to forcibly turn on or off an external input signal or an internal relay signal when debugging a ladder program or when investigating the cause of a system failure. . In order to deal with this, the following methods have been conventionally used.

First, when an operator gives a forced on / off instruction, the data of the corresponding bit address in the memory storing the input signal and the signal of the internal relay is set to 1 (on) or 0 (off). ).

Secondly, a table as to whether or not to perform forced on / off for each input signal is created based on the forced on / off instruction from the operator. Then, by referring to this table when capturing the input signal,
It is determined whether the input signal is taken into the memory as it is or forced on / off is performed.

[0005]

However, in the PC, the input signal from the outside is taken in each time the sequence program is scanned, that is, every time the entire sequence program is executed once. Even if the data of the bit address is rewritten to 1 or 0 as described above, it is immediately rewritten to the actual state at the next scan. Also, regarding the signal of the internal relay, if the sequence program writes a new calculation result to the internal relay, the forced on / off state is canceled at that point.

On the other hand, the second method has a problem that the table has to be referred every time the sequence program is scanned, and it takes a long time to fetch an input signal and the scan time becomes long.

The present invention has been made in view of the above circumstances, and a signal state of a PC capable of easily and surely performing forced on / off for debugging a sequence program or investigating a cause of a failure. The purpose is to provide a control method.

[0008]

According to the present invention, in order to solve the above problems, a PC (programmable controller) is used.
P that forcibly controls the on / off state of input signals etc.
In the signal state control method of C, program storage means for storing the sequence program in a rewritable state, on / off data storage means for storing on / off data indicating on / off states at predetermined two bit addresses, respectively, and Commanding means for instructing to forcibly turn on or off the state of the signal of No. 1 and the bit addressing section on the operand of the machine language instruction for handling the commanded signal correspond to the on / off data storing means. And a bit address rewriting means for rewriting to the other bit address.

[0009]

The sequence program is stored in a rewritable state by the program storing means, and the on / off data indicating the on / off state is stored in the predetermined two bit addresses by the on / off data storing means. When the compulsory command means forcibly turns on or off the desired signal state, the bit address rewriting means specifies the bit address on the operand of the machine language instruction that handles the commanded signal. The part is rewritten to the corresponding bit address of the on / off data storage means.

Therefore, unless the forced command is released, the on / off state of the on / off data storage means is always read,
To be executed.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram showing the main configuration inside the PC (programmable controller) of this embodiment. The processor (CPU) 1 reads and executes the management program in the EPROM 2 via the bus 8 and controls the operation of the entire PC. A ladder program, which is one of sequence programs, is stored in the RAMA3. This RAMA3 is backed up by the battery 3a and retains its contents even after the power of the PC is cut off.

RAMB4 is a work memory, and P
An input signal from a switch or the like connected to C, an output signal to a solenoid or a lamp, an internal relay signal for executing a ladder program, and the like are stored.

A switch and a solenoid are connected to the input / output interface 5, and signals are exchanged with the switch and the solenoid in response to a command from the processor 1. An operating device 7 such as a display and a keyboard is connected to the man-machine interface 6, and an operator performs debugging of a ladder program and forced on / off operation described later.

FIG. 3 is a diagram showing an example of a ladder program to be executed by a PC. However, only one net is shown here. This ladder program 10 is R
It is stored in the AMA 3 in the following instruction word format.

RD A AND B OR D AND. NOT C WRT E The processor 1 cyclically executes such a sequence program to write and read signals to and from the RAM B4.

FIG. 4 is a diagram showing an instruction format of machine language instructions for the processor 1 to execute the above ladder program. The instruction format 11 is composed of an OP code 12 and an operand 13. Also,
The operand 13 is composed of an address designation section 13a and a bit designation section 13b. In OP code 12,
Execution instruction codes such as RD, AND, and OR are written. Further, the addressing unit 13a includes a RAMB4
The address of the read or write destination of the signal data is written in, and the bit address of the data is written in the bit designating section 13b. The processor 1 reads a machine language instruction having the instruction format 11 to read or write data in the RAMB 4 according to the content.

FIG. 1 is a conceptual diagram showing the inside of the RAMB4 for data. In the RAMB4, an input signal area 41 for storing data of an input signal, an output signal area 42 for storing data of an output signal, an internal relay signal area 43 for storing a signal of an internal relay, and a book. An internal work area 44 specific to the embodiment is provided.

For example, the address 411 of the input signal area 41
On-off data of the input signals A, B, and C of the ladder program 10 of FIG. 3 are stored in the bit area 2, the bit area 0, and the bit area 5, respectively. Similarly, ON / OFF data of the solenoid E is stored in the bit area 5 of the address 421 of the output signal area 42, and ON / OFF data of the internal relay signal D is stored in the bit area 5 of the address 431 of the internal relay signal area 43.

On the other hand, the address 44 of the internal work area 44
Data 0 and 1 are stored in the bit area 0 and the bit area 1 of 1, respectively. These data are used for forced on / off control described later.

Next, P of the present embodiment having the above-mentioned structure
The basic operation of C will be described. When the operation of the PC is started, the processor 1 reads an input signal such as a switch through the input / output interface 5, and stores ON / OFF data of each signal in the input signal area 41 of the RAMB4.

Next, the processor 1 sequentially executes the ladder program of RAMA3. When executing the program, the machine language instruction of the format shown in FIG. 4 is read and executed according to its contents. FIG. 5 is a diagram showing a specific machine language instruction, and FIG. 5A is a diagram showing an example thereof.
(B) is a diagram showing the contents after the change. In the figure (A), the code RD (read instruction) is in the OP code 51 of the machine language instruction 53, and the address designation section 52 of the operand 52.
The address 411 is designated in a, and the bit 2 is designated in the bit designation section 52b. Therefore, the processor 1 having read this reads the data of the bit area 2 of the address 411 in the input signal area 41 of the RAMB 4 shown in FIG. 1, that is, the on / off state of the signal A.

When reading 1-bit data, the processor 1
Performs the logical operation specified by the OP code 51 with the data of the 1-bit accumulator in the processor,
The result is stored in the 1-bit accumulator. If the instruction of the OP code 51 is a write (WRT) instruction, the processor 1 writes the value of the 1-bit accumulator in the designated bit area of the RAMB4.

When all the instructions have been executed in this way, the processor 1 outputs each output signal of the output signal area 42 of the RAMB 4 through the input / output interface 5,
Turn on / off the corresponding solenoids and lamps.

By the way, when it is desired to debug the ladder program to be executed or to investigate the cause of the system failure, it is necessary to forcibly turn on or off the input signal and the signal of the internal relay to execute the ladder program. In such a case, the signal on the ladder diagram displayed on the display screen can be forcibly turned on / off by designating the cursor.

For example, when it is desired to forcibly turn on the input signal A, the cursor is moved to the input signal A and "1" is input on the display screen displaying the ladder diagram, for example. When this operation is performed, the contents of the machine language instruction 53 that handles the signal A are rewritten inside the PC. The machine language instruction for handling the signal A in the ladder program 10 is as shown in FIG. 5A described above, but if forced on is designated, the content is rewritten as shown in FIG. That is, the address designation section 52a of the operand 52 is designated from the address 411 to the address 441, and the bit designation section 52b is designated from bit 2 to bit 1.

Therefore, unless the forced off designation is released, the processor 1 reads the on / off state of the signal A into the bit area 1 of the address 441 in the internal work area 44 every time the machine language instruction 53 is read. As a result, the signal A is always treated as being in the ON state.

On the other hand, when the cursor is moved to the input signal A and "0" is input, the off state is forcibly designated.
In this case, the bit designating part 52b of the machine language instruction 53 has the bit area 0 of the address 441 in the internal work area 44.
Can be rewritten to. As a result, the signal A is always treated as being in the off state.

As described above, the normal signal areas 41 to 43 are used.
Besides, by providing an internal work area 44 which is a memory area for forced on / off, forced on / off control can be easily performed. In addition, since the specified state can be held unless the operator gives a change instruction, work such as debugging and trouble inspection becomes easy.

The content of the machine language instruction 53 before rewriting is stored in a predetermined area of the RAMB4,
When the forced on / off is released after work such as debugging, the contents can be easily restored to the original state. At this time, the signal state is returned to the original state on the ladder diagram.

[0030]

As described above, according to the present invention, the sequence program is stored in a rewritable state while the on / off data indicating the on / off states are stored in predetermined two bit addresses, respectively. When the signal state of the above is forcibly turned on or off, the bit address specification part on the operand of the machine language instruction that handles the commanded signal is rewritten to the corresponding on-off data bit address. I did so,
Unless the forced command is released, a predetermined on / off state can be read at all times when the machine language instruction is executed. Therefore, debugging and the like can be easily performed.

[Brief description of drawings]

FIG. 1 is a conceptual diagram showing the inside of a RAM for data.

FIG. 2 is a block diagram showing a main configuration inside a PC (programmable controller).

FIG. 3 is a diagram showing an example of a ladder program to be executed by a PC.

FIG. 4 is a diagram showing an instruction format of a machine language instruction for executing a ladder program.

5A and 5B are diagrams showing a specific machine language instruction, FIG. 5A being a diagram showing an example thereof, and FIG. 5B being a diagram showing the contents after change.

[Explanation of symbols]

 1 Processor (CPU) 3 RAMA 4 RAMB 5 Input / Output Interface 7 Operating Device 10 Ladder Program 11 Command Format 41 Input Signal Area 42 Output Signal Area 43 Internal Relay Signal Area 44 Internal Work Area 52 Operand 52b Bit Designation Section 53 Machine Language Instruction

Claims (2)

[Claims] 1. A PC (programmable controller)
P that forcibly controls the on / off state of input signals etc.
In the signal state control method of C, program storing means for storing the sequence program in a rewritable state, on / off data storing means for storing on / off data indicating on / off states at predetermined two bit addresses, respectively, Commanding means for instructing to forcibly turn on or off the state of the signal, and a bit addressing part on the operand of a machine language instruction that handles the commanded signal correspond to the on / off data storing means. A signal state control system for a PC, comprising: a bit address rewriting means for rewriting to one of the two bit addresses. 2. When there is an instruction to store the data of the bit address designating unit before being rewritten by the bit address rewriting unit and restore the signal forcibly turned on or off to the original state. 2. The signal state control system for a PC according to claim 1, further comprising rewriting means for rewriting the rewritten bit addressing section to original data.