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JPH0624205B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0624205B2
JPH0624205B2 JP60136027A JP13602785A JPH0624205B2 JP H0624205 B2 JPH0624205 B2 JP H0624205B2 JP 60136027 A JP60136027 A JP 60136027A JP 13602785 A JP13602785 A JP 13602785A JP H0624205 B2 JPH0624205 B2 JP H0624205B2
Authority
JP
Japan
Prior art keywords
wiring
layer
bonding
semiconductor substrate
wiring layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60136027A
Other languages
Japanese (ja)
Other versions
JPS61294838A (en
Inventor
靖 河渕
仁 大貫
正博 小泉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP60136027A priority Critical patent/JPH0624205B2/en
Publication of JPS61294838A publication Critical patent/JPS61294838A/en
Publication of JPH0624205B2 publication Critical patent/JPH0624205B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165Reinforcing structures
    • H01L2224/02166Collar structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147Copper (Cu) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、半導体装置に関するものである。Description: FIELD OF THE INVENTION The present invention relates to a semiconductor device.

〔発明の背景〕[Background of the Invention]

従来、半導体装置の電極・配線でCu 添加のAlが、例え
ば米国特許第3743894号公報に記載のように、エレクト
ロマイグレーション即ち電気移動の問題を回避するため
に用いられてきた。
Conventionally, Cu-added Al has been used in the electrodes and wirings of semiconductor devices to avoid the problem of electromigration, as described in US Pat. No. 3,743,894.

半導体装置の配線はAlが一般に用いられる この装置を高電流と高温状態の下で作動させるとき、A
l配線膜はそれを流れる電流により移動せしめられてこ
の金属をある区域では盛上げらせ他の区域では空所を形
成させる。この空所は十分大きくなるとこの空所が生じ
た区域での金属接触の抵抗を十分増大させて抵抗加熱を
起こし接触金属を溶融させ、それによりこの装置の早期
の事故を起させる可能性がある。
Al is generally used for the wiring of the semiconductor device. When this device is operated under high current and high temperature,
The l-wiring film is moved by the electric current flowing through it, causing the metal to rise in some areas and form voids in other areas. If this void becomes large enough, it will increase the resistance of the metal contact in the area where it occurred sufficiently to cause resistance heating and melting of the contact metal, which could lead to premature accidents of this equipment. .

上記米国特許によれば、このエレクトロマイグレーショ
ンの問題を回避するためにAlに1〜10重量%のCu を
混入する。そのためCu Al粒子の細粒構造を形成し
てこれがAl粒界と粒界三重点に介在し、Alの原子移
動を防げエレクトロマイグレーションに対する装置の寿
命を長くすることができる。
According to said U.S. patent, Al is mixed with 1-10 wt% Cu to avoid this electromigration problem. Therefore, a fine grain structure of Cu Al 2 grains is formed, and these are present at the Al grain boundaries and the grain boundary triple points, and it is possible to prevent atomic migration of Al and prolong the life of the device against electromigration.

本発明はAlよりも抵抗率の低いCu を用いて配線膜を
形成するもので、Alに比べ電流密度を大きくとること
ができる。更にCu の融点はAl よりも400℃以上高
いため、エレクトロマイグレーションによる装置の早期
の事故を防ぐことができる。このように配線をCu で形
成することによつて配線膜の幅を小さくすることができ
半導体基板の実装密度を上げることができる。同時にエ
レクトロマイグレーションによる装置の早期破壊を防止
できる。
In the present invention, the wiring film is formed by using Cu having a resistivity lower than that of Al, and the current density can be made larger than that of Al. Further, since the melting point of Cu is 400 ° C. or more higher than that of Al, it is possible to prevent an early accident of the device due to electromigration. By thus forming the wiring with Cu, the width of the wiring film can be reduced and the packaging density of the semiconductor substrate can be increased. At the same time, it is possible to prevent early destruction of the device due to electromigration.

〔発明の目的〕[Object of the Invention]

本発明の目的は従来の半導体Al配線膜に代わり、耐エ
レクトロマイグレーシヨン性に優れたCuを用いること
によつて、信頼性の高い半導体素子を提供することにあ
る。
An object of the present invention is to provide a highly reliable semiconductor element by using Cu having excellent electromigration resistance in place of the conventional semiconductor Al wiring film.

〔発明の概要〕[Outline of Invention]

従来、半導体装置の電極・配線には純Al又はSi 入り
Alが用いられていた。しかし、純Al,Si 入りAl
はエレクトロマイグレーション耐量が小さく、高電流密
度の電流を流すと、電極と半導体基体とのコンタクト抵
抗が増大する。あるいは、原子移動により配線が断線し
てしまう等の欠点があった。
Conventionally, pure Al or Si-containing Al has been used for electrodes and wiring of semiconductor devices. However, pure Al, Si containing Si
Has a low electromigration resistance, and when a current having a high current density is applied, the contact resistance between the electrode and the semiconductor substrate increases. Alternatively, there is a defect that the wiring is broken due to atom movement.

またCu 入りAl配線は耐エレクトロマイグレーション
性を有しているが、Cu 添加によりAl配線の比抵抗が
上昇するため、電流を流した際、素子の温度が著しく上
昇し、素子の動作不良の原因となる。またCu 入りAl
配線ではAl基地中にCu が分散しているため、エツチ
ングの際にAl原子とCu 原子とが局部電池として作用
し、Al配線のパターン精度が悪くなるという欠点があ
る。特に集積密度を高めた素子に於ける配線幅1μm以
下のCu 入りAl配線ではパターニング精度を確保する
ため、高度の加工技術を必要とする。
Although Cu-containing Al wiring has electromigration resistance, the addition of Cu increases the specific resistance of the Al wiring, so that when a current is applied, the temperature of the element rises remarkably, causing a malfunction of the element. Becomes Also Cu containing Al
Since Cu is dispersed in the Al base in the wiring, there is a drawback that Al atoms and Cu atoms act as a local battery during etching and the pattern accuracy of the Al wiring deteriorates. In particular, for Cu-containing Al wiring having a wiring width of 1 μm or less in an element having a high integration density, a high level of processing technology is required to ensure patterning accuracy.

本発明では、これらの欠点を除去するために、半導体と
のコンタクトをとる電極部分には純AlあるいはSi 入
りAlを用い、電流が流れる配線部分にはCu を用いた
もので、その目的は高集積、高精度を要求される半導体
装置の高安定電極・配線を実現することにある。またリ
ードフレームと素子を接続するボンディングワイヤとし
てCu ワイヤを用いることにより、半導体基体上のCu
配線膜のボンデイングパツド部分とCu ワイヤとを直接
接合できる利点がある。更にその際、銅製のリードフレ
ームを用いることにより、半導体基体上の配線膜、ボン
ディングワイヤ、リードフレーム全てを銅で構成するこ
とになり、耐湿信頼性・安定性に非常に優れた半導体装
置を提供することができる。
In order to eliminate these drawbacks, the present invention uses pure Al or Al containing Si and Cu for the wiring part through which a current flows, in order to eliminate these drawbacks. It is to realize highly stable electrodes and wirings of semiconductor devices that require high integration and high precision. Further, by using a Cu wire as a bonding wire for connecting the lead frame and the element, the Cu on the semiconductor substrate is
There is an advantage that the bonding pad portion of the wiring film and the Cu wire can be directly bonded. Furthermore, in this case, by using a copper lead frame, the wiring film on the semiconductor substrate, the bonding wires, and the lead frame are all made of copper, providing a semiconductor device with excellent moisture resistance reliability and stability. can do.

更にCu 配線膜の結晶粒を配線幅よりも小さく、結晶性
を半導体基板に対して〔111〕又は〔100〕方向に
優先配向させることにより、耐エレクトロマイグレーシ
ヨン性をより高めることができる。
Further, the crystal grain of the Cu wiring film is smaller than the wiring width and the crystallinity is preferentially oriented in the [111] or [100] direction with respect to the semiconductor substrate, whereby the electromigration resistance can be further enhanced.

次に、その理由を述べる。Si 入りAlの電気比抵抗が
3.1μΩcmなのに対しCuのそれが1.5μΩcmと小
さく、またSi 入りAlの融点が、660℃以下である
のに対し、Cu のそれが1083℃と高いため、同一電流密
度の通電ではCu の方が温度上昇が少なく、軟化の度合
も小さい。更に結晶の辷り面の多少を示す積層欠陥エネ
ルギは、(111)面内でCu では小さく(40erg/cm
2)、Alでは大きい(200erg/cm2)。これはAlの
辷り面の密度がCu のそれの数倍ある事を意味し、Al
の方が電流を流した時のエレクトロマイグレーシヨンを
起こし易いことを意味している。
Next, the reason will be described. The electrical resistivity of Si-containing Al is 3.1 μΩcm, while that of Cu is as small as 1.5 μΩcm, and the melting point of Si-containing Al is 660 ° C. or less, whereas that of Cu is as high as 1083 ° C. When the current is applied at the same current density, Cu has a smaller temperature rise and a smaller degree of softening. Furthermore, the stacking fault energy, which indicates the number of sloping faces of the crystal, is small for Cu in the (111) plane (40 erg / cm
2 ), large for Al (200 erg / cm 2 ). This means that the surface density of Al is several times higher than that of Cu.
Means that electromigration tends to occur when a current is applied.

一方、Cu 配線にCuワイヤをボンデイングするばかり
でなく、従来のAu ワイヤあるいはAlワイヤによるボ
ンデイングを行なうため、半導体基体上のCu配線膜の
ボンデイングパツド部にボンデイングの安定性にすぐれ
た純Al又はNi,Pd,Ptのうち少くとも1種以上
を添加したAl層を堆積させればよい。この方法を用い
ることにより、従来設備を生かし、Cu ワイヤでボンデ
イングしたのと同等の高信頼性をする半導体装置を提供
することができる。
On the other hand, not only the Cu wire is bonded to the Cu wiring but also the conventional Au wire or Al wire is used for bonding, so that the bonding pad portion of the Cu wiring film on the semiconductor substrate is pure Al or has excellent bonding stability. An Al layer to which at least one of Ni, Pd, and Pt is added may be deposited. By using this method, it is possible to provide a semiconductor device having high reliability equivalent to that of bonding with a Cu wire by utilizing conventional equipment.

このようにして作製した半導体装置をセラミクスモール
ドすることにより劣悪な環境下でも製品の信頼性を確保
できる。また、セラミクスモールドの替わりに、エポキ
シ樹脂を主とする樹脂モールドを行なうことによつても
外部環境から内部の半導体基板を保護することができ
る。
By subjecting the semiconductor device thus manufactured to the ceramics molding, the reliability of the product can be secured even in a bad environment. Further, instead of the ceramic mold, resin molding mainly composed of epoxy resin can be performed to protect the internal semiconductor substrate from the external environment.

〔発明の実施例〕Example of Invention

以下、本発明を実施例によつて詳細に説明する。 Hereinafter, the present invention will be described in detail with reference to examples.

第1図は本発明の実施例の構造を示した断面図である。
図において、1は半導体基板(Si 基板,Ga−As基
板)、2は不純物(例えばP,As,B,Al等)を拡
散した拡散層、3は窓明けされた絶縁物(例えば厚さ
0.1〜0.5μmのSiO2膜乃至PSG膜)、4は純
Al又はSi 入りAl層で形成(例えば蒸着、スパツ
タ、CVD法等により厚さ0.1〜0.5μm堆積さ
せ、フオトエツチングによりパターニング後350〜5
50℃の熱処理を5〜60分間施して安定化する。)さ
れた電極であり、拡散層2とコンタクト5で接触してい
る。6はAlに比べ電気比抵抗が半分のCu 層で形成
(例えば蒸着、スパツタ、CVD法等により厚さ0.5
〜2μm堆積させ、パターニング後250〜550℃の熱
処理を5〜60分間施こして安定化する。)された配線
であり、電極4と接触している。7は素子表面を保護す
る保護膜(例えば厚さ0.5〜2.0μmのSiO2膜乃
至PSG膜)でボンデイングパツド部分8が開口されて
いる。9はCu ボンデイングワイヤでパツド部8にボン
デイング(熱圧着又は超音波ボンデイング等による。)
される。
FIG. 1 is a sectional view showing the structure of an embodiment of the present invention.
In the figure, 1 is a semiconductor substrate (Si substrate, Ga-As substrate), 2 is a diffusion layer in which impurities (for example, P, As, B, Al, etc.) are diffused, 3 is a windowed insulator (for example, a thickness of 0). 1 to 0.5 μm of SiO 2 film or PSG film), 4 is formed of pure Al or an Al layer containing Si (0.1 to 0.5 μm in thickness by vapor deposition, sputtering, CVD, etc., and photo etching) After patterning by 350 ~ 5
Stabilize by heat treatment at 50 ° C. for 5 to 60 minutes. ), And is in contact with the diffusion layer 2 through the contact 5. 6 is a Cu layer having an electric resistivity which is half that of Al (for example, a thickness of 0.5 is formed by vapor deposition, sputtering, CVD, etc.).
After depositing ˜2 μm and patterning, heat treatment at 250 to 550 ° C. is applied for 5 to 60 minutes to stabilize. ), And is in contact with the electrode 4. Reference numeral 7 is a protective film (for example, 0.5 to 2.0 μm thick SiO 2 film or PSG film) for protecting the surface of the element, and the bonding pad portion 8 is opened. Numeral 9 is a Cu bonding wire which is bonded to the pad portion 8 (by thermocompression bonding or ultrasonic bonding).
To be done.

このように構成すると、以下に述べるように配線部分を
純Al又はSi 入りAlを用いた場合に比べ耐エレクト
ロマイグレーシヨン性が高く、また従来のAl配線膜、
Au ボンデイングワイヤで構成された樹脂モールド半導
体製品に比べて耐湿信頼性も向上する。
With this structure, as described below, the electromigration resistance is higher than in the case of using pure Al or Si-containing Al for the wiring portion, and the conventional Al wiring film,
Moisture-resistant reliability is also improved compared to resin-molded semiconductor products composed of Au bonding wires.

第2図は本発明の効果を説明するためのグラフであり、
配線材料として、従来のSi 入りAlを用いた場合と、
本発明のCu 配線を用いた場合の高温通電試験における
抵抗値の経時変化を示す。図から明らかなようにSi 入
りAlに比べCu配線の方が安定である。
FIG. 2 is a graph for explaining the effect of the present invention,
When using conventional Si-containing Al as the wiring material,
3 shows a change with time in resistance value in a high-temperature current test when using the Cu wiring of the present invention. As is clear from the figure, the Cu wiring is more stable than Al containing Si.

この理由は、Si 入りAlの電気比抵抗が3.1μΩcm
なのに対しCuのそれが1.5μΩcmと小さく、またSi
入りAlの融点が660℃以下であるのに対し、Cu
のそれが1083℃と高いため、同一電流密度の通電ではC
u の方が温度上昇が少なく、軟化の度合も小さいためで
ある。
The reason for this is that the electrical resistivity of Al containing Si is 3.1 μΩcm.
On the other hand, that of Cu is as small as 1.5 μΩcm, and Si
While the melting point of Al containing Al is 660 ° C or lower, Cu
Since it is as high as 1083 ℃, it is C at the same current density.
This is because u has a smaller temperature rise and a smaller degree of softening.

第3図は樹脂モールドした場合のCu配線、Cuボンデ
イングワイヤの組合せと、従来のSi 入りAl配線、A
u ボンデイングワイヤを組合せた場合の加速寿命試験
(2気圧飽和水蒸気中放置試験)の結果を示す。図から
明らかなように従来の方法に比べCu 配線Cu ワイヤの
組合せの方が耐湿信頼性に優れ、寿命が2〜2.5倍に
なる。
Fig. 3 shows the combination of Cu wiring and Cu bonding wire when resin-molded, the conventional Si-containing Al wiring, A
u The results of an accelerated life test (2 atmospheric pressure saturated steam test) in the case of combining bonding wires are shown. As is clear from the figure, the combination of Cu wiring and Cu wire is superior in moisture resistance reliability and the life is 2 to 2.5 times as long as the conventional method.

この理由は、従来の方法ではAlとAu を接合させてお
り、その接合部に水分が侵入してくると局部電池を形成
し電気的に卑なAlが溶けてしまうのに対し、本発明で
はCu 配線Cu ワイヤの組合せのため局部電池が形成さ
れず耐食性が向上するものと考えられる。
The reason for this is that Al and Au are bonded in the conventional method, and when water enters the bonding part, a local battery is formed and electrically base Al is melted, whereas in the present invention, It is considered that due to the combination of Cu wiring and Cu wire, a local battery is not formed and corrosion resistance is improved.

以上をまとめると、本発明によれば、エレクトロマイグ
レーシヨンに対する信頼性と耐湿信頼性の2つを同時に
満足できると考えられる。
In summary, according to the present invention, it is considered that the reliability for electromigration and the moisture resistance reliability can be simultaneously satisfied.

第4図は本発明のもう一つの実施例の構造を示した断面
図である。図において、前出の図1に於ける同一符号の
ものは同一又は均等部分を示すものとする。この実施例
は、第1図の実施例におけるCu 配線のボンデイングパ
ツド部分8とAu 又はAl又はCu ワイヤ11の中間に
Ni,Pd,Ptのうち少くとも1種以上の元素を0.0
1〜3%含むAl層10(例えば厚さ0.1〜1.0μ
m)を堆積したものである。このAl層10は耐食性を
有していることが知られており、ボンデイングワイヤと
Cu 配線膜間のボンデイングの安定性を損なうのを防止
するとともに耐湿信頼性を持たせる役割をはたす。
FIG. 4 is a sectional view showing the structure of another embodiment of the present invention. In the figure, the same reference numerals in FIG. 1 described above indicate the same or equivalent portions. This embodiment is intermediate in Ni of the first bonding of Cu wiring in the embodiment of Figure Patsu head portion 8 and the Au or Al or Cu wires 11, Pd, and at least one or more elements of P t 0.0
Al layer 10 containing 1 to 3% (for example, thickness of 0.1 to 1.0 μm)
m) is deposited. It is known that the Al layer 10 has corrosion resistance, and it serves to prevent the stability of bonding between the bonding wire and the Cu wiring film from being impaired and to have moisture resistance reliability.

以上説明したように、本発明によれば、エレクトロマイ
グレーシヨン耐性が高く、かつ耐湿信頼性にすぐれた配
線が得られる。
As described above, according to the present invention, a wiring having high electromigration resistance and excellent moisture resistance reliability can be obtained.

また、耐食性を有するAl層をボンデイングパツド上に
設けることにより、Au,Al,Cu何れのワイヤも容
易にボンデイングでき、かつ電極・配線形成後に熱処理
が加わる場合でも、ボンデイングの安定性は維持され、
セラミクスモールド又は樹脂モールドを行つた際に高信
頼性の半導体素子を作製できる。
Further, by providing an Al layer having corrosion resistance on the bonding pad, any of Au, Al and Cu wires can be bonded easily, and the stability of bonding is maintained even when heat treatment is applied after the electrode / wiring formation. ,
A highly reliable semiconductor element can be manufactured when the ceramics molding or the resin molding is performed.

次に、Cu 配線膜の構造について本発明の効果を説明す
る。第5図はCu 配線膜を形成する際に基板温度を変え
て結晶粒の大きさを配線幅(1μm)よりも小さくして
いつた場合の高温通電試験における抵抗値の経時変化を
示す。図から明らかなように結晶が小さなもの程安定度
が高く、結晶粒が配線幅よりも大きなものでは寿命が短
かい。
Next, the effect of the present invention will be described with respect to the structure of the Cu wiring film. FIG. 5 shows the change with time in the resistance value in the high temperature current test when the substrate temperature was changed and the crystal grain size was made smaller than the wiring width (1 μm) when the Cu wiring film was formed. As is clear from the figure, the smaller the crystal, the higher the stability, and the larger the crystal grain is, the shorter the life.

この理由は結晶粒が小さなもの程、粒界拡散が均一に起
こり、配線幅と結晶粒の大きさが同程度になると粒界拡
散の影響で粒界から配線が断線するためだと考えられ
る。
The reason for this is thought to be that the smaller the crystal grains, the more uniformly grain boundary diffusion occurs, and when the wiring width and the size of the crystal grains are about the same, the wiring breaks from the grain boundaries due to the influence of grain boundary diffusion.

第6図はCu 配線膜の結晶性を半導体基板に対して〔1
11〕又は〔100〕方向に優先配向させた場合(例え
ば、基板温度150℃以上でスパツタ法により形成す
る。)と結晶の配向性が無い場合の、高温通電試験にお
ける抵抗値の経時変化を示す。図から明らかなように
〔111〕又は〔100〕方向に優先配向させたもので
は安定度が高い。
FIG. 6 shows the crystallinity of the Cu wiring film with respect to the semiconductor substrate [1.
11] or the [100] direction is preferentially oriented (for example, it is formed by a sputtering method at a substrate temperature of 150 ° C. or higher) and the crystal orientation is absent. . As is apparent from the figure, stability is high in the case of preferential orientation in the [111] or [100] direction.

この理由はCu が面心立方格子であるため、辷り変形す
る際の剪断応力最大の辷り系は{111}面となる。そ
の際、結晶が半導体基板に対して〔111〕又は〔10
0〕方向に優先配向していると、{111}面上を移動
してくる転位は不動転位の障壁に向かつて堆積し、転位
の移動が妨げられることによりCu配線膜が強化される
ことになるためと考えられる。
The reason for this is that since Cu is a face-centered cubic lattice, the stagnation system with the maximum shear stress during stagnation deformation is the {111} plane. At that time, crystals are [111] or [10] against the semiconductor substrate.
0] direction, the dislocations moving on the {111} plane are deposited toward the barrier of immovable dislocations and the movement of dislocations is hindered to strengthen the Cu wiring film. It is thought to be because.

以上説明したように、本発明による構造のCu 配線膜を
用いれば、エレクトロマイグレーシヨン耐性が高い高信
頼性の半導体素子を作製できる。
As described above, by using the Cu wiring film having the structure according to the present invention, a highly reliable semiconductor element having high electromigration resistance can be manufactured.

〔発明の効果〕〔The invention's effect〕

本発明によれば、耐食性、耐エレクトロマイグレーシヨ
ン性ともに優れた半導体用配線膜が得られる。その結
果、樹脂モールドあるいはセラミクスモールドの半導体
素子の高密度、微細配線パターンに適用でき、半導体装
置の信頼性の向上を図ることができる。
According to the present invention, a wiring film for a semiconductor having excellent corrosion resistance and electromigration resistance can be obtained. As a result, it can be applied to a high density and fine wiring pattern of a semiconductor element of resin mold or ceramics mold, and the reliability of a semiconductor device can be improved.

【図面の簡単な説明】[Brief description of drawings]

第1図及び第4図はそれぞれ本発明の実施例の構造を示
した断面図、第2図,第5図及び第6図は本発明の効果
による耐エレクトロマイグレーシヨン性を示した線図、
第3図は本発明による耐湿性の効果を示したグラフであ
る。 1……半導体基板、2……拡散層、3……絶縁物、6…
…Cu 層、7……保護膜、8……ボンデイングパツド、
9……Cu ワイヤ、11……ボンデイングワイヤ。
1 and 4 are sectional views showing the structure of an embodiment of the present invention, and FIGS. 2, 5 and 6 are diagrams showing electromigration resistance by the effect of the present invention,
FIG. 3 is a graph showing the effect of moisture resistance according to the present invention. 1 ... Semiconductor substrate, 2 ... Diffusion layer, 3 ... Insulator, 6 ...
… Cu layer, 7 …… Protective film, 8 …… Bonding pad,
9 ... Cu wire, 11 ... Bonding wire.

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭59−43570(JP,A) 特開 昭53−116089(JP,A) 特開 昭59−143320(JP,A) 実開 昭58−18345(JP,U) ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-59-43570 (JP, A) JP-A-53-116089 (JP, A) JP-A-59-143320 (JP, A) Actual development Sho-58- 18345 (JP, U)

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】内部に拡散層を有する半導体基板と、 上記半導体基板上に形成された絶縁層と、 上記絶縁層上に形成されたCuからなる配線層とを有
し、 上記配線層は、純Al、又は、Si入りAlからなる電
極を介して上記拡散層にコンタクトされ、 上記配線層のボンディングパッド部にはCuボンディン
グワイヤがワイヤボンディングにより接合されているこ
とを特徴とする半導体装置。
1. A semiconductor substrate having a diffusion layer inside, an insulating layer formed on the semiconductor substrate, and a wiring layer made of Cu formed on the insulating layer, the wiring layer comprising: A semiconductor device, wherein the diffusion layer is contacted via an electrode made of pure Al or Si-containing Al, and a Cu bonding wire is bonded to the bonding pad portion of the wiring layer by wire bonding.
【請求項2】内部に拡散層を有する半導体基板と、 上記半導体基板上に形成された絶縁層と、 上記絶縁層上に形成されたCuからなる配線層とを有
し、 上記配線層は、純Al、又は、Si入りAlからなる電
極を介して上記拡散層にコンタクトされ、 上記配線層のボンディングパッド部には、純Al層、又
は、Ni、Pd、Ptのうち少なくとも1種以上の元素
を含むAl層が形成され、この層にAu、Al、また
は、Cuからなるボンディングワイヤがワイヤボンディ
ングにより接合されていることを特徴とする半導体装
置。
2. A semiconductor substrate having a diffusion layer inside, an insulating layer formed on the semiconductor substrate, and a wiring layer made of Cu formed on the insulating layer, wherein the wiring layer comprises: The diffusion layer is contacted via an electrode made of pure Al or Si-containing Al, and the bonding pad portion of the wiring layer has a pure Al layer or at least one element selected from Ni, Pd, and Pt. And a bonding wire made of Au, Al, or Cu is bonded to the layer by wire bonding.
【請求項3】特許請求の範囲第1、又は、第2項におい
て、上記配線層を形成するCuの結晶粒の大きさが、こ
の配線層の配線幅よりも小さいことを特徴とする半導体
装置。
3. A semiconductor device according to claim 1 or 2, wherein the size of the crystal grains of Cu forming the wiring layer is smaller than the wiring width of the wiring layer. .
【請求項4】特許請求の範囲第1、第2項、又は、第3
項において、上記配線層を形成するCuの結晶性を上記
半導体基板に対して〔111〕又は〔100〕方向に優
先配向させたことを特徴とする半導体装置。
4. Claims 1, 2, or 3
2. The semiconductor device according to the item 1, wherein the crystallinity of Cu forming the wiring layer is preferentially oriented in the [111] or [100] direction with respect to the semiconductor substrate.
JP60136027A 1985-06-24 1985-06-24 Semiconductor device Expired - Lifetime JPH0624205B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60136027A JPH0624205B2 (en) 1985-06-24 1985-06-24 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60136027A JPH0624205B2 (en) 1985-06-24 1985-06-24 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS61294838A JPS61294838A (en) 1986-12-25
JPH0624205B2 true JPH0624205B2 (en) 1994-03-30

Family

ID=15165470

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60136027A Expired - Lifetime JPH0624205B2 (en) 1985-06-24 1985-06-24 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0624205B2 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03131021A (en) * 1989-10-16 1991-06-04 Matsushita Electron Corp Manufacture of semiconductor device
TW571373B (en) 1996-12-04 2004-01-11 Seiko Epson Corp Semiconductor device, circuit substrate, and electronic machine
JP4513973B2 (en) * 1996-12-04 2010-07-28 セイコーエプソン株式会社 Manufacturing method of semiconductor device
TW480636B (en) 1996-12-04 2002-03-21 Seiko Epson Corp Electronic component and semiconductor device, method for manufacturing and mounting thereof, and circuit board and electronic equipment
JP4423379B2 (en) 2008-03-25 2010-03-03 合同会社先端配線材料研究所 Copper wiring, semiconductor device, and method of forming copper wiring
JP2009246218A (en) 2008-03-31 2009-10-22 Renesas Technology Corp Semiconductor device and method for manufacturing the same
JP2013219385A (en) * 2013-06-21 2013-10-24 Renesas Electronics Corp Semiconductor device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5639050B2 (en) * 1972-08-29 1981-09-10
JPS53116089A (en) * 1977-03-22 1978-10-11 Hitachi Ltd Wiring constituent body
JPS5818345U (en) * 1981-07-28 1983-02-04 株式会社日立製作所 Migration resistant Al wiring
JPH0228249B2 (en) * 1983-02-04 1990-06-22 Tdk Electronics Co Ltd PATAANKASARETADODENSEISOOKEISEISURUHOHO

Also Published As

Publication number Publication date
JPS61294838A (en) 1986-12-25

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