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JPH06232443A - Superlattice avalanche photodiode and manufacture thereof - Google Patents

Superlattice avalanche photodiode and manufacture thereof

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Publication number
JPH06232443A
JPH06232443A JP50A JP1666493A JPH06232443A JP H06232443 A JPH06232443 A JP H06232443A JP 50 A JP50 A JP 50A JP 1666493 A JP1666493 A JP 1666493A JP H06232443 A JPH06232443 A JP H06232443A
Authority
JP
Japan
Prior art keywords
type
layer
superlattice
type inp
mesa
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP50A
Other languages
Japanese (ja)
Other versions
JP2894910B2 (en
Inventor
Isao Watanabe
功 渡邊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
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Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP5016664A priority Critical patent/JP2894910B2/en
Publication of JPH06232443A publication Critical patent/JPH06232443A/en
Application granted granted Critical
Publication of JP2894910B2 publication Critical patent/JP2894910B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PURPOSE:To improve a low dark current and reliability by embedding mesa formed by etching and removing particular layers with a p<-> type InP or the like, thereby reducing a surface leak dark current. CONSTITUTION:Dangling bond causing an interfacial level or a surface defect is terminated at a p<-> type InP embedded layer 110 which has lattice-matching with a substrate 11, so that these interfacial level and surface defect can be considerably reduced. Also, when recrystalization growth of a semiconductor p<-> type InP embedded layer 110 is in progress at the mesa sidewall, a natural oxide film created on mesa sidewall can be removed by substrate heating or irradiation with a hydrogen radical beam in the molecular beam gaseous phase growth method, so that dangling bond even on a semiconductor natural oxide film or a semiconductor surface can be reduced. Because of this, p<-> type InP layer/interfacial defect on mesa sidewall or interfacial level have been reduced, so that a secular increase can be restricted and a semiconductor photodetector with improved element reliability can be realized.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、低暗電流・高信頼性を
有する超格子アバランシェフォトダイオードに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a superlattice avalanche photodiode having low dark current and high reliability.

【0002】[0002]

【従来の技術】高速・高感度・高信頼性の光通信システ
ムを構成するには、高速応答、低暗電流、かつ、高信頼
性を有する半導体受光素子が不可欠である。このため、
近年シリカ系ファイバの低損失波長域1.3〜1.6μ
mに適応できるInP/InGaAs系アバランシェフ
ォトダイオード(APD)やpinフォトダイオード
(pinPD)の高速化・高感度化に対する研究が活発
となっている。InP/InGaAs系APDでは現
在、小受光系化による低容量化、半導体層厚最適化によ
るキャリア走行時間の低減、ヘテロ界面への中間層導入
によるキャリア・トラップの抑制、プレーナ構造の採用
により、利得帯域幅(GB)積800GHz程度、最大
帯域8GHz程度の高速・高信頼性の素子が実用化され
ている。
2. Description of the Related Art In order to construct an optical communication system of high speed, high sensitivity and high reliability, a semiconductor light receiving element having high speed response, low dark current and high reliability is indispensable. For this reason,
Recently, low loss wavelength range of silica fiber 1.3-1.6μ
InP / InGaAs avalanche photodiodes (APDs) and pin photodiodes (pinPDs), which can be applied to m, have been actively researched for higher speed and higher sensitivity. InP / InGaAs APDs are currently gaining by reducing the capacity by reducing the light receiving system, reducing the carrier transit time by optimizing the semiconductor layer thickness, suppressing carrier traps by introducing an intermediate layer at the hetero interface, and adopting a planar structure. A high-speed and highly reliable element having a bandwidth (GB) product of about 800 GHz and a maximum bandwidth of about 8 GHz has been put into practical use.

【0003】しかしながら、この素子構造では、アバラ
ンシェ増倍層であるInPのイオン化率比β/αが〜2
と小さいため(α:電子のイオン化率、β:正孔のイオ
ン化率比)、GB積の最大値が80〜100GHzに制
限され、また、過剰雑音指数X(イオン化率比が小さい
ほど大きくなる)が〜0.7と大きくなり、高速化・低
雑音化・高感度化には限界がある。これは、他のバルク
のIII −V族化合物半導体をアバランシェ増倍層に用い
た場合も同様であり、高GB積化(高速応答特性)・低
雑音化を達成するにはイオン化率比α/βを人工的に増
大させる必要がある。
However, in this device structure, the ionization rate ratio β / α of InP, which is the avalanche multiplication layer, is about 2 or less.
Is small (α: electron ionization rate, β: hole ionization rate ratio), the maximum value of the GB product is limited to 80 to 100 GHz, and the excess noise figure X (the smaller the ionization rate ratio, the larger). Becomes as large as ~ 0.7, and there is a limit to speeding up, noise reduction, and high sensitivity. This is the same when other bulk III-V group compound semiconductors are used for the avalanche multiplication layer, and in order to achieve high GB product (fast response characteristics) and low noise, the ionization rate ratio α / It is necessary to artificially increase β.

【0004】そこでカパッソ(F.Capasso)等
は、アプライド・フィジックス・レター(Appl.P
hys.Lett.)、40(1)巻、p.38〜4
0、1992年で超格子による伝導帯エネルギー不連続
量ΔEcを電子の衝突イオン化に利用してイオン化率比
α/βを人工的に増大させる構造を提案し、実際にGa
As/GaAlAs系超格子でイオン化率比α/βの増
大(バルクGaAsの〜2に対して超格子で〜8)を確
認した。
[0004] Therefore, F. Capasso and the like, Applied Physics Letter (Appl. P
hys. Lett. ), 40 (1), p. 38-4
In 0, 1992, we proposed a structure to artificially increase the ionization rate ratio α / β by utilizing the conduction band energy discontinuity ΔEc due to superlattice for electron impact ionization.
It was confirmed that the ionization rate ratio α / β was increased in the As / GaAlAs-based superlattice (up to 8 in the superlattice compared to ˜2 in bulk GaAs).

【0005】さらに、香川らは、ジャーナル・オブ・ク
ォンタム・エレクトロニクス(J.Quantum.E
lectron.)、28(6)巻、p.1419−1
423、1992年で、長距離光通信に用いられる波長
1.3〜1.6μm帯に受光感度を有するInGaAs
P/InAlAs系超格子を用いて同様の構造を形成
し、やはりイオン化率比α/βの増大(バルクInGa
Asの〜2に対して超格子層で〜10)を報告した。そ
の素子構造を図2に示す。図2において、21はn+
InP基板、22はn+ 型InPバッファー層、23は
- 型InGaAsP/InAlAs超格子アバランシ
ェ増倍層、24はp型InP電界降下層、25はp-
InGaAs光吸収層、26はp+ 型InPキャップ
層、27はp+ 型InGaAsコンタクト層、28はn
側電極、29はp側電極、210はSiNパッシベーシ
ョン膜である。この超格子構造では、伝導帯不連続量Δ
Ecが0.39eVと価電子帯不連続量ΔEvの0.0
3eVより大きく、井戸層に入ったときバンド不連続に
より獲得するエネルギーが電子の方が正孔より大きく、
これによって電子がイオン化しきい値エネルギーに達し
やすくなることで電子イオン化率が増大し、イオン化率
比α/βの増大とそれによる低雑音化が図られている。
Furthermore, Kagawa et al., Journal of Quantum Electronics (J. Quantum.
electron. ), 28 (6), p. 1419-1
423, 1992, InGaAs having a photosensitivity in the wavelength band 1.3 to 1.6 μm used for long-distance optical communication.
A similar structure was formed using a P / InAlAs superlattice, and the ionization rate ratio α / β was also increased (bulk InGa
Reported ~ 10) in superlattice layers for ~ 2 As. The element structure is shown in FIG. In FIG. 2, 21 is an n + type InP substrate, 22 is an n + type InP buffer layer, 23 is an n type InGaAsP / InAlAs superlattice avalanche multiplication layer, 24 is a p type InP electric field drop layer, and 25 is a p type. InGaAs light absorption layer, 26 is p + type InP cap layer, 27 is p + type InGaAs contact layer, and 28 is n
A side electrode, 29 is a p-side electrode, and 210 is a SiN passivation film. In this superlattice structure, the conduction band discontinuity Δ
Ec of 0.39 eV and valence band discontinuity ΔEv of 0.0
Electrons are larger than holes, and the energy acquired by the band discontinuity when entering the well layer is larger than 3 eV.
This makes it easier for electrons to reach the ionization threshold energy, thereby increasing the electron ionization rate, and increasing the ionization rate ratio α / β and resulting noise reduction.

【0006】[0006]

【発明が解決しようとする課題】しかしながら、この構
造のアバランシェフォトダイオードは、メサ側壁の半導
体23,24,25/SiN表面パッシベーション膜2
10界面における界面準位、半導体表面の残留酸化膜・
欠陥を介してリーク電流が発生し、実用的な増倍率領域
(10〜20)において暗電流が0.8〜数μAオーダ
程度に増加し、この暗電流による雑音増加がイオン化率
比改善による低雑音効果を打ち消してしまうという欠点
を有する。また、このパッシベーション界面は、従来報
告されているように一般的な信頼性試験の条件(例えば
雰囲気温度200℃、逆方向電流100μAのバイアス
条件)のもとでは経時的に不安定であり、暗電流増加に
よる素子特性の信頼性が十分でないという欠点を有す
る。
However, in the avalanche photodiode having this structure, the semiconductor 23, 24, 25 / SiN surface passivation film 2 on the side wall of the mesa is formed.
10 interface levels, residual oxide film on semiconductor surface
Leakage current is generated through the defect, and the dark current increases to about 0.8 to several μA in the practical multiplication factor region (10 to 20), and the noise increase due to this dark current is reduced due to the improvement of the ionization ratio. It has the drawback of canceling the noise effect. In addition, this passivation interface is unstable over time under the conditions of a general reliability test (for example, an ambient temperature of 200 ° C. and a bias current of 100 μA in the reverse direction) as previously reported, and is dark. It has a drawback that the reliability of device characteristics due to an increase in current is not sufficient.

【0007】一方、図3に示す、中村等がECOC(E
uropean Conference on Opt
ical Communication)、TuC5−
4、p.261−264、1991年で報告したポリイ
ミド膜310をメサパッシベーション膜として用いた超
格子APDの構造においても、界面準位、半導体表面の
残留酸化膜・欠陥を介して発生するリーク暗電流・信頼
性の問題は図2の例の場合と本質的に同様である。なお
図3において、31はn+ 型InP基板、32はn+
InPバッファー層、33はn- 型InGaAs/In
AlAs超格子アバランシェ増倍層、34はp型InA
lAs電界降下層、35はp- 型InGaAs光吸収
層、36はp+ 型InAlAsキャップ層、37はp+
型InGaAsコンタクト層、38はn側電極、39は
p側電極、311は反射防止膜である。
On the other hand, as shown in FIG. 3, Nakamura et al.
european Conference on Opt
ical Communication), TuC5-
4, p. 261-264, in the structure of a superlattice APD using the polyimide film 310 as a mesa passivation film, reported in 1991, leak dark current and reliability generated via interface states, residual oxide film on the semiconductor surface, and defects. Is essentially the same as the case of the example of FIG. In FIG. 3, 31 is an n + type InP substrate, 32 is an n + type InP buffer layer, and 33 is an n type InGaAs / In.
AlAs superlattice avalanche multiplication layer, 34 is p-type InA
lAs electric field drop layer, 35 p type InGaAs light absorption layer, 36 p + type InAlAs cap layer, 37 p +
InGaAs contact layer, 38 is an n-side electrode, 39 is a p-side electrode, and 311 is an antireflection film.

【0008】そこで、本発明の目的は、メサ型pn接合
フォトダイオードで問題となる表面リーク暗電流を低減
し低暗電流・高信頼な超格子アバランシェフォトダイオ
ードを実現することにある。
Therefore, an object of the present invention is to realize a superlattice avalanche photodiode having a low dark current and a high reliability by reducing the surface leak dark current which is a problem in the mesa type pn junction photodiode.

【0009】本発明の他の目的は、このような超格子ア
バランシェフォトダイオードの製造方法を提供すること
にある。
Another object of the present invention is to provide a method of manufacturing such a superlattice avalanche photodiode.

【0010】[0010]

【課題を解決するための手段】本発明は、p+ 型InP
基板に、p- 型InGaAs光吸収層、p型InP電界
緩和層、アンドープn- 型InAlAs/InAlGa
As超格子増倍層、n+ 型InPキャップ層、n+ 型I
nGaAs(P)コンタクト層を順次積層した構造を有
する超格子アバランシェフォトダイオードにおいて、前
記超格子増倍層、n+ 型InPキャップ層、n+ 型In
GaAs(P)コンタクト層のみをエッチング除去して
形成したメサを、p- 型InPもしくはp-型InAl
Asで埋め込んだ構造を有することを特徴とする。
The present invention is a p + type InP
On the substrate, p type InGaAs light absorption layer, p type InP electric field relaxation layer, undoped n type InAlAs / InAlGa
As superlattice multiplication layer, n + type InP cap layer, n + type I
In a superlattice avalanche photodiode having a structure in which nGaAs (P) contact layers are sequentially laminated, the superlattice multiplication layer, n + type InP cap layer, n + type In
The mesa formed by etching away only the GaAs (P) contact layer is used as p type InP or p type InAl.
It is characterized by having a structure embedded with As.

【0011】本発明の超格子アバランシェフォトダイオ
ードの製造方法は、p+ 型InP基板に、p- 型InG
aAs光吸収層、p型InP電界緩和層、アンドープn
- 型InAlAs/InAlGaAs超格子増倍層、n
+ 型InPキャップ層、n+ 型InGaAs(P)コン
タクト層を順次積層し、前記超格子増倍層、n+ 型In
Pキャップ層、n+ 型InGaAs(P)コンタクト層
のみをエッチング除去してメサを形成し、このメサをp
- 型InPもしくはp- 型InAlAsで埋め込むこと
を特徴とする。
A method of manufacturing a superlattice avalanche photodiode according to the present invention comprises a p + -type InP substrate and a p -type InG.
aAs light absorption layer, p-type InP electric field relaxation layer, undoped n
- type InAlAs / InAlGaAs superlattice multiplication layer, n
A + -type InP cap layer and an n + -type InGaAs (P) contact layer are sequentially stacked to form the superlattice multiplication layer and the n + -type In layer.
Only the P cap layer and the n + type InGaAs (P) contact layer are removed by etching to form a mesa.
- and wherein the embedding in the type InAlAs - -type InP or p.

【0012】[0012]

【作用】本発明は、上述の構成により従来例より特性を
改善した。図1は本発明の素子構造図である。
The present invention has improved characteristics as compared with the conventional example by the above-mentioned structure. FIG. 1 is a structural diagram of an element of the present invention.

【0013】図1において、11はp+ 型InP基板、
12はp+ 型InPバッファー層、13はp- 型InG
aAs光吸収層、14はp型InP電界降下層、15は
アンドープn- 型InAlAs/InAlGaAs超格
子アバランシェ増倍層、16はn+ 型InPキャップ
層、17はn+ 型InGaAsコンタクト層、18はn
側電極、19はp側電極であり、110はp- 型InP
埋め込み層、111は反射防止膜である。
In FIG. 1, 11 is a p + type InP substrate,
12 is p + type InP buffer layer, 13 is p type InG
aAs light absorption layer, 14 p-type InP field drop layer, 15 undoped n type InAlAs / InAlGaAs superlattice avalanche multiplication layer, 16 n + type InP cap layer, 17 n + type InGaAs contact layer, 18 n
A side electrode, 19 is a p-side electrode, and 110 is p -type InP
The burying layer 111 is an antireflection film.

【0014】この図1と従来例を示す図2,図3を用い
て本発明の作用を説明する。従来構造では、パッシベー
ション膜SiN膜210、もしくは、ポリイミド膜31
0と、メサ側壁の半導体の界面には多数の界面準位(2
×1012cm-2/eV以上)が存在する。この界面準位
は、通常の半導体/SiN膜(もしくはポリイミド膜)
界面のダングリングボンドと、メサ形成後に生成した半
導体自然酸化膜/半導体界面のダングリングボンド、さ
らには、表面欠陥に起因するもの等が挙げられる。特
に、逆バイアス時に空乏化する半導体層(23〜25,
33〜35)中で、比較的禁制帯幅の小さなp- 型In
GaAs光吸収層25,35中には前者が、また、自然
酸化されやすいアルミニウム原子を含む超格子増倍層2
3,33中では後者が多く存在すると考えられる。した
がって、従来構造では、逆バイアスのもとではこれらの
界面準位を介する表面リーク暗電流が発生し、実用的増
倍率を得るような高電界化にはμAオーダとなってしま
う。また、経時的にもこれらの界面準位や表面欠陥が増
加することで暗電流劣化が生じ、素子の信頼性は十分な
ものが得にくい。
The operation of the present invention will be described with reference to FIG. 1 and FIGS. 2 and 3 showing a conventional example. In the conventional structure, the passivation film SiN film 210 or the polyimide film 31
0 and many interface states (2
X10 12 cm -2 / eV or more) is present. This interface level is a normal semiconductor / SiN film (or polyimide film)
Examples include dangling bonds at the interface, dangling bonds at the semiconductor natural oxide film / semiconductor interface formed after mesa formation, and those caused by surface defects. In particular, semiconductor layers (23 to 25,
33-35), p - type In having a relatively small forbidden band width
The former is also present in the GaAs light absorption layers 25 and 35, and the superlattice multiplication layer 2 containing aluminum atoms which are easily oxidized naturally.
It is considered that the latter is abundant among 3,33. Therefore, in the conventional structure, under the reverse bias, a surface leak dark current is generated via these interface states, and it becomes on the order of μA for increasing the electric field to obtain a practical multiplication factor. Further, dark current deterioration occurs due to an increase in these interface states and surface defects over time, and it is difficult to obtain sufficient reliability of the device.

【0015】これに対して図1に示す本発明の構造で
は、上記の界面準位や表面欠陥の原因となるダングリン
グボンドは基板と格子整合するp- 型InP埋め込み層
で終端されるために、これらの界面準位や表面欠陥は著
しく低減される。また、半導体p- 型InP埋め込み層
をメサ側壁に再結晶成長する際、分子線気相成長法(M
BE法)では基板加熱もしくは水素ラジカルビームを照
射することで、メサ側壁に生成した自然酸化膜を除去す
ることが可能なため、半導体自然酸化膜/半導体界面の
ダングリングボンドも低減できる。このとき、p- 型I
nP埋め込み層は、n+ 型コンタクト層17、n+ 型キ
ャップ層16、アンドープn- 型超格子増倍層15との
間でpn接合を形成し、逆バイアス印加により空乏層が
形成されるが、p濃度を1×1016cm-3程度にしてお
くことで、逆バイアス電界が印加されてもその電界強度
がInPのトンネル耐圧、あるいは、アバランシェ耐圧
(両者ともに超格子増倍層の増倍電界強度よりは大き
い)まではリーク電流は数十nA程度に抑制することが
できる。
On the other hand, in the structure of the present invention shown in FIG. 1, the dangling bonds that cause the above-mentioned interface states and surface defects are terminated by the p -- type InP buried layer which is lattice-matched with the substrate. , These interface states and surface defects are significantly reduced. Further, when the semiconductor p type InP buried layer is recrystallized on the mesa side wall, the molecular beam vapor deposition method (M
In the BE method), by heating the substrate or irradiating a hydrogen radical beam, the natural oxide film formed on the side wall of the mesa can be removed, so that dangling bonds at the semiconductor natural oxide film / semiconductor interface can be reduced. At this time, p - type I
The nP buried layer forms a pn junction with the n + type contact layer 17, the n + type cap layer 16, and the undoped n type superlattice multiplication layer 15, and a depletion layer is formed by applying a reverse bias. , P concentration is set to about 1 × 10 16 cm −3 , the electric field strength of InP tunnel breakdown voltage or avalanche breakdown voltage (both are multiplication of superlattice multiplication layer) even when a reverse bias electric field is applied. The leakage current can be suppressed to about several tens of nA up to the electric field strength).

【0016】以上の効果により、従来のSiN膜もしく
はポリイミド膜を表面保護膜とするメサ型のフォトダイ
オード構造と比較して、本発明の構造では表面リーク暗
電流が減少する。さらに、もともとp- 型InP層/メ
サ側壁の界面の欠陥や界面準位が著しく低減されている
ためにこれらの経時的増加が従来と比較して抑制され、
素子信頼性が向上した半導体受光素子が実現できる。
Due to the above effects, the surface leakage dark current is reduced in the structure of the present invention as compared with the conventional mesa type photodiode structure in which the surface protection film is the SiN film or the polyimide film. Furthermore, since the defects and interface states of the p -type InP layer / mesa side wall interface are originally significantly reduced, their increase over time is suppressed as compared with the conventional case.
A semiconductor light receiving element having improved element reliability can be realized.

【0017】[0017]

【実施例】以下、本発明の実施例として、InPに格子
整合するInAlAs/InAlGaAs超格子アバラ
ンシェフォトダイオードを用いて説明する。
EXAMPLE An InAlAs / InAlGaAs superlattice avalanche photodiode which is lattice-matched to InP will be described below as an example of the present invention.

【0018】図1に示す本発明である半導体受光素子を
以下の工程によって製作した。p+型InP基板11上
に、p+ 型InPバッファー層12を0.5μm厚に、
キャリア濃度〜2×1015cm-3のp- 型InGaAs
光吸収層13を1μm厚に、キャリア濃度〜5×1017
cm-3のp+ 型InP電界降下層14を0.2μm、キ
ャリア濃度〜1×1015cm-3のアンドープn- 型In
AlGaAs/InAlAs超格子増倍層15を0.2
3μm厚に、キャリア濃度〜5×1018cm-3のn+
InPキャリア層16を0.5μm厚に、キャリア濃度
〜1×1019cm-3のn+ 型InGaAsコンタクト層
17を0.1μm厚に順次、ガスソース分子線成長法
(ガスソースMBE)を用いて成長する。
The semiconductor light receiving element of the present invention shown in FIG. 1 was manufactured by the following steps. On the p + type InP substrate 11, the p + type InP buffer layer 12 having a thickness of 0.5 μm,
Carrier concentration ~ 2 x 10 15 cm -3 p - type InGaAs
The thickness of the light absorption layer 13 is 1 μm, and the carrier concentration is up to 5 × 10 17
cm −3 p + type InP electric field drop layer 14 is 0.2 μm, carrier concentration is up to 1 × 10 15 cm −3 undoped n type In.
The AlGaAs / InAlAs superlattice multiplication layer 15 is 0.2
The n + -type InP carrier layer 16 having a carrier concentration of 5 × 10 18 cm −3 has a thickness of 0.5 μm, and the n + -type InGaAs contact layer 17 having a carrier concentration of 1 × 10 19 cm −3 has a thickness of 0.3 μm. The film is sequentially grown to a thickness of 1 μm using a gas source molecular beam growth method (gas source MBE).

【0019】次に、通常のフォトリソグラフィーとウエ
ットエッチングの技術を用いて直径50μmの円形メサ
を形成する。このメサエッチングのエッチング深さは、
+型InP電界降下層14の上面が露出する深さ、す
なわち、0.83μmとする。このウェハに、ガスソー
スMBEを用いて、p- 型InP埋め込み層110を
0.5μm程度再成長する。再成長の前には成長装置内
で半導体表面の自然酸化膜を基板加熱や水素ラジカルビ
ーム処理等の方法で除去しておく。
Next, a circular mesa having a diameter of 50 μm is formed by using ordinary photolithography and wet etching techniques. The etching depth of this mesa etching is
The depth at which the upper surface of the p + type InP field drop layer 14 is exposed, that is, 0.83 μm is set. A p -type InP burying layer 110 is regrown to about 0.5 μm on this wafer by using a gas source MBE. Before re-growth, the native oxide film on the semiconductor surface is removed by a method such as substrate heating or hydrogen radical beam treatment in the growth apparatus.

【0020】以上により、得られたウェハ表面に反射防
止膜111をSiN膜で形成し、p側電極19をAuZ
nで形成する。最後に裏面研磨を行ってからn側電極1
8をAuGeNiで形成する。
As described above, the antireflection film 111 is formed of a SiN film on the surface of the obtained wafer, and the p-side electrode 19 is AuZ.
n. Finally, after backside polishing, n-side electrode 1
8 is formed of AuGeNi.

【0021】[0021]

【発明の効果】上記の実施例の構造と、従来例のSiN
膜・ポリイミド膜のいずれかでメサ側壁パッシベーショ
ン膜を施した構造で、その高速応答特性と暗電流特性と
素子信頼性について比較を行った。高速応答特性につい
ては両者の差はなくともに、GB積120GHz程度の
高速性が確認されたのに対して、暗電流の初期値として
は、本実施例の素子は、いずれの従来例よりも小さい値
が得られた(同一メサ直径で比較)。さらに、素子信頼
性に関しても、信頼性試験(例えば、雰囲気温度200
℃、逆方向電流100μAのバイアス条件で1000時
間)の後も、従来例では、暗電流の増加がしばしば観測
されたのに対して、本発明では暗電流増加による素子特
性の劣化はほとんど観測されなかった。
The structure of the above embodiment and the conventional SiN
We compared the high-speed response characteristics, dark current characteristics, and device reliability of the structure in which a mesa side wall passivation film was applied to either a film or a polyimide film. Regarding the high-speed response characteristics, there was no difference between the two, and a high-speed property of a GB product of about 120 GHz was confirmed, while the initial value of the dark current was smaller in the device of this example than in any of the conventional examples. Values were obtained (compare with same mesa diameter). Furthermore, regarding the element reliability, a reliability test (for example, an ambient temperature of 200
Even after 1000 hours under a bias condition of a reverse current of 100 μA and a reverse current of 100 ° C., in the conventional example, an increase in dark current was often observed, whereas in the present invention, deterioration of device characteristics due to an increase in dark current was almost observed. There wasn't.

【0022】これより、本発明によって、波長1.3〜
1.6μm帯に受光感度を有し、高イオン化率比α/β
で低雑音・高速応答特性と同時に、表面リーク暗電流が
小さく、高信頼性を有するアバランシェフォトダイオー
ドを実現することができ、その効果は大きい。
Therefore, according to the present invention, the wavelength of 1.3 to
Has a photosensitivity in the 1.6 μm band and a high ionization ratio α / β
Thus, it is possible to realize a highly reliable avalanche photodiode having a low surface leak dark current as well as low noise and high speed response characteristics, and its effect is great.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の超格子アバランシェフォトダイオード
の構造図である。
FIG. 1 is a structural diagram of a superlattice avalanche photodiode of the present invention.

【図2】従来例の超格子増倍層の構造図である。FIG. 2 is a structural diagram of a conventional superlattice multiplication layer.

【図3】従来例の超格子増倍層の構造図である。FIG. 3 is a structural diagram of a conventional superlattice multiplication layer.

【符号の説明】[Explanation of symbols]

11 p+ 型InP基板 12 p+ 型InPバッファー層 13 p- 型InGaAs光吸収層 14 p型InPワイドギャップ電界降下層 15 アンドープn- 型InAlAs/InAlGaA
s超格子アバランシェ増倍層 16 n+ 型InPキャップ層 17 n+ 型InGaAsコンタクト層 18 n側電極 19 p側電極 110 p- 型InP埋め込み層 111 反射防止膜 21 n+ 型InP基板 22 n+ 型InPバッファー層 23 n- 型InGaAsP/InAlAs超格子アバ
ランシェ増倍層 24 p型InP電界降下層 25 p- 型InGaAs光吸収層 26 p+ 型InPキャップ層 27 p+ 型InGaAsコンタクト層 28 n側電極 29 p側電極 210 SiNパッシベーション膜 31 n+ 型InP基板 32 n+ 型InAlAsバッファー層 33 n- 型InGaAs/InAlAs超格子アバラ
ンシェ増倍層 34 p型InAlAs電界降下層 35 p- 型InGaAs光吸収層 36 p+ 型InAlAsキャップ層 37 p+ 型InGaAsコンタクト層 38 n側電極 39 p側電極 310 ポリイミドパッシベーション膜 311 反射防止膜
11 p + type InP substrate 12 p + type InP buffer layer 13 p type InGaAs light absorption layer 14 p type InP wide gap field drop layer 15 undoped n type InAlAs / InAlGaA
s Superlattice avalanche multiplication layer 16 n + type InP cap layer 17 n + type InGaAs contact layer 18 n side electrode 19 p side electrode 110 p type InP buried layer 111 antireflection film 21 n + type InP substrate 22 n + type InP buffer layer 23 n - type InGaAsP / InAlAs superlattice avalanche multiplication layer 24 p-type InP field drop layer 25 p - type InGaAs light absorption layer 26 p + type InP cap layer 27 p + type InGaAs contact layer 28 n-side electrode 29 p-side electrode 210 SiN passivation film 31 n + type InP substrate 32 n + type InAlAs buffer layer 33 n type InGaAs / InAlAs superlattice avalanche multiplication layer 34 p type InAlAs electric field drop layer 35 p type InGaAs light absorption layer 36 p + Type InAlAs cap layer 37 p + Type InGaAs contact layer 38 n-side electrode 39 p-side electrode 310 polyimide passivation film 311 antireflection film

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】メサ型の超格子アバランシェフォトダイオ
ードにおいて、メサを構成する超格子増倍層、n+ 型I
nPキャップ層、n+ 型InGaAs(P)コンタクト
層が、p- 型InPもしくはp- 型InAlAsで埋め
込まれていることを特徴とする超格子アバランシェフォ
トダイオード。
1. In a mesa-type superlattice avalanche photodiode, a superlattice multiplication layer constituting a mesa, an n + -type I
A superlattice avalanche photodiode characterized in that an nP cap layer and an n + -type InGaAs (P) contact layer are filled with p -type InP or p -type InAlAs.
【請求項2】p+ 型InP基板に、p- 型InGaAs
光吸収層、p型InP電界緩和層、アンドープn- 型I
nAlAs/InAlGaAs超格子増倍層、n+ 型I
nPキャップ層、n+ 型InGaAs(P)コンタクト
層を順次積層した構造を有する超格子アバランシェフォ
トダイオードにおいて、 前記超格子増倍層、n+ 型InPキャップ層、n+ 型I
nGaAs(P)コンタクト層のみをエッチング除去し
て形成したメサを、p- 型InPもしくはp-型InA
lAsで埋め込んだ構造を有することを特徴とする超格
子アバランシェフォトダイオード。
2. A p + -type InP substrate and a p -type InGaAs
Light absorption layer, p-type InP electric field relaxation layer, undoped n - type I
nAlAs / InAlGaAs superlattice multiplication layer, n + type I
A superlattice avalanche photodiode having a structure in which an nP cap layer and an n + -type InGaAs (P) contact layer are sequentially stacked, wherein the superlattice multiplication layer, the n + -type InP cap layer, and the n + -type I
The mesa formed by etching away only the nGaAs (P) contact layer is used as p type InP or p type InA.
A superlattice avalanche photodiode characterized by having a structure embedded with lAs.
【請求項3】p+ 型InP基板に、p- 型InGaAs
光吸収層、p型InP電界緩和層、アンドープn- 型I
nAlAs/InAlGaAs超格子増倍層、n+ 型I
nPキャップ層、n+ 型InGaAs(P)コンタクト
層を順次積層し、前記超格子増倍層、n+ 型InPキャ
ップ層、n+ 型InGaAs(P)コンタクト層のみを
エッチング除去してメサを形成し、このメサをp- 型I
nPもしくはp- 型InAlAsで埋め込むことを特徴
とする超格子アバランシェフォトダイオードの製造方
法。
3. A p + -type InP substrate on which p -type InGaAs is formed.
Light absorption layer, p-type InP electric field relaxation layer, undoped n - type I
nAlAs / InAlGaAs superlattice multiplication layer, n + type I
An nP cap layer and an n + -type InGaAs (P) contact layer are sequentially stacked, and only the superlattice multiplication layer, the n + -type InP cap layer and the n + -type InGaAs (P) contact layer are removed by etching to form a mesa. And use this mesa as p - type I
A method for manufacturing a superlattice avalanche photodiode, which comprises burying with nP or p type InAlAs.
【請求項4】前記メサを埋め込む前に、メサ側面に生成
した自然酸化膜を除去することを特徴とする請求項3記
載の超格子アバランシェフォトダイオードの製造方法。
4. The method of manufacturing a superlattice avalanche photodiode according to claim 3, wherein the natural oxide film formed on the side surface of the mesa is removed before the mesa is buried.
JP5016664A 1993-02-04 1993-02-04 Superlattice avalanche photodiode and method of manufacturing the same Expired - Lifetime JP2894910B2 (en)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0408213A2 (en) * 1989-07-13 1991-01-16 Eastman Kodak Company Process of preparing a tabular grain silver bromoiodide emulsion and emulsions produced thereby
JPH08152361A (en) * 1994-11-29 1996-06-11 Nippon Telegr & Teleph Corp <Ntt> Apparatus for measuring waveform of optical signal
JPH08162663A (en) * 1994-12-09 1996-06-21 Nec Corp Semiconductor photodetector
US6800914B2 (en) 2002-05-24 2004-10-05 Opnext Japan, Inc. Semiconductor photodetector device and manufacturing method thereof
JP2006295216A (en) * 1995-02-02 2006-10-26 Sumitomo Electric Ind Ltd Pin type light receiving element and method of manufacturing pin type light receiving element
CN113826220A (en) * 2019-06-19 2021-12-21 康普泰克解决方案公司 Optoelectronic devices

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6150382A (en) * 1984-08-20 1986-03-12 Fujitsu Ltd PIN diode
JPH04241473A (en) * 1991-01-16 1992-08-28 Nec Corp Avalanche photo diode

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6150382A (en) * 1984-08-20 1986-03-12 Fujitsu Ltd PIN diode
JPH04241473A (en) * 1991-01-16 1992-08-28 Nec Corp Avalanche photo diode

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0408213A2 (en) * 1989-07-13 1991-01-16 Eastman Kodak Company Process of preparing a tabular grain silver bromoiodide emulsion and emulsions produced thereby
JPH08152361A (en) * 1994-11-29 1996-06-11 Nippon Telegr & Teleph Corp <Ntt> Apparatus for measuring waveform of optical signal
JPH08162663A (en) * 1994-12-09 1996-06-21 Nec Corp Semiconductor photodetector
JP2006295216A (en) * 1995-02-02 2006-10-26 Sumitomo Electric Ind Ltd Pin type light receiving element and method of manufacturing pin type light receiving element
US6800914B2 (en) 2002-05-24 2004-10-05 Opnext Japan, Inc. Semiconductor photodetector device and manufacturing method thereof
CN113826220A (en) * 2019-06-19 2021-12-21 康普泰克解决方案公司 Optoelectronic devices

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