JPH06230421A - Method of manufacturing thin film transistor matrix - Google Patents
Method of manufacturing thin film transistor matrixInfo
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- JPH06230421A JPH06230421A JP1502093A JP1502093A JPH06230421A JP H06230421 A JPH06230421 A JP H06230421A JP 1502093 A JP1502093 A JP 1502093A JP 1502093 A JP1502093 A JP 1502093A JP H06230421 A JPH06230421 A JP H06230421A
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Abstract
(57)【要約】
【目的】 薄膜トランジスタ(TFT) マトリクスの製法に
関し,工程数の増加を抑制してTFT マトリクスの透過率
を高くし, 液晶パネルの高輝度化, 高性能化を図ること
を目的とする。
【構成】 透明絶縁性の基板 1上に, 原子層デポジショ
ン(ALD) 法を用い, 補助容量の電極となるZnO:Al膜から
なる透明導電膜11とAl2O3 からなる補助容量の誘電体膜
12を成膜し,基板上にゲート電極 2を形成し,その上に
ゲート絶縁膜 4,動作半導体層 5 ,チャネル保護膜 6を
順次成膜し,ゲート電極直上のチャネル保護膜を残すよ
うにパターニングし,基板上に高濃度半導体からなるコ
ンタクト層7と金属膜 8を順に成膜し,パターニングし
て, ドレイン電極とソース電極を形成し,基板上に透明
電極膜を成膜して, ソース電極に接続するようにパター
ニングして画素電極10を形成し,前記透明導電膜との間
で補助容量を構成する。
(57) [Summary] [Objective] Regarding the manufacturing method of a thin film transistor (TFT) matrix, the object is to suppress the increase in the number of steps and increase the transmittance of the TFT matrix to achieve high brightness and high performance of the liquid crystal panel. And [Structure] Atomic layer deposition (ALD) method was used on the transparent insulating substrate 1 to form the transparent conductive film 11 made of ZnO: Al film and the auxiliary capacitor dielectric film made of Al 2 O 3 as the auxiliary capacitor electrode. Body membrane
12 is formed, the gate electrode 2 is formed on the substrate, the gate insulating film 4, the operating semiconductor layer 5, and the channel protective film 6 are sequentially formed on the substrate, leaving the channel protective film directly above the gate electrode. After patterning, a contact layer 7 made of a high-concentration semiconductor and a metal film 8 are sequentially formed on the substrate, patterning is performed to form a drain electrode and a source electrode, a transparent electrode film is formed on the substrate, and a source is formed. The pixel electrode 10 is formed by patterning so as to be connected to the electrode, and an auxiliary capacitance is formed with the transparent conductive film.
Description
【0001】[0001]
【産業上の利用分野】本発明はアクティブマトリクス駆
動方式による液晶パネル等に構成される薄膜トランジス
タ(TFT) マトリクスの製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor (TFT) matrix formed in a liquid crystal panel or the like by an active matrix driving method.
【0002】ラップトップパーソナルコンピュータや壁
掛けテレビに使用するTFT マトリクス型液晶パネルの開
発が進められている。近年,TFT マトリクス型液晶パネ
ルは高輝度, 高画質なものが求められ, その製造技術の
開発が進められている。Development of a TFT matrix type liquid crystal panel for use in a laptop personal computer and a wall-mounted television is in progress. In recent years, TFT-matrix liquid crystal panels are required to have high brightness and high image quality, and the development of their manufacturing technology is in progress.
【0003】[0003]
【従来の技術】アクティブマトリクス駆動方式による液
晶パネルはドット表示を行う個々の画素に対応してマト
リクス状にTFT を配置し,各画素にメモリ機能を持たせ
コントラスト良く多ラインの表示を可能としている。2. Description of the Related Art A liquid crystal panel based on an active matrix driving system has TFTs arranged in a matrix corresponding to individual pixels for dot display, and each pixel has a memory function to enable multi-line display with good contrast. .
【0004】図4(A) 〜(C) はTFT マトリクスの説明図
である。図4(A) は平面図, 図4(B) はA-A 断面図でTF
T 部, 図4(C) はB-B 断面図で補助容量(CS)部である。FIGS. 4A to 4C are explanatory views of the TFT matrix. Figure 4 (A) is a plan view and Figure 4 (B) is a cross-sectional view taken along the line AA and TF.
The T part, Fig. 4 (C), is a sectional view taken along the line BB, which shows the auxiliary capacitance (CS) part.
【0005】TFT マトリクス型液晶パネルは, X,Y方
向に交差してマトリクス状に配置された多数のゲートバ
スライン 2とドレインバスライン 9に駆動電圧を印加し
て,両バスライン交差部に接続されたTFT を選択駆動す
ることにより, 対応する所望の画素をドット表示するよ
うに構成されている。このようなTFT マトリクスの構造
は, 例えば, 透明絶縁性のガラス基板上に多数のゲート
バスラインとドレインバスラインとが窒化シリコン(Si
N) 等からなる層間絶縁膜を介してX,Y方向に交差し
た形に配置され, 両バスラインの交差部にTFT が接続さ
れている。また,TFT の動作半導体層にアモルファスシ
リコン(a-Si)層を用いる場合には,ゲート絶縁膜にプラ
ズマ気相成長(P-CVD) 法による窒化シリコン膜(SiN) あ
るいは窒化シリコンオキシナイトライド(SiNO)膜が用い
られていた。The TFT matrix type liquid crystal panel is connected to both bus line intersections by applying a drive voltage to a large number of gate bus lines 2 and drain bus lines 9 arranged in a matrix so as to intersect in the X and Y directions. By selectively driving the selected TFT, the corresponding desired pixel is displayed in dots. Such a TFT matrix structure has a structure in which a large number of gate bus lines and drain bus lines are formed on a transparent insulating glass substrate by using silicon nitride (Si
The TFTs are connected at the intersections of both bus lines, which are arranged so as to intersect in the X and Y directions through an interlayer insulating film made of N) or the like. Moreover, when an amorphous silicon (a-Si) layer is used as the operating semiconductor layer of the TFT, a silicon nitride film (SiN) or a silicon nitride oxynitride (P-CVD) film is used as the gate insulating film. A SiNO) film was used.
【0006】なお,図中, 6はチャネル保護膜でSiN
膜, 8はTFT のドレイン電極(左側)およびソース電極
(右側)を示す。図5(A) 〜(E) は従来のTFT 素子の製
造工程を説明する断面図である。In the figure, 6 is a channel protective film made of SiN.
Membrane, 8 shows the drain electrode (left side) and source electrode (right side) of the TFT. 5 (A) to 5 (E) are cross-sectional views illustrating a conventional process for manufacturing a TFT element.
【0007】図の左側はTFT 部,右側は対応する補助容
量部である。図5(A) において,透明絶縁性基板として
ガラス基板 1上にスパッタリングにより, 例えばチタン
(Ti)膜を連続して成膜し,フォトリソグラフィによりレ
ジスト膜をパターニングした後, レジスト膜をマスクに
してエッチングしてゲート電極 2と補助容量下部電極 3
を形成する。The left side of the figure is the TFT section, and the right side is the corresponding auxiliary capacitance section. As shown in FIG. 5 (A), a transparent insulating substrate, such as titanium, is sputtered on the glass substrate 1.
(Ti) film is continuously formed, and after patterning the resist film by photolithography, etching is performed by using the resist film as a mask to etch the gate electrode 2 and auxiliary capacitor lower electrode 3
To form.
【0008】図5(B) において,レジスト膜を剥離し,
P-CVD 法により, ゲート絶縁膜および補助容量誘電体膜
としてSiN 膜 4, 動作半導体層としてa-Si膜 5, チャネ
ル保護膜としてSiN 膜 6を連続成長する。ここで, 第1
層目絶縁膜は, CVD SiN 膜 4と原子層デポジション(AL
D) 法によるアルミナ(Al2O3) 膜との積層膜を用いても
よい。In FIG. 5B, the resist film is peeled off,
By the P-CVD method, a SiN film 4 as a gate insulating film and a storage capacitor dielectric film, an a-Si film as an operating semiconductor layer 5, and a SiN film 6 as a channel protective film are continuously grown. Where the first
The second layer insulating film is composed of CVD SiN film 4 and atomic layer deposition (AL
D) Method according to alumina (Al 2 O 3) may be a stacked film of a film.
【0009】次いで,ゲート電極 2の直上のチャネル保
護膜 6を残すようにパターニングする。図5(C) におい
て,基板上にコンタクト層として n+ 型a-Si層 7とソー
スドレイン電極用金属膜として例えばTi膜 8を連続成膜
する。Next, patterning is performed so as to leave the channel protective film 6 directly above the gate electrode 2. In FIG. 5C, an n + -type a-Si layer 7 as a contact layer and a Ti film 8 as a source / drain electrode metal film are successively formed on the substrate.
【0010】次いで,コンタクト層 7とソースドレイン
電極用金属膜 8をパターニングして, ドレイン電極(左
側)とソース電極(右側)を形成する。図5(D) におい
て,基板上に金属膜, 例えばAl膜 9を成膜し,パターニ
ングしてドレインバスラインを形成する。Next, the contact layer 7 and the source / drain electrode metal film 8 are patterned to form a drain electrode (left side) and a source electrode (right side). In FIG. 5 (D), a metal film, for example, an Al film 9 is formed on the substrate and patterned to form a drain bus line.
【0011】図5(E) において,基板上に透明電極膜と
して酸化インジウムと酸化錫の固溶体からなるITO 膜10
を成膜して, 蓄積容量部上とソース電極を残してパター
ニングし, 画素電極を形成する。以上でTFT マトリクス
の主要部の工程を終わる。In FIG. 5 (E), an ITO film 10 made of a solid solution of indium oxide and tin oxide is formed as a transparent electrode film on the substrate.
A film is formed, and patterning is performed leaving the storage capacitor and the source electrode, and the pixel electrode is formed. This completes the process of the main part of the TFT matrix.
【0012】[0012]
【発明が解決しようとする課題】従来のTFT マトリクス
においては,補助容量の電極が金属で構成されているた
め,TFT の開口率が低下し,その結果液晶パネルの透過
率が低下するという問題があった。In the conventional TFT matrix, since the electrode of the auxiliary capacitance is made of metal, there is a problem that the aperture ratio of the TFT is lowered and, as a result, the transmittance of the liquid crystal panel is lowered. there were.
【0013】本発明は工程数の増加を抑制してTFT マト
リクスの透過率を高くし, 液晶パネルの高輝度化, 高性
能化を図ることを目的とする。It is an object of the present invention to suppress the increase in the number of steps and increase the transmittance of the TFT matrix to achieve high brightness and high performance of the liquid crystal panel.
【0014】[0014]
【課題を解決するための手段】上記課題の解決は,透明
絶縁性の基板 1上に, 原子層デポジション(ALD) 法を用
い, 補助容量の電極となるZnO:Al膜からなる透明導電膜
11とAl2O3 からなる補助容量の誘電体膜12を連続して成
膜する工程と, 次いで, 該基板 1上にゲート電極 2を形
成し,その上にゲート絶縁膜 4, 動作半導体層 5 ,チャ
ネル保護膜 6を順次成膜する工程と,次いで, 該ゲート
電極直上の該チャネル保護膜を残すように, 該チャネル
保護膜をパターニングする工程と, 次いで,該基板上に
高濃度半導体からなるコンタクト層 7と金属膜 8を順に
成膜する工程と, 次いで, 該コンタクト層と該金属膜を
パターニングして, ドレイン電極と, ソース電極を形成
する工程と, 次いで,該基板上に透明電極膜を成膜し
て, 該透明電極膜を該ソース電極に接続するようにパタ
ーニングして画素電極10を形成し,該画素電極と前記透
明導電膜との間で補助容量を構成する工程とを有する薄
膜トランジスタマトリクスの製造方法により達成され
る。[Means for Solving the Problems] The above problems are solved by using an atomic layer deposition (ALD) method on a transparent insulating substrate 1 and using a transparent conductive film made of a ZnO: Al film as an electrode of an auxiliary capacitance.
11 and a step of continuously forming a dielectric film 12 of an auxiliary capacitor made of Al 2 O 3 , and then forming a gate electrode 2 on the substrate 1, a gate insulating film 4, an operating semiconductor layer on the gate electrode 2. 5, the step of sequentially forming the channel protective film 6, then the step of patterning the channel protective film so as to leave the channel protective film directly above the gate electrode, and then the high-concentration semiconductor on the substrate. Forming a contact layer 7 and a metal film 8 in that order, then patterning the contact layer and the metal film to form a drain electrode and a source electrode, and then forming a transparent electrode on the substrate. Forming a film, patterning so that the transparent electrode film is connected to the source electrode to form the pixel electrode 10, and forming an auxiliary capacitance between the pixel electrode and the transparent conductive film. Method of manufacturing thin film transistor matrix having More is achieved.
【0015】[0015]
【作用】本発明では, 補助容量の電極膜を透明導電膜
(ZnO:Al)で形成し,且つ工程の増加を防ぐため補助電
極膜および誘電体膜(Al2O3 )をALD 法により連続成長
している。In the present invention, the electrode film of the auxiliary capacitor is formed of the transparent conductive film (ZnO: Al), and the auxiliary electrode film and the dielectric film (Al 2 O 3 ) are continuously formed by the ALD method in order to prevent an increase in the number of processes. Growing.
【0016】従って, 補助容量の電極膜を透明導電膜で
あるため,TFT マトリクスの開口率が低下することな
く,また,補助容量の電極膜をパターニングする必要は
なく工程数は全体として増えることはない。さらに, Zn
O:AlとAl2O3 をALD 装置内で連続成膜する際, 使用する
原料ガスは3種類のみでよいという利点がある。Therefore, since the electrode film of the auxiliary capacitance is a transparent conductive film, the aperture ratio of the TFT matrix does not decrease, and it is not necessary to pattern the electrode film of the auxiliary capacitance, and the number of steps is not increased as a whole. Absent. In addition, Zn
O: When the Al and Al 2 O 3 are continuously formed in the ALD apparatus is advantageous in that the raw material gas to be used may only three types.
【0017】[0017]
実施例(1) :図1は本発明の実施例(1) の説明図であ
る。Embodiment (1): FIG. 1 is an illustration of an embodiment (1) of the present invention.
【0018】図において,ゲート電極 2を形成する前
に, ALD 法を用い, 透明の絶縁性基板1上に補助容量の
透明導電膜としてZnO:Al膜11と誘電体膜としてAl2O3 膜
12を連続して成膜する。In the figure, before forming the gate electrode 2, the ZnO: Al film 11 as the transparent conductive film of the auxiliary capacitance and the Al 2 O 3 film as the dielectric film are used on the transparent insulating substrate 1 by the ALD method.
12 is continuously formed.
【0019】次に, ZnO:Al/Al2O3の成長条件の一例を示
す。 ここで,DEZ はジエチル亜鉛, TMA はトリメチルアルミ
ニウムである。Next, an example of growth conditions of ZnO: Al / Al 2 O 3 will be shown. Here, DEZ is diethylzinc and TMA is trimethylaluminum.
【0020】この後の工程は, 従来例の工程から補助容
量電極部の形成を取り除いたものと同様である。図2
(A) 〜(C),図3(D) 〜(F) は本発明の実施例(2) の説明
図である。The subsequent steps are the same as those of the conventional example except that the formation of the auxiliary capacitance electrode portion is removed. Figure 2
FIGS. 3A to 3C and FIGS. 3D to 3F are explanatory views of the embodiment (2) of the present invention.
【0021】図の左側は断面図,右側は対応する平面図
である。図2(A) において,ALD 法を用い, 透明絶縁性
基板としてのガラス基板 1上に透明の絶縁性基板 1上に
補助容量の透明導電膜としてZnO:Al膜11と, 誘電体膜と
してAl2O3 膜12を連続して成膜する。The left side of the figure is a sectional view and the right side is a corresponding plan view. In Fig. 2 (A), the ZnO: Al film 11 as the transparent conductive film of the auxiliary capacitance and the Al as the dielectric film are formed on the transparent insulating substrate 1 on the glass substrate 1 as the transparent insulating substrate by using the ALD method. The 2 O 3 film 12 is continuously formed.
【0022】次にスパッタリングにより厚さ1500ÅのTi
膜を成膜し,フォトリソグラフィによりレジスト膜をパ
ターニングした後, レジスト膜をマスクにしてエッチン
グしてゲート電極 2を形成する。Next, sputtered Ti with a thickness of 1500Å
After forming a film and patterning the resist film by photolithography, the gate electrode 2 is formed by etching using the resist film as a mask.
【0023】図2(B) において,レジスト膜を剥離し,
P-CVD 法により, ゲート絶縁膜として厚さ4000ÅのSiN
膜 4, 動作半導体層として厚さ 150Åのa-Si膜 5, チャ
ネル保護膜として厚さ1200Åの SiN 膜 6を連続成長す
る。ここで, ゲート絶縁膜は, CVD SiN 膜 4と原子層デ
ポジション法によるアルミナ(Al2O3) 膜との積層膜を用
いてもよい。In FIG. 2B, the resist film is peeled off,
By the P-CVD method, SiN with a thickness of 4000 Å is used as a gate insulating film.
Film 4, an a-Si film with a thickness of 150Å as an operating semiconductor layer 5, and a SiN film 6 with a thickness of 1200Å as a channel protective film are continuously grown. Here, the gate insulating film may be a laminated film of a CVD SiN film 4 and an alumina (Al 2 O 3 ) film formed by the atomic layer deposition method.
【0024】図2(C) において,ゲート電極 2の直上の
チャネル保護膜 6を残すようにパターニングする。図3
(D) において,基板上にコンタクト層として厚さ 600Å
の n+ 型a-Si層 7と厚さ1500ÅのTi膜からなるソースド
レイン電極用金属膜 8を連続成膜する。In FIG. 2C, patterning is performed so that the channel protection film 6 immediately above the gate electrode 2 remains. Figure 3
In (D), the thickness of the contact layer on the substrate is 600Å
The n + type a-Si layer 7 and the metal film 8 for the source / drain electrode consisting of a Ti film having a thickness of 1500 Å are continuously formed.
【0025】次いで,SiN 膜 4とa-Si層 5と n+ 型a-Si
層 7とTi膜をパターニングして, ドレイン電極とソース
電極を形成する。この工程で実施例(1) および従来工程
と相違する点は, TFT 部以外のSiN 膜 4が除去されるこ
とである。Next, the SiN film 4, the a-Si layer 5, and the n + -type a-Si
Layer 7 and the Ti film are patterned to form the drain and source electrodes. The difference between this step and Example (1) and the conventional step is that the SiN film 4 other than the TFT part is removed.
【0026】従って, 実施例(2) では,補助容量の誘電
体膜はAl2O3 膜12のみとなり,容量が大きくなる利点が
ある。図3(E) において,基板上に金属膜, 例えばAl膜
9を成膜し,パターニングしてドレインバスラインを形
成する。Therefore, in the embodiment (2), the dielectric film of the auxiliary capacitance is only the Al 2 O 3 film 12, which has an advantage of increasing the capacitance. In Fig. 3 (E), a metal film such as an Al film is formed on the substrate.
9 is deposited and patterned to form a drain bus line.
【0027】図3(F) において,基板上に透明電極膜と
してITO 膜10を成膜して, 蓄積容量部上とソース電極8S
を残してパターニングし, 画素電極を形成する。以上で
TFTマトリクスの主要部の工程を終わる。In FIG. 3 (F), an ITO film 10 is formed as a transparent electrode film on the substrate, and is formed on the storage capacitor portion and the source electrode 8S.
The pixel electrode is formed by patterning with leaving. Above
The process of the main part of the TFT matrix is completed.
【0028】[0028]
【発明の効果】本発明によれば,TFT 素子の製造におい
て工程数の増加を抑制してTFT マトリクスの透過率を高
くし, 液晶パネルの高輝度化, 高性能化に寄与すること
ができた。According to the present invention, it is possible to suppress an increase in the number of steps in manufacturing a TFT device and increase the transmittance of the TFT matrix, thereby contributing to higher brightness and higher performance of the liquid crystal panel. .
【図1】 本発明の実施例1の説明図FIG. 1 is an explanatory diagram of a first embodiment of the present invention.
【図2】 本発明の実施例2の説明図(1)FIG. 2 is an explanatory diagram of Embodiment 2 of the present invention (1)
【図3】 本発明の実施例2の説明図(2)FIG. 3 is an explanatory diagram (2) of the second embodiment of the present invention.
【図4】 TFT マトリクスの説明図[Figure 4] Explanatory drawing of the TFT matrix
【図5】 従来のTFT 素子の製造工程を説明する断面図FIG. 5 is a cross-sectional view illustrating a manufacturing process of a conventional TFT device.
1 透明絶縁性基板でガラス基板 2 ゲート電極でTi膜 3 蓄積容量下部電極 4 ゲート絶縁膜でSiN 膜 5 動作半導体層でa-Si膜 6 チャネル保護膜でSiN 膜 7 コンタクト層で n+ 型a-Si層 8 ソースドレイン電極用金属膜でTi膜 9 ドレインバスラインでAl膜 10 画素電極でITO 膜 11 補助容量の電極膜となる透明導電膜でZnO:Al膜 12 補助容量の誘電体膜でAl2O3 膜1 Transparent insulating substrate, glass substrate 2 Gate electrode, Ti film 3 Storage capacitor lower electrode 4 Gate insulating film, SiN film 5 Operating semiconductor layer, a-Si film 6 Channel protective film, SiN film 7 Contact layer, n + type a -Si layer 8 Metal film for source / drain electrode Ti film 9 Al film on drain bus line 10 ITO film on pixel electrode 11 Transparent conductive film to be the electrode film of auxiliary capacitance ZnO: Al film 12 Dielectric film of auxiliary capacitance Al 2 O 3 film
Claims (1)
ジション(ALD) 法を用い, 補助容量の電極となるZnO:Al
膜からなる透明導電膜(11)とAl2O3 からなる補助容量の
誘電体膜(12)を連続して成膜する工程と,次いで, 該基
板(1) 上にゲート電極(2) を形成し,その上にゲート絶
縁膜(4), 動作半導体層(5) , チャネル保護膜(6) を順
次成膜する工程と,次いで, 該ゲート電極直上の該チャ
ネル保護膜を残すように, 該チャネル保護膜をパターニ
ングする工程と,次いで,該基板上に高濃度半導体から
なるコンタクト層(7) と金属膜(8) を順に成膜する工程
と,次いで, 該コンタクト層と該金属膜をパターニング
して, ドレイン電極と, ソース電極を形成する工程と,
次いで,該基板上に透明電極膜を成膜して, 該透明電極
膜を該ソース電極に接続するようにパターニングして画
素電極(10)を形成し,該画素電極と前記透明導電膜との
間で補助容量を構成する工程とを有することを特徴とす
る薄膜トランジスタマトリクスの製造方法。1. A transparent insulating substrate (1) is prepared by using an atomic layer deposition (ALD) method to form a ZnO: Al electrode serving as an auxiliary capacitance electrode.
A step of continuously forming a transparent conductive film (11) made of a film and a dielectric film (12) of an auxiliary capacitor made of Al 2 O 3 , and then forming a gate electrode (2) on the substrate (1). Forming the gate insulating film (4), the operating semiconductor layer (5), and the channel protective film (6) in that order, and then leaving the channel protective film directly above the gate electrode, A step of patterning the channel protective film, a step of sequentially forming a contact layer (7) made of a high-concentration semiconductor and a metal film (8) on the substrate, and then a step of forming the contact layer and the metal film. Patterning, forming a drain electrode and a source electrode,
Next, a transparent electrode film is formed on the substrate, and the pixel electrode (10) is formed by patterning the transparent electrode film so as to connect the transparent electrode film to the source electrode. And a step of forming a storage capacitor between them, the method of manufacturing a thin film transistor matrix.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1502093A JPH06230421A (en) | 1993-02-02 | 1993-02-02 | Method of manufacturing thin film transistor matrix |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1502093A JPH06230421A (en) | 1993-02-02 | 1993-02-02 | Method of manufacturing thin film transistor matrix |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06230421A true JPH06230421A (en) | 1994-08-19 |
Family
ID=11877172
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1502093A Withdrawn JPH06230421A (en) | 1993-02-02 | 1993-02-02 | Method of manufacturing thin film transistor matrix |
Country Status (1)
| Country | Link |
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| JP (1) | JPH06230421A (en) |
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