JPH0622238A - Peak correction circuit for slave pattern for television receiver - Google Patents

Abstract

PURPOSE:To provide a slave pattern video with excellent quality without white level distortion and black level distortion by using a peak limiter or a gamma correction circuit so as to obtain a slave pattern signal with a proper contrast in response to lightness of a visual pattern. CONSTITUTION:The circuit consists of a pattern ABL detection circuit 1, a slave pattern APL detection circuit 2, a peak limiter voltage generating circuit 3, a peak limiter circuit 4, a master pattern APL detection circuit and a slave pattern gamma correction circuit. When the master pattern is dark, that is, when the ABL or APL is low, the peak limiter voltage generating circuit 3 outputs the voltage itself of the slave pattern APL detection circuit 2 to operate the peak limiter circuit 4 or the slave pattern gamma correction circuit thereby suppressing a peak of the slave pattern. Conversely, when the ABL or the APL of the master pattern is high, the peak limiter voltage generating circuit 3 inactivates the peak limiter 4 or the slave pattern gamma correction circuit thereby outputting the slave pattern luminance signal as it is.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a child screen display circuit for a television receiver.

[0002]

2. Description of the Related Art Recently, an increasing number of television receivers have a built-in screen function. However, with respect to the image quality of the child screen, particularly the contrast, it is general that the image is output with a constant amplitude (contrast) regardless of the parent screen.

[0003]

However, in such a conventional sub-screen circuit, for example, when the main screen receives an image that is very bright and ABL works, and the sub-screen is an image that is very dark and has no peaks. The inset screen looks dull. On the contrary, when the main screen is very dark and the ABL is not effective, when the sub screen has a high peak contrast, the peak of the sub screen may be skipped and whitening may occur. Had.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a good-quality small-screen image having proper contrast at all times without causing the small-size screen to be broken.

[0005]

In order to achieve the above-mentioned object, the present invention provides 1) a screen ABL detection circuit and 2) a child screen AP.
An L detection circuit, 3) peak limiter voltage generation circuit, 4) peak limiter circuit, 5) parent screen APL detection circuit, and 6) child screen γ correction circuit.

[0006]

According to the present invention, with the above configuration, when the contrast of the sub-picture luminance signal is the APL or ABL detection signal of the sub-picture and the APL detection signal of the sub-picture, the sub-picture is bright when the sub-picture APL is low and the sub-picture is low. The black limit is prevented without applying the screen limiter or γ correction, and when the main screen is dark and the APL of the child screen is high, the limiter or γ correction is effective to control the white crushing to obtain a good image reception state of the child screen. Is to say.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to FIGS.
Will be described with reference to.

As shown in FIGS. 1, 2, 5 and 6, the present invention is 1) a parent screen ABL detection circuit or 5) a parent screen APL detection circuit 2) a child screen APL detection circuit 3) a peak limiter voltage generation circuit 4). Peak limiter circuit or 6) Sub-screen gamma correction circuit, 4) Peak limiter or 6) Sub-screen gamma correction circuit until the luminance signal from the sub-screen video chroma jungle is input to the sub-screen A / D Is inserted. In the case of FIGS. 3, 4, 7, and 8, the child screen D / A is inserted in the subsequent stage. The small screen APL detection circuit 2 detects the APL of the brightness signal of the small screen, and the peak limiter voltage generation circuit 3 generates a peak limiter voltage based on the detected APL. Then, the peak limiter 4 or the sub-screen γ correction circuit 6 suppresses the peak of the luminance signal or performs γ correction. At this time, the parent screen ABL detection circuit 1 detects the ABL of the parent screen and generates a voltage, and the parent screen APL detects the APL of the parent screen.
The detection circuit 5. When the main screen is dark, that is, when ABL or APL is low, the peak limiter voltage generation circuit 3
The voltage itself of the small screen APL detection circuit is output to operate the peak limiter circuit 4 or the small screen γ correction circuit 6 to suppress the peak of the small screen. Conversely, ABL or APL on the main screen
When is high, the peak limiter voltage generation circuit 3 prevents the peak limiter 4 or the small screen γ correction circuit 6 from operating, and outputs the small screen luminance signal as it is. This allows
Even in a scene in which the APL of the inset screen is high and the inset screen is dark and ABL does not work, whiteout of the inset screen does not occur. On the contrary, when the APL of the main screen is high and the image of the low APL comes to the child screen, it is possible to avoid the loss of gradation.

[0009]

As is apparent from the above embodiments, according to the present invention, the parent screen ABL detection circuit 1 or the parent screen APL is used.
The peak limiter 4 or the γ correction circuit 6 controlled by the detection circuit 5 and the sub-screen APL detection circuit can obtain a sub-screen signal having an appropriate contrast according to the brightness of the main screen, and is a good quality without white crush or black crush. The child screen image of can be provided to the user.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of a circuit according to an embodiment of the present invention.

FIG. 2 is a configuration block diagram of a circuit according to an embodiment of the present invention.

FIG. 3 is a configuration block diagram of a circuit according to an embodiment of the present invention.

FIG. 4 is a configuration block diagram of a circuit according to an embodiment of the present invention.

FIG. 5 is a configuration block diagram of a circuit according to an embodiment of the present invention.

FIG. 6 is a configuration block diagram of a circuit according to an embodiment of the present invention.

FIG. 7 is a configuration block diagram of a circuit according to an embodiment of the present invention.

FIG. 8 is a configuration block diagram of a circuit according to an embodiment of the present invention.

[Explanation of symbols]

 1 parent screen ABL detection circuit 2 child screen APL detection circuit 3 peak limiter voltage generation circuit 4 peak limiter circuit 5 parent screen APL detection circuit 6 child screen γ correction circuit

Claims (8)

[Claims] 1. A child screen APL detection circuit and a parent screen AB
A television receiver child screen having a peak limiter circuit controlled by the peak limiter voltage generated by the L detection circuit, in which the peak limiter is inserted before the A / D input for child screen processing in the television receiver child screen display circuit. Screen display circuit. 2. A child screen APL detection circuit and a parent screen AP
A television receiver child screen having a peak limiter circuit controlled by the peak limiter voltage generated by the L detection circuit, in which the peak limiter is inserted before the A / D input for child screen processing in the television receiver child screen display circuit. Screen display circuit. 3. A child screen APL detection circuit and a parent screen AB
A television receiver child screen in which the peak limiter is inserted after the D / A output for child screen processing in the television receiver child screen display circuit having a peak limiter circuit controlled by the peak limiter voltage generated by the L detection circuit. Display circuit. 4. A child screen APL detection circuit and a parent screen AP
A television receiver child screen in which the peak limiter is inserted after the D / A output for child screen processing in the television receiver child screen display circuit having a peak limiter circuit controlled by the peak limiter voltage generated by the L detection circuit. Display circuit. 5. A child screen APL detection circuit and a parent screen AB
For a television receiver having a γ-correction circuit controlled by the peak limiter voltage generated by the L detection circuit, in which the γ-correction circuit is inserted before the A / D input for child-screen processing. Sub-screen display circuit. 6. A child screen APL detection circuit and a parent screen AP
For a television receiver having a γ-correction circuit controlled by the peak limiter voltage generated by the L detection circuit, in which the γ-correction circuit is inserted before the A / D input for child-screen processing. Sub-screen display circuit. 7. A child screen APL detection circuit and a parent screen AB
Television receiver child having a γ correction circuit controlled by the peak limiter voltage generated by the L detection circuit, in which the γ correction circuit is inserted after the D / A output for child screen processing in the television receiver child screen display circuit. Screen display circuit. 8. A child screen APL detection circuit and a parent screen AP
Television receiver child having a γ correction circuit controlled by the peak limiter voltage generated by the L detection circuit, in which the γ correction circuit is inserted after the D / A output for child screen processing in the television receiver child screen display circuit. Screen display circuit.