JPH0621461A - Thin-film transistor - Google Patents

Abstract

PURPOSE:To provide a thin-film transistor of bottom-gate type in which source and drain regions have their respective offset lengths to decrease leakage current. CONSTITUTION:A source region 107a and a drain region 108a are formed on the surface of a CVD silicon oxide film 103. The ends of the source and drain regions are extended by thermal diffusion to a given depth from the upper edge of a groove, which extends to a gate electrode 102a through the silicon oxide film 103.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bottom gate type thin film transistor.

[0002]

2. Description of the Related Art Since a polycrystalline silicon thin film transistor can be formed on an insulator,
It is used as a load element of a memory integrated circuit, or is used as a liquid crystal drive transistor arranged in each display unit called a pixel in a liquid crystal display element.

FIG. 4 shows a sectional view of the element structure of a general thin film transistor called a bottom gate type. A gate electrode 202 made of polycrystalline silicon is arranged on the base insulator 201. After depositing a polycrystalline silicon layer 205 on the gate oxide film 204, a source region 207 and a drain region 20 which are heavily doped with carrier impurities.
8 is formed, and at the same time, the channel region 205a is formed. Further, as the cover film 209, a silicon oxide film is deposited on the upper portion, and the source region 207 and the drain region 208 are formed.
The aluminum electrode 210 is formed by performing opening processing on the portion. In the structure thus formed, the movement of carriers between the source region 207 and the drain region 208 is controlled by the electric field from the gate electrode 202,
It operates as a MOS transistor.

However, as compared with a MOS transistor formed by using a silicon substrate crystal, a thin film transistor using polycrystalline silicon has a large leak current, and a characteristic structural ingenuity has been made. It has a source region 207 and a drain region 208, as shown in FIG.
Offset regions 220 are provided separately from the ends of the gate electrode 202. Since the thin film transistor uses polycrystalline silicon, it contains many crystal defects such as crystal grain boundaries, and the effect of the electric field influences the generation mechanism of the leakage current. It is inferred from the conduction behavior. In fact, taking such an offset structure is effective in reducing the leakage current.
Known from experience.

[0005]

A problem in the manufacturing technique for forming the above offset region is that the source / drain regions are formed in alignment with the underlying gate electrode pattern, but there is a positional error. Can be unavoidable.

In a general MOS transistor formed by using a silicon substrate crystal, carrier impurities can be doped by an ion implantation method using a gate electrode arranged above the substrate as a mask. Therefore, the source / drain regions can be formed in self-alignment with the pattern of the gate electrode. This is one of the factors that allows transistor elements having little variation in characteristics to be integrated at an extremely high density, and it has been required to form self-aligned source / drain regions also in thin film transistors.

[0007]

In order to solve the above-mentioned problems of the prior art, the present invention employs a thin film transistor structure in which an insulator having a groove is embedded and a gate electrode is arranged at the bottom of the insulator. The source / drain regions located at are formed by self-alignment by impurity diffusion from above.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

Referring to FIG. 1 which is a sectional view in order of steps for explaining a method of manufacturing a thin film transistor, a first embodiment of the present invention is described below.
Gate electrode 102a made of a 2 μm polycrystalline silicon layer
To form. Next, the CVD silicon oxide film 103 is formed on the entire surface.
Is deposited to a thickness of 0.5 μm. A groove is formed by aligning with the gate electrode 102a by using a lithography technique and a dry etching technique to form a groove, and the surface of the gate electrode 102a is exposed at the bottom. The required alignment accuracy at this time may include the groove-shaped bottom portion on the upper surface of the gate electrode 102a, and does not directly affect the device characteristics. [FIG. 1 (a)].

Next, a reduced pressure CV as a gate oxide film is formed on the entire surface.
A D silicon oxide film 104a is formed to a film thickness of 0.1 μm, and a polycrystalline silicon layer 105 is deposited to a thickness of 0.2 μm.
As a method for producing the polycrystalline silicon layer 105, amorphous silicon is deposited by thermal decomposition of disilane at 535 ° C. and then annealed at 620 ° C. for 15 hours in a nitrogen atmosphere to be crystallized. After forming the polycrystalline silicon layer 105, a CVD silicon oxide film 106 is deposited on the entire surface to fill the groove. The deposited film thickness at this time must be determined in consideration of factors such as the opening size of the groove shape. Usually, it is set to about 2 to 3 times the opening size [Fig. 1 (b)].

Next, the CVD silicon oxide film 106 is removed while being flattened from above by an etch bag method, so that the polycrystalline silicon layer 105 is exposed and the trench is formed by CVD.
It can be filled with the silicon oxide film 106a. Then, the polycrystalline silicon layer 105 is patterned by dry etching to form a transistor formation region.
Boron is ion-implanted into this surface to convert the polycrystalline silicon layer 105 around the opening of the groove into ion-implanted regions 107 and 108 containing boron of about 5 × 10 ²⁰ / cm ³ (FIG. 1C). .

Next, by annealing at 920 ° C. for 40 minutes, the implanted ions are activated and diffused downward to form the source region 107a and the drain region 108a. At the same time, the channel region 105a is formed. After this, a CVD film having a thickness of 0.4 μm is formed as a cover film.
A silicon oxide film 109a is deposited and the source region 107
The aluminum electrode 110 is arranged on the drain region 108a (FIG. 1D).

According to the first embodiment, the distance from the gate end of the source / drain region is set by the thickness of the silicon oxide film forming the groove and the diffusion length from the ion implantation region around the opening. Therefore, the offset area can be sourced without causing misalignment like the conventional structure.
Can be set equally on both sides of the drain. Further, since it can be formed by stacking on the underlying gate electrode, there is also an advantage that a required element region area can be reduced.

Referring to FIG. 2 which is a cross-sectional view of the thin film transistor, the second embodiment of the present invention has an asymmetric groove shape. The thin film transistor according to this embodiment is similar to the first embodiment in that the gate electrode 102b and the CVD are used.
The silicon oxide film 103 is formed.

Then, a thin silicon nitride film (not shown) is deposited on the entire surface, and a polycrystalline silicon wiring 112 is formed on the side where a drain region is formed by depositing and processing a polycrystalline silicon film having a predetermined thickness. Then, a CVD silicon oxide film 113 is deposited on the entire surface. Next, the polycrystalline silicon wiring 1
This CVD silicon oxide film 1 is exposed until the upper surface of 12 is exposed.
13 is etched back. Then, using a photoresist (not shown) as a mask, the CVD silicon oxide film 113 and the silicon nitride film in the region where the groove and the source region are formed are removed by etching.

The subsequent steps are generally the same as those of the first embodiment. A groove is formed in the CVD silicon oxide film 103, a CVD silicon oxide film 104b having a film thickness of 0.1 μm to be a gate oxide film is deposited on the entire surface, and an opening reaching the polycrystalline silicon wiring 112 is formed in the CVD silicon oxide film 104b. After the portion is provided, a polycrystalline silicon layer having a film thickness of 0.2 μm is formed on the entire surface. A CVD silicon oxide film 106b in a state of being filled with a groove is formed, and this polycrystalline silicon layer is subjected to patterning, ion implantation, and activation processing to obtain a P-type source region 107b, a P-type drain region 108b,
Then, a channel region 105b is formed, and a CVD silicon oxide film 109b and an aluminum electrode 110 are formed.

In the second embodiment, the length of the offset region on the drain region side is longer than the length of the offset region on the source region side by the film thickness of the polycrystalline silicon wiring. Therefore, for example, when an operating bias is used with a fixed value with respect to the source / drain in a thin film transistor, it is the drain region, which is the PN junction in the reverse bias state, that affects the leak current, and a larger distance is provided on the drain side. It is effective to set the leakage current while suppressing unnecessary parasitic resistance.

A sectional view of the third embodiment of the present invention is shown in FIG. The present embodiment is a novel structure for achieving a longer gate length with a small area. Here, the shape of the gate electrode 102c arranged at the bottom of the groove shape is further processed into a groove shape to increase the contact area through the thin film transistor and the gate oxide film 104c. The CVD silicon oxide film 106c, the P-type source region 107c, the P-type drain region 108c, the channel region 105c, the CVD silicon oxide film 109c, etc. are formed essentially in the same manner as in the first embodiment.

[0019]

As described above, in the thin film transistor of the present invention, the lengths of the offset regions of the source and drain regions are the thickness of the silicon oxide film forming the groove and the diffusion length from the upper end of the opening of the groove. Uniquely determined by the difference. Therefore, the generation of the leak current depending on the alignment as in the related art can be suppressed with good controllability.

[Brief description of drawings]

1A to 1D are cross-sectional views in order of processes for explaining a first embodiment of the present invention.

FIG. 2 is a sectional view for explaining a second embodiment of the present invention.

FIG. 3 is a sectional view for explaining a third embodiment of the present invention.

FIG. 4 is a sectional view illustrating a conventional thin film transistor.

[Explanation of symbols]

101, 201 Base insulators 102a, 102b, 102c, 202 Gate electrodes 103, 104a, 104b, 104c, 106, 10
6a, 106b, 106c, 109a, 109b, 10
9c, 113 CVD silicon oxide film 105, 205 Polycrystalline silicon layer 105a, 105b, 105c, 205a Channel region 107, 108 Ion implantation region 107a, 107b, 107c, 207 Source region 108a, 108b, 108c, 208 Drain region 110, 210 Aluminum wiring 112 Polycrystalline silicon wiring 204 Gate oxide film 209 Cover film 220 Offset region

Claims (1)

[Claims] 1. A thin film transistor which is embedded in an insulator having a groove and has a gate electrode at the bottom of the groove, and source / drain regions are formed in self alignment with the gate electrode.