JPH0621431A - Mesa-type semiconductor element and its manufacture - Google Patents
Mesa-type semiconductor element and its manufactureInfo
- Publication number
- JPH0621431A JPH0621431A JP40768590A JP40768590A JPH0621431A JP H0621431 A JPH0621431 A JP H0621431A JP 40768590 A JP40768590 A JP 40768590A JP 40768590 A JP40768590 A JP 40768590A JP H0621431 A JPH0621431 A JP H0621431A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- electrode
- brazing material
- local
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims abstract description 50
- 238000005219 brazing Methods 0.000 claims abstract description 24
- 239000000463 material Substances 0.000 claims abstract description 24
- 238000005530 etching Methods 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 9
- 230000002265 prevention Effects 0.000 claims description 6
- 230000008018 melting Effects 0.000 claims description 3
- 238000002844 melting Methods 0.000 claims description 3
- 238000005453 pelletization Methods 0.000 claims description 2
- 239000008188 pellet Substances 0.000 abstract description 12
- 239000007772 electrode material Substances 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000007598 dipping method Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 230000003449 preventive effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 230000000007 visual effect Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000012850 discrimination method Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、特にSR複合回路装置
(STACK)に使用されるメサ型半導体素子の製造方
法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a mesa type semiconductor device used in an SR composite circuit device (STACK).
【0002】[0002]
【従来の技術】従来、メサ型半導体素子(ペレット)の
製造は、例えばN型のウェハの両面に夫々ドナー,アク
セプター不純物を全面拡散し、その上にメッキあるいは
蒸着にて局部電極を形成し、その上に外部電極との接続
のためにろう材を浸漬法等により形成し、更にろう材を
含めた電極をマスクしながらエッチングによりペレット
化することにより形成していた。2. Description of the Related Art Conventionally, in the manufacture of a mesa type semiconductor device (pellet), for example, donor and acceptor impurities are entirely diffused on both sides of an N type wafer, and a local electrode is formed thereon by plating or vapor deposition. A brazing material is formed thereon by a dipping method or the like for connection with an external electrode, and is further pelletized by etching while masking the electrode including the brazing material.
【0003】ところで、こうして得られたペレットの判
別は、従来目視あるいは電気的特性により行なわれてい
るのが一般的であるが、電気的特性特性による判別方法
は量産的でないため、目視による判別が主流である。By the way, the pellets thus obtained are generally discriminated by visual observation or electrical characteristics, but the discrimination method based on the electrical characteristic characteristics is not mass-produced, and therefore the visual discrimination is performed. Mainstream.
【0004】[0004]
【発明が解決しようとする課題】しかし、従来の半導体
素子においては、基板表裏に形成された局部電極の形状
が同一であるため、その後のエッチング工程において片
面からの選択エッチング等の工夫を用いても上から見る
と同一形状になり、表裏の選別が難しい。従って、複合
回路半導体装置例えば整流ブリッジ等を作る場合、回路
通りペレットを並べるのに時間がかかったり、不良が多
発する場合があった。However, in the conventional semiconductor device, since the shapes of the local electrodes formed on the front and back surfaces of the substrate are the same, a method such as selective etching from one side is used in the subsequent etching process. Also has the same shape when viewed from above, making it difficult to sort the front and back. Therefore, when making a composite circuit semiconductor device such as a rectifying bridge, it may take a long time to arrange the pellets according to the circuit, or defects may frequently occur.
【0005】本発明は上記事情に鑑みてなされたもの
で、基板の両面の第1電極部,第2電極部の形状を異な
らせることにより、ペレット選別を容易に行うことがで
き、作業性を向上しうるメサ型半導体素子及びその製造
方法を提供することを目的とする。The present invention has been made in view of the above circumstances, and by making the shapes of the first electrode portion and the second electrode portion on both surfaces of the substrate different, it is possible to easily perform pellet selection and improve workability. An object of the present invention is to provide a mesa type semiconductor device that can be improved and a method for manufacturing the same.
【0006】[0006]
【課題を解決するための手段】本願第1の発明は、両面
に第1導電型の高濃度領域,第2導電型の高濃度領域を
夫々形成した第1導電型の半導体基板と、この半導体基
板の両面に夫々形成された互いに形状の異なる第1・第
2電極部とを具備することを特徴とするメサ型半導体素
子である。SUMMARY OF THE INVENTION A first invention of the present application is a semiconductor substrate of a first conductivity type in which a high concentration region of a first conductivity type and a high concentration region of a second conductivity type are formed on both surfaces, respectively, and this semiconductor. A mesa-type semiconductor device, comprising: first and second electrode portions having different shapes formed on both surfaces of a substrate, respectively.
【0007】本願第2の発明は、第1導電型の半導体基
板の両面に夫々第1導電型の高濃度領域,第2導電型の
高濃度領域を形成する工程と、前記基板の両面に夫々局
部電極を選択的に形成する工程と、これらの局部電極上
にろう材を溶融,形成し第1電極部,第2電極部を形成
する工程と、前記基板裏面側の局部電極及びろう材を覆
うエッチング防止層を形成する工程と、前記基板の等方
性エッチングを基板裏面側の高濃度領域の直前まで行う
工程と、露出する基板表面のろう材を再度溶融する工程
と、前記エッチング防止層を除去した後ペレット化する
工程とを具備する事を特徴とするメサ型半導体素子の製
造方法である。A second invention of the present application is the step of forming a high-concentration region of the first conductivity type and a high-concentration region of the second conductivity type on both surfaces of the semiconductor substrate of the first conductivity type, and on both surfaces of the substrate, respectively. A step of selectively forming the local electrodes, a step of melting and forming a brazing material on these local electrodes to form the first electrode portion and the second electrode portion, and a step of forming the local electrodes and the brazing material on the back surface side of the substrate. A step of forming an etching preventive layer for covering, a step of performing isotropic etching of the substrate just before the high concentration region on the back surface of the substrate, a step of remelting the brazing material on the exposed substrate surface, and the etching preventive layer And a step of pelletizing after removing the above. A method of manufacturing a mesa-type semiconductor device, comprising:
【0008】[0008]
【作用】本願第1の発明によれば、基板の両面の電極部
の形状が異なる構成となっているため、ペレット選別を
用意に行うことができ、作業性を向上できる。According to the first invention of the present application, since the shapes of the electrode portions on both surfaces of the substrate are different, pellet selection can be performed easily and workability can be improved.
【0009】本願第2の発明によれば、基板上に局部電
極を介して形成したろう材を段階的に溶融して基板裏面
側のろう材の形状と異ならせ、これにより第1電極部と
第2電極部の形状を異ならせるため、本願第1発明と同
様、ペレット選別を容易に行って作業性を向上できる。According to the second invention of the present application, the brazing material formed on the substrate via the local electrode is gradually melted to have a shape different from that of the brazing material on the back surface side of the substrate. Since the second electrode portion has a different shape, pellet selection can be easily performed and workability can be improved, as in the first invention of the present application.
【0010】[0010]
【実施例】以下、本発明の一実施例に係るメサ型半導体
素子を製造方法を併記しつつを図1及び図2を参照して
説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a mesa type semiconductor device according to an embodiment of the present invention will be described below with reference to FIGS. 1 and 2.
【0011】まず、例えばN型のシリコン基板1の表面
にn型不純物を拡散して高濃度領域(N+ 型領域)2を
形成した後、前記基板1の裏面にp型不純物を拡散して
高濃度領域(P+ 型領域)3を形成した。次に、前記基
板1の両面にメッキあるいは蒸着により電極材料を形成
した後、写真蝕刻法によりこれらの電極材料上にレジス
トパターン4を形成した。つづいて、このレジストパタ
ーン4をマスクとして前記電極材料を選択的にエッチン
グ除去し、基板1の表面,裏面に夫々局部電極5a,5bを
形成した(図1(A)図示)。First, for example, an n-type impurity is diffused on the surface of an N-type silicon substrate 1 to form a high concentration region (N + type region) 2, and then a p-type impurity is diffused on the back surface of the substrate 1. A high concentration region (P + type region) 3 was formed. Next, after electrode materials were formed on both surfaces of the substrate 1 by plating or vapor deposition, a resist pattern 4 was formed on these electrode materials by a photo-etching method. Subsequently, the electrode material was selectively removed by etching using the resist pattern 4 as a mask to form local electrodes 5a and 5b on the front surface and the back surface of the substrate 1 (shown in FIG. 1A).
【0012】次に、前記レジストパターン4を剥離した
後、前記基板1表面の局部電極5a上にろう材6aを、前記
基板1裏面の局部電極5b上にろう材6bを夫々例えば浸漬
法等により形成し(図1(B)図示)。なお、同図
(B)において、局部電極5a及びろう材6aを総称して第
1電極部7と呼び、局部電極5b及びろう材6bを総称して
第2電極部8と呼ぶ。つづいて、前記基板1の裏面側
に、局部電極5b,ろう材6bを覆うようなエッチング防止
層9を形成した。次いで、基板表面側の第1電極部7を
マスクとして前記基板1を等方的にエッチングした。但
し、このエッチングは、基板1裏面のP+ 型領域3に到
達する直前で停止させた。また、この際、露出する局部
電極5a及びろう材6aも若干エッチングされた(図1
(C)図示)。Next, after removing the resist pattern 4, the brazing material 6a is placed on the local electrode 5a on the front surface of the substrate 1 and the brazing material 6b is placed on the local electrode 5b on the back surface of the substrate 1 by, for example, a dipping method. Formed (shown in FIG. 1B). In FIG. 2B, the local electrode 5a and the brazing material 6a are collectively referred to as the first electrode portion 7, and the local electrode 5b and the brazing material 6b are collectively referred to as the second electrode portion 8. Subsequently, an etching prevention layer 9 was formed on the back surface of the substrate 1 so as to cover the local electrodes 5b and the brazing material 6b. Then, the substrate 1 was isotropically etched using the first electrode portion 7 on the front surface side of the substrate as a mask. However, this etching was stopped immediately before reaching the P + type region 3 on the back surface of the substrate 1. At this time, the exposed local electrode 5a and the brazing material 6a were also slightly etched (see FIG. 1).
(C) Illustration).
【0013】次に、前記エッチング防止層9を除去した
後、前記第1電極部7のろう材6aを再度溶融させ、その
下端面を下部の局部電極5aと同じ形状にした(図1
(D)図示)。その結果、基板表面の第1電極部7の形
状と基板裏面の第2電極部8の形状が異なった。この
後、前記基板1をエッチングしたラインに沿ってダイシ
ングし、図2(A),(B)に示すペレットを得た。但
し、同図(A)は同図(B)の平面図である。Next, after the etching prevention layer 9 is removed, the brazing material 6a of the first electrode portion 7 is melted again so that the lower end surface thereof has the same shape as the lower local electrode 5a (FIG. 1).
(D) Illustration). As a result, the shape of the first electrode portion 7 on the front surface of the substrate was different from the shape of the second electrode portion 8 on the back surface of the substrate. Then, the substrate 1 was diced along the etched line to obtain pellets shown in FIGS. 2 (A) and 2 (B). However, FIG. 7A is a plan view of FIG.
【0014】しかして、こうした本発明方法によれば、
図1(B)のように基板1の表裏にろう材の溶融により
第1電極部7,第2電極部8を夫々形成した後、基板裏
面をエッチング防止層9でマスクした状態で基板表面側
のみを等方的にエッチングし、更に前記第1電極部7の
ろう材6aを再度溶融させるため、最終的に図2に示すよ
うに第1電極部7を第2電極部8の形状よりも小さいペ
レットを得ることができた。したがって、第1電極部7
側と第2電極部側を目視により容易に見分けられため、
従来と比べてペレット選別を容易に行うことができる。
その結果、振動機等にかけることにより所望の極性を所
望の位置に配置でき、作業性を著しく向上できる。According to the method of the present invention, however,
As shown in FIG. 1B, after the first electrode portion 7 and the second electrode portion 8 are formed on the front and back surfaces of the substrate 1 by melting the brazing material, respectively, and then the substrate front surface side is masked with the etching prevention layer 9 Only the isotropic etching is performed, and the brazing material 6a of the first electrode portion 7 is melted again. Therefore, as shown in FIG. Small pellets could be obtained. Therefore, the first electrode portion 7
Side and the second electrode portion side can be easily distinguished visually,
Pellet selection can be performed more easily than before.
As a result, a desired polarity can be arranged at a desired position by applying it to a vibrator or the like, and workability can be significantly improved.
【0015】また、上記実施例に係るメサ型半導体素子
によれば、基板表裏の第1電極部7,第2電極部8の形
状が異なった構成となっているため、上述したようにペ
レットの選別が容易で、作業性の向上を図る事ができ
る。Further, in the mesa type semiconductor device according to the above-mentioned embodiment, since the shapes of the first electrode portion 7 and the second electrode portion 8 on the front and back surfaces of the substrate are different, as described above, It is easy to sort, and workability can be improved.
【0016】なお、本発明に係る半導体素子は、図2に
示したような構成のものに限らず、例えば図3(A),
(B)に示す如く平面形状が四角形のプレーナ型の半導
体素子、あるいは図4(A),(B)に示す如く平面形
状が六角形状の半導体素子、あるいは外部電極との接続
の為のろう材が浸漬されていないものでもよい。但し、
図3(B)は図3(A)の平面図、図4(B)は図4
(A)の平面図である。The semiconductor element according to the present invention is not limited to the one having the structure shown in FIG.
A planar semiconductor element having a quadrangular planar shape as shown in FIG. 4B, a semiconductor element having a hexagonal planar shape as shown in FIGS. 4A and 4B, or a brazing material for connection with an external electrode. May not be soaked. However,
3B is a plan view of FIG. 3A, and FIG. 4B is FIG.
It is a top view of (A).
【0017】[0017]
【発明の効果】以上詳述した如く本発明によれば、基板
の両面の第1電極部,第2電極部の形状を異ならせる事
により、ペレット選別を容易に行うことができ、作業性
を向上しうるメサ型半導体素子及びその製造方法を提供
できる。As described in detail above, according to the present invention, pellets can be easily selected by changing the shapes of the first electrode portion and the second electrode portion on both surfaces of the substrate, and the workability is improved. An improved mesa-type semiconductor device and a method for manufacturing the same can be provided.
【図1】本発明に係るメサ型半導体素子の製造方法を工
程順に示す断面図。FIG. 1 is a sectional view showing a method of manufacturing a mesa type semiconductor device according to the present invention in the order of steps.
【図2】本発明に係るメサ型半導体素子の説明図。FIG. 2 is an explanatory view of a mesa type semiconductor device according to the present invention.
【図3】本発明の他の実施例に係る半導体素子の説明
図。FIG. 3 is an explanatory diagram of a semiconductor device according to another embodiment of the present invention.
【図4】本発明の他の実施例に係る半導体素子の説明
図。FIG. 4 is an explanatory diagram of a semiconductor device according to another embodiment of the present invention.
1…N型のシリコン基板、2…N+ 型領域、3…P+ 型
領域、4…レジスト、5a,5b…分極電極、6a,6b…ろう
材、7…第1電極部、8…第2電極部、9…エッチング
防止層。1 ... N type silicon substrate, 2 ... N + type region, 3 ... P + type region, 4 ... Resist, 5a, 5b ... Polarizing electrode, 6a, 6b ... Brazing material, 7 ... First electrode portion, 8 ... 2 electrode parts, 9 ... Etching prevention layer.
Claims (2)
電型の高濃度領域を夫々形成した第1導電型の半導体基
板と、この半導体基板の両面に夫々形成された互いに形
状の異なる第1・第2電極部とを具備することを特徴と
するメサ型半導体素子。1. A first-conductivity-type semiconductor substrate having a first-conductivity-type high-concentration region and a second-conductivity-type high-concentration region formed on both sides, and a mutually-shaped semiconductor substrate formed on both sides of the semiconductor substrate. A mesa-type semiconductor device comprising different first and second electrode portions.
1導電型の高濃度領域,第2導電型の高濃度領域を形成
する工程と、前記基板の両面に夫々局部電極を選択的に
形成する工程と、これらの局部電極上にろう材を溶融,
形成し第1電極部,第2電極部を形成する工程と、前記
基板裏面側の局部電極及びろう材を覆うエッチング防止
層を形成する工程と、前記基板の等方性エッチングを基
板裏面側の高濃度領域の直前まで行う工程と、露出する
基板表面のろう材を再度溶融する工程と、前記エッチン
グ防止層を除去した後ペレット化する工程とを具備する
事を特徴とするメサ型半導体素子の製造方法。2. A step of forming a high-concentration region of a first conductivity type and a high-concentration region of a second conductivity type on both surfaces of a semiconductor substrate of the first conductivity type, and a local electrode selectively on both surfaces of the substrate. And the process of forming and melting the brazing material on these local electrodes,
Forming a first electrode portion and a second electrode portion, a step of forming an etching prevention layer covering the local electrode and the brazing material on the back surface side of the substrate, and isotropic etching of the substrate on the back surface side of the substrate. A mesa-type semiconductor device characterized by comprising: a step of performing until just before the high-concentration region, a step of remelting the exposed brazing material on the substrate surface, and a step of pelletizing after removing the etching prevention layer. Production method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP40768590A JPH0621431A (en) | 1990-12-27 | 1990-12-27 | Mesa-type semiconductor element and its manufacture |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP40768590A JPH0621431A (en) | 1990-12-27 | 1990-12-27 | Mesa-type semiconductor element and its manufacture |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0621431A true JPH0621431A (en) | 1994-01-28 |
Family
ID=18517241
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP40768590A Pending JPH0621431A (en) | 1990-12-27 | 1990-12-27 | Mesa-type semiconductor element and its manufacture |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0621431A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2005066388A2 (en) | 2004-01-05 | 2005-07-21 | Epg (Engineered Nanoproducts Germany) Gmbh | Metallic substrates comprising a deformable glass-type coating |
-
1990
- 1990-12-27 JP JP40768590A patent/JPH0621431A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2005066388A2 (en) | 2004-01-05 | 2005-07-21 | Epg (Engineered Nanoproducts Germany) Gmbh | Metallic substrates comprising a deformable glass-type coating |
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