JP2858866B2 - Method of manufacturing mesa-type semiconductor device - Google Patents
Method of manufacturing mesa-type semiconductor deviceInfo
- Publication number
- JP2858866B2 JP2858866B2 JP11045290A JP11045290A JP2858866B2 JP 2858866 B2 JP2858866 B2 JP 2858866B2 JP 11045290 A JP11045290 A JP 11045290A JP 11045290 A JP11045290 A JP 11045290A JP 2858866 B2 JP2858866 B2 JP 2858866B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- brazing material
- semiconductor device
- local
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Description
【発明の詳細な説明】 [産業上の利用分野] 本発明は、特にSR複合回路装置(STACK)に使用され
るメサ型半導体素子の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a mesa-type semiconductor device used especially for an SR composite circuit device (STACK).
[従来の技術と課題] 従来、メサ型半導体素子(ペレット)の製造は、例え
ばN型のウェハの両面に夫々ドナー,アクセプター不純
物を全面拡散し、その上にメッキあるいは蒸着にて局部
電極を形成し、その上に外部電極との接続のためにろう
材を浸漬法等により形成し、更にろう材を含めた電極を
マスクにしながらエッチングによりペレット化すること
により形成していた。[Prior art and problems] Conventionally, in the manufacture of a mesa-type semiconductor element (pellet), for example, donor and acceptor impurities are entirely diffused on both surfaces of an N-type wafer, and a local electrode is formed thereon by plating or vapor deposition. Then, a brazing material is formed thereon by an immersion method or the like for connection with an external electrode, and further formed by etching into a pellet using the electrode including the brazing material as a mask.
ところで、こうして得られたペレットの判別は、従来
目視あるいは電気的特性により行なわれているのが一般
的であるが、電気的特性による判別方法は量産的でない
ため、目視による判別が主流である。By the way, the determination of the pellet thus obtained is generally performed visually or by electrical characteristics, but the determination method based on the electrical characteristics is not mass-produced, so that the visual determination is the mainstream.
しかし、従来の半導体素子においては、基板表裏に形
成された局部電極の形状が同一であるため、その後のエ
ッチング工程において片面からの選択エッチング等の工
夫を用いても上から見ると同一形状になり、表裏の選別
が難しい。従って、複合回路半導体装置例えば整流ブリ
ッジ等を作る場合、回路通りペレットを並べるのに時間
がかかったり、不良が多発する場合があった。However, in the conventional semiconductor device, since the shape of the local electrodes formed on the front and back surfaces of the substrate is the same, the shape becomes the same when viewed from above even if a device such as selective etching from one side is used in a subsequent etching process. It is difficult to sort the front and back. Therefore, when a composite circuit semiconductor device such as a rectifier bridge is manufactured, it may take time to arrange the pellets according to the circuit or the defect may occur frequently.
本発明は上記事情に鑑みてなされたもので、基板の両
面の局部電極の形状又は大きさを互いに異ならせる事に
より、ペレット選別を容易に行うことができ、作業性を
向上しうるメサ型半導体素子及びその製造方法を提供す
ることを目的とする。The present invention has been made in view of the above circumstances, and by making the shapes or sizes of local electrodes on both surfaces of a substrate different from each other, a pellet sorting can be easily performed, and a mesa semiconductor that can improve workability. An object is to provide an element and a method for manufacturing the element.
[課題を解決するための手段と作用] 本発明は、第1導電型の半導体基板の両面に夫々第1
導電型の高濃度領域,第2導電型の高濃度領域を形成す
る工程と、前記基板の両面に夫々局部電極を選択的に形
成する工程と、これらの局部電極上にろう材を溶融,形
成する工程と、前記基板裏面側の局部電極及びろう材を
覆うエッチング防止層を形成する工程と、前記基板を片
面より等方性エッチングし裏面側の直前で止める工程
と、前記エッチング防止層を除去する工程と、両面より
等方性エッチングしてペレット化する工程と、露出する
ペレット表面のろう材を再度溶融して局部電極の形状又
は大きさを異ならせる工程とを具備する事を特徴とする
メサ型半導体素子の製造方法である。[Means and Actions for Solving the Problems] The present invention provides a semiconductor device of the first conductivity type on both surfaces thereof.
A step of forming a high-concentration region of the conductivity type and a high-concentration region of the second conductivity type; a step of selectively forming local electrodes on both surfaces of the substrate; and melting and forming a brazing material on these local electrodes Performing a step of forming an etching prevention layer covering the local electrode and the brazing material on the back side of the substrate; a step of isotropically etching the substrate from one side and stopping immediately before the back side; and removing the etching prevention layer. And a step of pelletizing by isotropically etching from both surfaces, and a step of melting the brazing material on the exposed pellet surface again to vary the shape or size of the local electrode. This is a method for manufacturing a mesa semiconductor device.
本発明によれば、基板の両面の電極の形状又は大きさ
を互いに異ならせる事により、ペレット選別を容易に行
うことができ、作業性を向上しうるメサ型半導体素子を
得ることができる。According to the present invention, by changing the shape or size of the electrodes on both surfaces of the substrate from each other, it is possible to easily perform pellet sorting and obtain a mesa-type semiconductor element capable of improving workability.
[実施例] 以下、本発明の一実施例に係るメサ型半導体素子を製
造方法を併記しつつを第1図及び第2図を参照して説明
する。Example A method of manufacturing a mesa-type semiconductor device according to an example of the present invention will be described below with reference to FIGS. 1 and 2.
まず、例えばN型のシリコン基板1の表面にn型不純
物を拡散して高濃度領域(N+型領域)2を形成した後、
前記基板1の裏面にp型不純物を拡散して高濃度領域
(P+型領域)3を形成した。次に、前記基板1の両面に
メッキあるいは蒸着により電極材料を形成した後、写真
蝕刻法によりこれらの電極材料上にレジストパターン4
を形成した。つづいて、このレジストパターン4をマス
クとして前記電極材料を選択的にエッチング除去し、基
板1の表面,裏面に夫々局部電極5a,5bを形成した(第
1図(A)図示)。First, a high-concentration region (N + -type region) 2 is formed by diffusing an n-type impurity on the surface of an N-type silicon substrate 1,
A high concentration region (P + type region) 3 was formed by diffusing a p-type impurity on the back surface of the substrate 1. Next, after electrode materials are formed on both surfaces of the substrate 1 by plating or vapor deposition, a resist pattern 4 is formed on these electrode materials by photolithography.
Was formed. Subsequently, using the resist pattern 4 as a mask, the electrode material was selectively etched away to form local electrodes 5a and 5b on the front and back surfaces of the substrate 1, respectively (see FIG. 1 (A)).
次に、前記レジストパターン4を剥離した後、前記基
板1表面の局部電極5a上にろう材6aを、前記基板1裏面
の局部電極5b上にろう材6bを夫々例えば浸漬法等により
形成し(第1図(B)図示)。つづいて、前記基板1の
裏面側に、局部電極5b,ろう材6bを覆うようなエッチン
グ防止層7を形成した。次いで、基板表面側のろう材6a
をマスクとして前記基板1を等方的にエッチングした
(第1図(B)図示)。但し、このエッチングは、基板
1裏面のP+型領域3に到達する直前で停止させた。Next, after the resist pattern 4 is peeled off, a brazing material 6a is formed on the local electrode 5a on the surface of the substrate 1 and a brazing material 6b is formed on the local electrode 5b on the back surface of the substrate 1 by, for example, an immersion method or the like ( FIG. 1 (B) is shown. Subsequently, an etching prevention layer 7 was formed on the back surface of the substrate 1 so as to cover the local electrode 5b and the brazing material 6b. Next, the brazing material 6a on the substrate surface side
Using the mask as a mask, the substrate 1 was isotropically etched (shown in FIG. 1 (B)). However, this etching was stopped immediately before reaching the P + type region 3 on the back surface of the substrate 1.
次に、前記エッチング防止層7を除去した後、基板1
の両面から等方的にエッチングを行い、ペレットに分離
した(第1図(C)及び第2図図示)。ここで、第2図
は第1図(C)の平面図である。Next, after removing the etching prevention layer 7, the substrate 1
Was isotropically etched from both sides to separate into pellets (FIG. 1 (C) and FIG. 2). Here, FIG. 2 is a plan view of FIG. 1 (C).
次に、個々に分離されたペレットの各電極部のろう材
6a,6bを再度溶融させ、各電極部のろう材6a,6bの形状を
局部電極5a,5bと同じ径にした(第1図(D)及び第3
図図示)。ここで、第3図は第1図(D)の平面図であ
る。Next, the brazing filler metal of each electrode part of the individually separated pellet
6a and 6b were melted again, and the shape of the brazing material 6a and 6b of each electrode portion was made the same diameter as that of the local electrodes 5a and 5b (FIG. 1 (D) and FIG.
Illustration). Here, FIG. 3 is a plan view of FIG. 1 (D).
しかして、こうした本発明方法によれば、第1図
(A)のように基板1の表裏にろう材の溶融により局部
電極5a,5bを夫々形成した後、基板裏面をエッチング防
止層7でマスクした状態で基板表面側のみを等方的にエ
ッチングし、次にエッチング防止層7を除去した状態で
基板の両面から等方的にエッチングし、更にろう材6a,6
bを再度溶融させるため、最終的に第1図(D)及び第
3図に示すようにうに基板表面側の局部電極5aを基板裏
面側の局部電極5bの形状よりも小さいペレットを得るこ
とができた。従って、ペレットの表裏を目視により容易
に見分けられため、従来と比べてペレット選別を容易に
行うことができる。その結果、振動機等にかけることに
より所望の極性を所望の位置に配置でき、作業性を著し
く向上できる。According to the method of the present invention, as shown in FIG. 1 (A), after the local electrodes 5a and 5b are respectively formed on the front and back of the substrate 1 by melting the brazing material, the back surface of the substrate is masked with the etching preventing layer 7. In this state, only the surface side of the substrate is isotropically etched, and then, with the etching prevention layer 7 removed, isotropically etching is performed from both sides of the substrate.
In order to re-melt b, finally, as shown in FIGS. 1 (D) and 3, a local electrode 5a on the substrate front side may be obtained as a pellet smaller than the shape of the local electrode 5b on the substrate rear side. did it. Therefore, since the front and back of the pellet can be easily distinguished visually, the pellet can be easily sorted as compared with the related art. As a result, the desired polarity can be arranged at a desired position by applying to a vibrator or the like, and workability can be significantly improved.
また、上記実施例に係るメサ型半導体素子によれば、
基板表面側の局部電極5a,基板裏面側の局部電極5bの形
状が異なった構成となっているため、上述したようにペ
レットの選別が容易で、作業性の向上を図る事ができ
る。Further, according to the mesa semiconductor device according to the above embodiment,
Since the local electrode 5a on the front surface side of the substrate and the local electrode 5b on the rear surface side of the substrate have different shapes, the selection of the pellets is easy as described above, and the workability can be improved.
なお、本発明に係る半導体素子は、第2図に示したよ
うな構成のものに限らず、例えば第4図(A),(B)
に示す如く平面形状が六角形状の半導体素子、あるいは
外部電極との接続の為のろう材が浸漬されていないもの
でもよい。第4図(B)は第4図(A)の平面図であ
る。The semiconductor device according to the present invention is not limited to the structure as shown in FIG. 2, but may be, for example, FIGS. 4 (A) and 4 (B).
The semiconductor element may have a hexagonal planar shape as shown in FIG. 3 or may not be immersed in a brazing material for connection to an external electrode. FIG. 4 (B) is a plan view of FIG. 4 (A).
[発明の効果] 以上詳述した如く本発明によれば、表裏の電極の形状
又は大きさを互いに異ならせる異により、ペレット選別
を容易に行うことができ、作業性を向上しうるメサ型半
導体素子及びその製造方法を提供できる。[Effects of the Invention] As described in detail above, according to the present invention, a mesa-type semiconductor that can easily perform pellet sorting and improve workability due to different shapes or sizes of front and rear electrodes. An element and a method for manufacturing the same can be provided.
第1図(A)〜(D)は本発明の一実施例に係るメサ型
半導体素子の製造方法を工程順に示す断面図、第2図は
第1図(C)の平面図、第3図は第1図(D)の平面
図、第4図は本発明の他の実施例に係る半導体素子の説
明図である。 1……N型のシリコン基板、2……N+型領域、3……P+
型領域、4……レジスト、4a,4b……分極電極、6a,6b…
…ろう材、7……エッチング防止層。1 (A) to 1 (D) are cross-sectional views showing a method of manufacturing a mesa semiconductor device according to an embodiment of the present invention in the order of steps, FIG. 2 is a plan view of FIG. 1 (C), and FIG. 1 is a plan view of FIG. 1 (D), and FIG. 4 is an explanatory view of a semiconductor device according to another embodiment of the present invention. 1 ... N-type silicon substrate, 2 ... N + type region, 3 ... P +
Mold region, 4 ... resist, 4a, 4b ... polarization electrode, 6a, 6b ...
... brazing material, 7 ... etching prevention layer.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 飯島 善幸 千葉県茂原市茂原647番地 東芝コンポ ーネンツ株式会社茂原工場内 (56)参考文献 特開 昭60−89981(JP,A) 特公 昭45−38650(JP,B1) 特公 昭46−14410(JP,B1) (58)調査した分野(Int.Cl.6,DB名) H01L 29/861 - 29/885──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Yoshiyuki Iijima 647 Mobara, Mobara City, Chiba Prefecture Inside the Mobara Plant of Toshiba Components Corporation (56) References 38650 (JP, B1) JP 46-14410 (JP, B1) (58) Fields investigated (Int. Cl. 6 , DB name) H01L 29/861-29/885
Claims (1)
導電型の高濃度領域,第2導電型の高濃度領域を形成す
る工程と、前記基板の両面に夫々局部電極を選択的に形
成する工程と、これらの局部電極上にろう材を溶融,形
成する工程と、前記基板裏面側の局部電極及びろう材を
覆うエッチング防止層を形成する工程と、前記基板を片
面より等方性エッチングし裏面側の直前で止める工程
と、前記エッチング防止層を除去する工程と、両面より
等方性エッチングしてペレット化する工程と、露出する
ペレット表面のろう材を再度溶融して局部電極の形状又
は大きさを異ならせる工程とを具備する事を特徴とする
メサ型半導体素子の製造方法。A first conductive type semiconductor substrate provided on both sides thereof;
A step of forming a high-concentration region of the conductivity type and a high-concentration region of the second conductivity type; a step of selectively forming local electrodes on both surfaces of the substrate; and melting and forming a brazing material on these local electrodes Performing a step of forming an etching prevention layer covering the local electrode and the brazing material on the back side of the substrate; a step of isotropically etching the substrate from one side and stopping immediately before the back side; and removing the etching prevention layer. And a step of pelletizing by isotropically etching from both surfaces, and a step of melting the brazing material on the exposed pellet surface again to vary the shape or size of the local electrode. A method for manufacturing a mesa semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11045290A JP2858866B2 (en) | 1990-04-27 | 1990-04-27 | Method of manufacturing mesa-type semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11045290A JP2858866B2 (en) | 1990-04-27 | 1990-04-27 | Method of manufacturing mesa-type semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0410575A JPH0410575A (en) | 1992-01-14 |
JP2858866B2 true JP2858866B2 (en) | 1999-02-17 |
Family
ID=14536076
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11045290A Expired - Fee Related JP2858866B2 (en) | 1990-04-27 | 1990-04-27 | Method of manufacturing mesa-type semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2858866B2 (en) |
-
1990
- 1990-04-27 JP JP11045290A patent/JP2858866B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH0410575A (en) | 1992-01-14 |
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