JPH0620989A - Contact hole formation - Google Patents

Abstract

PURPOSE:To form a reliable contact hole which has a low contact resistance. CONSTITUTION:After forming an interlayer insulating film BPSG 13, a poly-Si film 14 is formed and a contact hole 16 is formed by using a resist 15. A CVD- silicon oxide film is formed on the whole surface and is left in the contact hole 16 as the side wall 17 by etching back. Poly-Si is deposited so as to fill the contact hole and is left only in the contact hole 16 as a poly-Si plug 18 by etching back. Lastly, ion implantation and heat treatment are performed so that the poly-Si plug 18 may have the p-type conductivity when the contact hole is a p-type diffused layer and have the n-type conductivity when the contact hole is an n-type diffused layer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming contact holes used in semiconductor integrated circuits.

[0002]

2. Description of the Related Art As semiconductor elements are miniaturized, the coverage of wiring metal in contact holes connecting the impurity diffusion layer of the semiconductor element and the wiring layer becomes a problem. Since the wiring metal has been conventionally formed by the sputtering method, it has a problem that its coverage is particularly poor and its reliability is lowered. In order to fill the contact hole, for example, a poly-Si plug method has been developed in which polycrystalline silicon (hereinafter referred to as poly-Si) is deposited to fill the contact. The outline of this forming process is shown in FIG.
A description will be given using (a) to (c).

FIG. 2 (a) shows a contact hole 5 in an impurity diffusion layer 2 formed on the surface of a Si substrate 1, a boron silicon which is an insulating film between wiring layers, and a BPSG3 which is a CVD silicon oxide film containing phosphorus. To form. The contact hole 5 is opened by using the resist 4 as a mask by normal dry etching. Then, as shown in FIG. 2B, poly-Si 6 is deposited on the entire surface to fill the contact hole 5. After this, etch back poly-Si,
As shown in FIG. 2C, the poly- is formed in the contact hole 5.
Leave the Si plug 7. Then, according to the conductivity type of the impurity diffusion layer 2, impurities are ion-implanted into the poly-Si plug 7 using the resist as a mask. For example, the impurity layer is BF ₂ ⁺ if p-type, implanting As ⁺ if n-type.
After this, heat treatment is performed to activate the impurities and form the upper wiring.

[0004]

However, in the contact hole 5 constructed as described above, p
There is a problem that the contact resistance to the type diffusion layer is high. This is because phosphorus is added to the poly-Si plug 7 from the BPSG 3 used as the interlayer insulating film when impurities are injected into the poly-Si plug 7 and heat treatment for activation is performed.
Spread inside. Therefore, the carriers in the poly-Si plug 7 are reduced and the resistance is increased.

The present invention provides a poly with low contact resistance.
An object of the present invention is to provide a method for forming a contact hole using a Si plug.

[0006]

In order to achieve the above object, a method of forming a contact hole according to the present invention comprises forming an interlayer insulating film on a substrate on which a semiconductor element is formed, and forming a first interlayer insulating film on the interlayer insulating film. Depositing a polycrystalline silicon film of 1;
A step of forming a contact hole in the interlayer insulating film and the first polycrystalline silicon film; a step of forming a CVD-oxide film on the entire surface; and a step of forming the CVD in the contact hole.
A step of leaving as a sidewall of an oxide film, a step of embedding a second polycrystalline silicon in the contact hole, and a second polycrystalline silicon having the same conductivity type as that of the semiconductor substrate immediately below the contact hole. And the step of giving.

[0007]

According to the present invention, after the contact hole is opened, the CVD
-By leaving the oxide film as a sidewall in the contact hole, the diffusion of the interlayer insulating film phosphorus in the poly-Si plug is prevented and the contact resistance is prevented from increasing. In addition, the CVD-
When the oxide film is etched back, a poly-Si film is formed between the CVD-oxide film and the interlayer insulating film to prevent the Si etch rate in the contact from increasing.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a process sectional view of an embodiment of a method for forming a contact hole according to the present invention. The present invention will be described below with reference to this drawing. First, the steps for forming a semiconductor element on the Si substrate 11 and forming the BPSG 13 as an interlayer insulating film are the same as those for forming a normal semiconductor integrated circuit. Next, the poly-Si film 14 is deposited on the BPSG 13. The poly-Si film 14 has a role of preventing an increase in the etching rate of Si in the etching stopper and the contact hole when the sidewall is formed. A suitable film thickness is 10 to 100 nm. Next target S
A resist 15 having a pattern of contact holes to the impurity diffusion layer 12 on the i substrate 11 is formed.

Next, as shown in FIG. 1A, the resist 15
Using the as a mask, the contact hole 16 is opened by dry etching. For example, the poly-Si film 14
Is etched with SF ₆ , and BPSG 13 is etched with C
A mixed gas of HF ₃ + O ₂ is used.

After that, the resist 15 is removed, and the reduced pressure CV is applied.
A CVD-oxide film is deposited on the entire surface by the D method. The appropriate film thickness is 50 to 300 nm. Then, for example,
Anisotropic dry etching is performed using a mixed gas of CHF ₃ + O _{2 so} that only the inside of the contact hole 16 is exposed.
The sidewall 17 is left as shown in FIG. If the poly-Si film 14 is not formed during this etching, the contact hole 16 near the end point of the etching.
When the Si substrate 11 is exposed inside, there arises a problem that the etching rate of Si increases. Since most of the etched portion is of a silicon oxide film type such as BPSG 13, oxygen is supplied from the oxide film during etching, and the partial pressure of oxygen is increased. However, in the present invention, since the poly-Si film 14 is formed, oxygen is not supplied from the oxide film during etching, and the oxygen partial pressure does not increase. Therefore, such a problem does not occur.

Further, the etching is performed on the poly-Si film 1
Since it stops at 4, the film thickness of the interlayer insulating film BPSG13 does not decrease.

After that, before depositing the poly-Si film filling the contact hole 16, the contact hole 1 is formed.
The natural oxide film generated in 6 is removed using buffer hydrofluoric acid or the like. After this, a poly-Si film is deposited. At this time, it is appropriate that the deposited film thickness of the poly-Si film is about 0.6 to 1 times the size on the short side of the opened contact hole 16.

Next, as shown in FIG. 1C, dry etching is performed using, for example, a mixed gas of SF ₆ + CF ₄ to etch back the poly-Si film to form poly-Si in the contact hole 16. Leave the plug 18. Finally, if the impurity diffusion layer 12 is p-type, poly-Si
The plug 18 is given a p-type conductivity type and an n-type conductivity type if it is n-type.

For example, from the state shown in FIG. 1C, a resist pattern is formed in which only the contact hole 16 corresponding to the p-type impurity diffusion layer is opened, and BF ₂ ⁺ is 3 × 10 ^16.
cm ^-2 inject. After removing the resist, a resist pattern in which only the contact hole 16 corresponding to the n-type impurity diffusion layer is opened is formed, and P ⁺ is implanted at 2 × 10 ¹⁶ cm ^-2 . After that, the resist is removed and 900
Heat treatment is performed at 30 ° C. for 30 minutes to activate the impurities. At this time, P or the like from the BPSG 13 which is the interlayer insulating film is polled.
Even if an attempt is made to diffuse into the y-Si plug 18, it is prevented because of the sidewall 17. As described above, the formation of the contact hole according to the present invention is completed, and thereafter, by forming the wiring layer by the usual method, a contact having low resistance and high reliability can be formed.

In this embodiment, the CVD-oxide film is used as the side wall, but a CVD-nitride film can be used to form the same. In this case, since the nitride film has a higher ability to suppress diffusion of P and the like from BPSG than the silicon oxide film, it has an effect of making the sidewall thin. Although the interlayer insulating film is BPSG, the same can be applied to PSG not containing B.

[0016]

As described above, according to the present invention, the contact resistance is low and the contact is completely embedded.
A highly reliable contact can be formed and its practical effect is great.

[Brief description of drawings]

FIG. 1 is a process sectional view of an embodiment of the present invention.

FIG. 2 is a process sectional view of a conventional technique.

[Explanation of symbols]

 11 Si Substrate 12 Impurity Diffusion Layer 13 BPSG 14 Poly-Si Film 15 Resist 16 Contact Hole 17 Sidewall 18 Poly-Si Plug

Claims (1)

[Claims] 1. A step of forming an interlayer insulating film on a substrate on which a semiconductor element is formed and depositing a first polycrystalline silicon film on the interlayer insulating film, the interlayer insulating film and the first polycrystalline silicon film. A step of forming a contact hole in the crystalline silicon film, a step of forming a CVD-oxide film on the entire surface, a step of leaving the CVD-oxide film as a sidewall of the CVD-oxide film in the contact hole, and a second step in the contact hole. A method of forming a contact hole, comprising: a step of burying polycrystalline silicon; and a step of providing the second polycrystalline silicon with the same conductivity type as that of the semiconductor substrate immediately below the contact hole.