JPH06208540A - Dma bus master module device and control method - Google Patents

Abstract

PURPOSE:To obtain the bus right of the internal bus of a MDA bus master module preferentially by a system which employing a DMA controller 11 not to be capable of forcibly interrupting temporarily started bus transfer from outside. CONSTITUTION:When a mask circuit 20 is actuated by turning ON a mask actuating circuit 12, the releasing of the internal bus 15 is detected by monitoring the invalidation of a signal HOLDREQ. The detection result is outputted as a state signal to a sense circuit 13. Further, the mask circuit 20 inhibits a signal HOLDBACK from being supplied to the DMA controller 11 immediately after the internal bus 15 is released. Therefore, a main processor 3 can executes an input/output instruction preferentially to the DMA controller 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA bus master module device and a control method suitable for a bus master busy control for coordinating the use of an internal bus of a bus master module that occupies a system bus and executes burst transfer.

[0002]

2. Description of the Related Art Direct memory access control is widely used in information processing apparatuses for automating data transfer of memories, input / output devices and the like. In Figure 2,
A block diagram of the main part of such a general information processing apparatus is shown. This device has a system bus 1 and a main memory 2
, The main processor 3 and the DMA bus master module 4 are connected. A DMA controller is incorporated in the DMA bus master module 4. An input / output device 5 is also connected to the system bus 1.

In such an apparatus, the main processor 3
The DMA bus master module 4 receives the input / output instruction of the above, and processes data transfer between the input / output device 5 and the main memory 2. In order to collectively execute a certain amount of such data transfer, a means called burst transfer is adopted. When performing such burst transfer, when the DMA bus master module 4 acquires the bus right of the system bus 1, a considerable amount of data transfer processing is continuously executed at once.

However, if such a burst transfer is executed unconditionally, the system bus 1 keeps on for a long time during that period.
It is occupied by the DMA bus master module 4. As a result, other modules connected to the system bus 1, for example, the main processor 3 cannot acquire the bus right of the system bus 1 during that time. For example, system bus 1
On the other hand, if the RS232C port is connected, an overrun error of that port may occur. As a method to prevent such problems from occurring,
In addition to the method of limiting the line speed and the number of lines of the RS232C port, there is a method of not continuously giving the bus right to the DMA bus master module 4.

FIG. 3 is an explanatory diagram showing the relationship between the burst transfer in which the bus right is restricted and the system bus right.
As shown in FIG. 3A, for example, the DMA bus master module 4 shown in FIG. 2 executes burst transfer from time T1 to time T4.

However, the DMA bus master module 4
During this period, as shown in FIG. 3 (b), the bus right is relinquished and the system bus 1 is released for each data transfer. If such a method is adopted, the DMA bus master module 4 is operated, for example, between time T2 and time T3 shown in FIG.
Releases the bus right, so that another module can obtain the bus right of the system bus 1.

[0007]

By the way, since the bus right of the system bus is periodically abandoned before the burst transfer is completed while the DMA bus master module 4 is executing the burst transfer as described above, the burst transfer is executed. During this, another module may issue another input / output command to the DMA bus master module 4. Even in such a case, the DMA bus master module 4 has a function of interrupting the burst transfer currently being executed, accepting a new input / output instruction, and restarting the interrupted burst transfer after executing the input / output instruction. There is. In such a DMA bus master module, forced interruption can be performed by masking the HOLD ACK signal generated when the DMA controller occupies the internal bus of the module.

However, there is also a DMA bus master module having a structure in which burst transfer cannot be forcibly interrupted. In such a module, the bus master busy control as described above cannot be performed. The present invention has been made paying attention to the above points. In a system employing a DMA bus master module in which burst transfer once started cannot be forcibly interrupted externally by masking the HOLD ACK signal, other modules are , DMA
An object of the present invention is to provide a DMA bus master module device and a control method capable of preferentially acquiring the bus right of the system bus when the internal bus of the bus master module is released.

[0009]

According to a first aspect of the present invention, a bus right is released at a predetermined timing while a system bus is occupied and burst transfer is being executed, so that another system can occupy the system bus. Before the direct memory access controller detects the release of the internal bus by the direct memory access controller and the direct memory access controller acquires the bus right of the internal bus again, A mask circuit for masking so as to cut off the supply path of the bus right permission signal of the bus, and a sense circuit for holding a status signal for notifying the other module whether or not the mask processing by the mask circuit is completed The present invention relates to a DMA bus master module device characterized by the above.

According to a second aspect of the present invention, a direct memory access, which occupies the system bus and releases the bus right at a predetermined timing during execution of burst transfer, enables another module to occupy the system bus. A bus grant signal for an internal bus before the direct memory access controller detects the release of the internal bus by the controller and the direct memory access controller, and the direct memory access controller acquires the bus right of the internal bus again. A mask circuit for performing mask processing so as to cut off the supply path of the power supply circuit, and a sense circuit for holding a status signal for notifying the other module of the end of the mask processing by the mask circuit, and the other module is provided in advance. After clearing the interrupt of another module to its own module, the bus right of the system bus is removed. When the activation of the mask circuit is requested at the released timing, the sense circuit is read, and a notice of the end of the mask processing is recognized, an input / output instruction is issued to the direct memory access controller. And a DMA bus master module control method.

According to a third aspect of the present invention, in the above method, when another module reads the sense circuit and recognizes a notification that the mask processing has not been completed, the other module recognizes another module from another module. It is characterized by canceling the interrupt elimination measures of.

According to a fourth aspect of the present invention, a direct memory access, which occupies the system bus and releases the bus right at a predetermined timing during a burst transfer, enables another module to occupy the system bus. When an I / O command is issued from another module with the controller and the timing that the bus right of the system bus is released,
While the burst transfer is being executed, the input / output instruction is invalid,
The present invention relates to a DMA bus master module device having a result display circuit for validating the input / output command after the burst transfer and displaying the result.

According to a fifth aspect of the present invention, a direct memory access control system that releases the bus right at a predetermined timing while occupying the system bus and executing a burst transfer so that another system can occupy the system bus. When an I / O command is issued from another module with the controller and the timing that the bus right of the system bus is released,
While the burst transfer is being executed, the input / output instruction is invalid,
After the burst transfer is completed, a result display circuit for validating the input / output instruction and displaying the result is provided, and the other module is configured to perform the read cycle after the input / output instruction is issued to the direct memory access controller. The present invention relates to a DMA bus master module control method characterized by reading a result display circuit.

According to a sixth aspect of the present invention, a direct memory access program is provided which releases the bus right at a predetermined timing while occupying the system bus and executing a burst transfer so that the system bus can be occupied by another module. When an I / O command is issued from another module with the controller and the timing that the bus right of the system bus is released,
While the burst transfer is being executed, the input / output instruction is invalid,
After the burst transfer is completed, a result display circuit is provided for validating the input / output command and displaying the result, and the other module is configured to display the result display circuit in the DMA data output from the direct memory access controller. The present invention relates to a method for controlling a DMA bus master module, which is characterized in that the output including the data is read.

[0015]

When the mask activation circuit is turned on to activate the mask circuit, the device of the first aspect monitors the invalidation of the HOLD REQ signal and detects the release of the internal bus. The detection result is output to the sense circuit as a status signal. Also, when the burst transfer is completed, the mask circuit immediately releases the HOLD ACK.
Prevents signals from being provided to the DMA controller.
Therefore, other modules, such as the main processor,
After detecting the release of the internal bus through the sense circuit, the I / O command can be preferentially executed to the DMA controller.

In the method of the second aspect of the invention, the main processor preliminarily excludes an interrupt of another module with respect to its own module, then activates the mask circuit and waits for the end of the mask processing. Therefore, after the activation of the mask circuit, another module interrupts the main processor, so that the DMA controller is not kept waiting for a long time while being masked.

According to the third aspect of the present invention, when the main processor eliminates the interrupt of another module as described above before activating the mask circuit and reads the sense circuit, and judges that the mask processing is not yet finished, Immediately release the interrupt disabling measure of another module. As a result, it is possible to prevent a situation in which an interrupt to the main processor by another module cannot be accepted at all before the main processor issues an input / output instruction to the DMA controller.

According to the fourth aspect of the invention, when another module issues an input / output instruction to the DMA controller, the input / output instruction is invalidated during the burst transfer and the input / output instruction is validated after the burst transfer is completed. The result is read by another module via the result display circuit. As a result, the end of burst transfer of the DMA controller can be recognized with a small number of dynamic steps.

In the fifth invention, the burst transfer end recognition shown in the fourth invention is executed in the read cycle after the I / O instruction is issued, and the dynamic step can be minimized. In the sixth aspect, when the DMA controller outputs the DMA data, the DMA data includes the information indicating the end of the burst transfer, so that it is not necessary to perform a special process for reading the result display circuit.

[0020]

The present invention will be described in detail below with reference to the embodiments shown in the drawings. FIG. 1 is a block diagram showing an embodiment of a DMA bus master module device of the first invention. In this device, a main memory 2, a main processor 3, and a DMA bus master module 10 are connected to a system bus 1. The DMA bus master module 10 has D
An MA controller 11 is provided. Further, the system bus 1 includes a mask activation circuit 12 and a sense circuit 13.
And the bidirectional buffer 14 are connected. The DMA controller 11 is connected to the bidirectional buffer 14 via an internal bus 15 and is configured to mutually transfer data.

A mask circuit 20 is connected to the mask starting circuit 12. The mask starting circuit 12 is composed of a register for storing a 1-bit signal for starting the mask circuit 20. The mask circuit 20 includes an AND gate 21, a flip-flop 22, and an OR gate 23.
And a flip-flop 24, which are connected in sequence. The output of the flip-flop 24 is input to one terminal of the AND gate 21, and the AND gate 21 is opened / closed by the output of the mask starting circuit 12.

The output of the flip-flop 22 is connected to the sense circuit 13. The output of the flip-flop 22 is used as a status signal, and the mask circuit 2
When 0 ends the mask processing, it is a high-level signal, and in other cases, it is a low-level 1-bit signal. Sense circuit 13
Is composed of a register for storing such a signal. The HOLD REQ signal of the DMA controller is input to the OR gate 23 of the mask circuit 20 via the flip-flop 16. The output of the flip-flop 22 is input to the OR gate 23, and the logical sum of the two is input to the flip-flop 24 and the HOLD A of the DMA controller 11.
It is configured to be sent to the CK signal input terminal. In this embodiment, the HOLD REQ of the DMA controller 11 is
Both the signal and the HOLD ACK signal are low active signals that are valid at a low level.

When the circuit as described above occupies the system bus 1, the DMA controller 11 executes a predetermined burst transfer. During execution of the burst transfer, an operation of releasing the bus right of the system bus 1 is performed every data transfer. The circuit for controlling this operation is the same as the conventional one, and is not shown. Also, this DMA controller 11 holds HOLD during the execution of burst transfer.
Even if the ACK signal is invalid, the operation cannot be interrupted. The present invention is effectively utilized for such a DMA controller 11.

The mask circuit 20 is the mask activation circuit 1
When another module for 2, for example, the main processor 3 shown in this figure sets a signal for starting the mask circuit 20, the mask processing is started. In this case, when the HOLD REQ signal output from the DMA controller 11 is valid, the mask circuit 20 inputs this signal to the HOLD ACK signal input terminal of the DMA controller 11 through the OR gate 23. At this time, a low-level signal is input to the flip-flop 24 and the AND gate 21 does not pass the output of the mask activation circuit 12, so that the flip-flop 2
2 holds a low level signal. Therefore, the state signal becomes low level, and the sense circuit 13 holds the low level signal. The output of the OR gate 23 is also held at the low level. Thus, when the HOLD REQ signal is valid, the interrupt of the main processor 3 is not acknowledged.

On the other hand, when the DMA controller 11 terminates the burst transfer and invalidates the HOLD REQ signal, the output of the OR gate 23 of the mask circuit 20 becomes high level, and the high level signal is stored in the flip-flop 24.
In addition, the HOLD ACK signal is low active, so it becomes invalid at this stage. On the other hand, the signal stored in the flip-flop 24 is supplied to the AND gate 21, and the high-level signal stored in the mask activation circuit 12 is supplied to the flip-flop 22. As a result, the output of the flip-flop 22 becomes high level, and this becomes a status signal and is stored in the sense circuit 13. In this state, the main processor 3 can issue an input / output command to the DMA controller 11.

In this state, the flip-flop 22
A high level signal is stored in the OR gate 23.
Is supplied to the flip-flop 24 through
After that, even if the HOLD REQ signal becomes valid and a low level signal is supplied to the OR gate 23 through the flip-flop 16, the HOLD ACK signal does not become low level, that is, valid only by that. As a result, the next burst transfer operation by the DMA controller 11 is masked by the mask circuit 20. The main processor 3 thus detects that the storage signal of the sense circuit 13 has become high level, and can issue an input / output command to the DMA controller 11.

FIG. 4 shows an operation flowchart of the second invention. In the device of the first invention, the mask activation circuit 12 is turned on to enable the operation of the mask circuit 20, and then the status signal stored in the sense circuit 13 is monitored, and after the status signal becomes high level, The input / output instruction for the DMA controller 11 is executed.

However, when such an operation is performed, the burst transfer is once terminated, and when the mask circuit 20 finishes the mask processing, the DMA controller 11 then causes the next D
The MA transfer cannot be executed. For example, if another module interrupts the main processor 3 during this period and the main processor 3 executes the interrupt processing first, the DMA controller 1
No. 1 is kept waiting for operation. This hinders DMA transfer by another module using the DMA controller 11 and may cause overrun or underrun.

Therefore, in practice, before the main processor 3 turns on the mask activation circuit 12, it is preferable to take measures to eliminate an interrupt by another module. The second invention is made for such a purpose, and its processing will be described in order with reference to the flowchart of FIG. That is, in step S1, the main processor 3 takes an interrupt elimination measure by another module. This is performed by the interrupt control of the processor itself, which is well known in the art.

Thereafter, in step S2, the main processor 3 inputs a high level signal to the mask starting circuit 12 to turn it on. After that, the mask circuit 20 operates in the manner described above, and the main processor 3 reads the state signal of the sense circuit 13 (step S3). Then, in step S4, it is determined whether or not the mask processing is completed. If it is not completed, the sense circuit 13 is restarted.
Repeat reading the status signal of.

After that, when the masking process is completed, the process goes to step S5 to execute the input / output command to the DMA controller 11. Then, when the processing of the necessary input / output instruction is completed, in step S6, the interrupt elimination measure executed first is canceled.

FIG. 5 shows an operation timing chart of the second invention. The second invention described above is specifically executed at such a timing. (A) of the figure shows the state of the mask activation circuit, in which the low level is off and the high level is on. (B) shows the state signal of the sense circuit, the low level indicates the masking process, and the high level indicates the masking completion state. (C) is the HOLD REQ signal, (d)
Indicates a HOLD ACK signal, in which high level is invalid and low level is valid. Further, (e) shows the operation of the DMA controller, and (f) shows the timing of reading the state information by the main processor 3.

First, at time T1, when the HOLD REQ signal becomes valid, the HOLD ACK signal becomes valid subsequently to this. Here, at time T2, the mask activation circuit 12 is turned on by the main processor 3, and then at time T3, T4,
At the timing of T6, the state information of the sense circuit 13 is read by the main processor 3. FIG. 5 (c)
At time T5, when the burst transfer of the DMA controller 11 is completed and the HOLD REQ signal becomes invalid at time T5, the HOLD ACK signal also becomes invalid. On the other hand, by this, the state information of the sense circuit 13 becomes high level, and the end of the mask processing is notified to the main processor. When the main processor 3 reads the status information as shown in (f) at time T6, the end of this masking process is recognized by the main processor 3, and the main processor 3 thereafter executes an input / output instruction at time T8.

As described above, for example, the time T
Mask circuit 2 even if the HOLD REQ signal becomes valid in 7
0 operates and masks this signal, so that the HOLD ACK signal is held invalid until time T9. When the mask activation circuit 12 is turned off, the output of the AND gate 21 becomes low level regardless of whether the output of the flip-flop 24 is high level, so that the low-level signal is stored in the flip-flop 22. . Therefore, if the HOLD REQ signal goes low after that, OR gate 2
The output of 3 becomes low level, and the HOLD ACK signal becomes valid. Further, the state signal output from the flip-flop 22 becomes low level, and this is stored in the sense circuit 13.

FIG. 6 shows an operation flowchart of the third invention. In the above-described second invention, when the mask activation circuit 12 is turned on, the main processor 3 monitors the state signal of the sense circuit 13 and waits for the end of burst transfer to execute the input / output instruction. However, if the time from the turning on of the mask activation circuit 12 to the end of the burst transfer is long, the main processor 3 prohibits the interrupt by another module during that time, and prevents the operation of another module.

In order to improve this point, the third invention is arranged such that after reading the status signal of the sense circuit 13, the process for activating the mask is once terminated and the measure for eliminating the interrupt is released. That is, as shown in steps S1 and S2 in FIG. 6, the main processor 3 first executes the interrupt elimination measure and then turns on the mask starting circuit 12. Then, when the state information of the sense circuit 13 is read (step S3), it is determined in step S4 whether or not the mask processing is completed. If the mask processing is not completed, the process proceeds to step S5, and the mask starting circuit 1
Turn off 2. After that, in step S6, the interrupt exclusion measure is released, and the interrupt from another module is accepted.

On the other hand, after an appropriate time has passed, the process returns to step S1 again, and a series of processes from the interrupt elimination measure to the mask activation circuit on is repeated. Then, when it is detected in step S4 that the masking process is completed, the same operation as the second invention is executed, in which an input / output command to the DMA controller is executed in step S7 and the interrupt elimination measure is canceled in step S8. Run. This eliminates the possibility that the main processor 3 will continue the interrupt prohibition measure for a long time.

FIG. 7 shows a timing chart of the third invention. According to the third invention, the device operates at the timing as shown in this figure. The description of the signals (a) to (f) in the figure is the same as that shown in FIG. As shown in this figure, the HOLD REQ signal becomes valid at time T1, and the HOLD
When the ACK signal becomes valid, as shown in (e), DMA
Burst transfer is executed. Here, when the mask activation circuit is turned on at time T2, the state information is read by the main processor 3 at time T3.

Here, in the third invention, when the end of the mask processing is not detected, the mask starting circuit is turned off at time T4. After that, when the HOLD REQ signal becomes invalid at time T5, the HOLD ACK signal also becomes invalid subsequently. Then, after that, the mask activation circuit is turned on again at time T6, and when the status information is read at time T7, the main processor 3 recognizes that the mask processing of the mask circuit is completed.
Then, as shown in (e), the input / output instruction of the DMA controller is executed at time T8. The operation in which the HOLD ACK signal is held in the invalid state until time T9 is the same as that described with reference to FIG.

FIG. 8 shows a block diagram of the device of the fourth invention. The device of the fourth invention is different from the device of the first invention in that HOLD
The end of burst transfer is detected by an input / output instruction without masking the ACK signal. The device in this figure
Similar to the device shown in FIG. 1, the system bus 1 is connected to a main memory 2, a main processor 3, and a DMA bus master module 30.

The DMA bus master module 30 has a DM
An A controller 11 is provided. Further, the DMA bus master module 30 is provided with an I / O decoder 31 that receives the address bus of the system bus 1. The I / O decoder 31 receives the chip select signal input through the address bus from the result display circuit 32 and DM.
This is a circuit for supplying the A controller 11.

In the result display circuit 32, an input / output instruction by a module such as the main processor 3 in the second invention is D.
A circuit for displaying invalid when issued during burst transfer operation by the MA controller 11 and valid when issued after burst transfer is completed. For example, a register for storing a 1-bit signal. Composed of. In this example, the result display circuit 32
When the content of the signal is high level, the input / output instruction is valid, and when it is low level, it is invalid. In addition, the HOLD REQ signal and HOLD ACK of the DMA controller 11
In this example, the signal is valid when it is at a high level.

OR gate 41 and AND gates 42 and 43
The flip-flops 52, 53, 54 and the AND gate 45 constitute a control circuit for supplying a chip select signal from the I / O decoder 31 to the DMA controller 11. AND gate 45 is flip-flop 54
When the output of is the high level, the chip select signal input from the I / O decoder 31 is sent to the DMA controller 11
It is configured to be supplied to and to start the operation. The flip-flop 55, the AND gate 44, and the flip-flops 56 and 57 constitute a circuit for holding the HOLD REQ signal output from the DMA controller 11, generating a HOLD ACK signal and supplying the HOLD ACK signal to the DMA controller. There is.

The OR gate 41 is the I / O decoder 3
It is provided in order to lead the chip select signal of the result display circuit 32 output by 1 to the result display circuit 32. Furthermore,
The flip-flop 51 is provided to hold the reset signal of the result display circuit 32. In addition, the control signal of the system bus 1 is input to the AND gate 42, and the chip select signal output from the I / O decoder 31 is input to the result display circuit 32 depending on whether the system bus 1 is a read cycle or a write cycle. I'm trying to control. That is, in this example, in the case of a read cycle, a high level signal is input to the AND gate 42 from the system bus 1, and the chip select signal of the I / O decoder 31 is supplied to the result display circuit 32 through the OR gate 41. It is configured to.

Further, the AND gate 43 provided on the output side of the flip-flop 52 and the AND gate 44 provided on the output side of the flip-flop 55 are in the case where one of the output signals is high level. , The chip select signal is not supplied from the flip-flop 52 to the flip-flop 53 when the HOLD REQ signal is valid at the high level. When is valid, the HOLD REQ signal is blocked by the AND gate 44 and controlled so that it is not supplied from the flip-flop 55 to the flip-flop 56. As a result, the control of the DMA controller 11 by the main processor 3 is suppressed during the burst transfer in which the HOLD REQ signal is valid, and the HOLD REQ signal is masked once the control of the DMA controller 11 by the main processor 3 is started.

Bidirectional buffers 33, 34 and 35 are inserted between the DMA controller 11 and the system bus 1. The bidirectional buffer 35 is for connecting the internal bus of the DMA bus master module 30 and the data bus of the system bus 1. In this example, the data bus has a 16-bit configuration. Also, in this example, D
The internal bus of the MA bus master module 30 has 8 bits.

The bidirectional buffer 33 is a buffer for holding input / output instructions transferred on the internal bus, and the bidirectional buffer 34 is a buffer for holding DMA data transferred on the internal bus. Bidirectional buffer 33
Are connected so as to hold an input / output command when the signal output from the flip-flop 54 is at a high level. Further, the bidirectional buffer 35 is configured to receive a 1-bit output signal from the result display circuit 32 in order to include the output of the result display circuit 32 in the DMA data as described later.

The device of the fourth invention having the above-mentioned configuration operates as follows. FIG. 9 shows an operation timing chart of the device of the fourth invention. In the figure, (a) shows the operation timing of the main processor, (b) shows the DMA access operation timing of the main memory, and (c) shows the HOLD REQ signal of the DMA controller. As described above, this signal is a signal in which the low level is invalid and the high level is valid. Also,
(D) shows the HOLD ACK signal of the DMA controller, and the low level is invalid and the high level is valid in the same manner. Further, (e) shows the chip select output of the I / O decoder, which is valid at the high level and invalid at the low level. (F) shows the chip select signal input to the result display circuit. Similarly, the high level is valid, and the low level is invalid. (G) shows the chip select input signal of the DMA controller, and the low level is invalid and the high level is valid. (H) shows the output signal of the result display circuit 32, which indicates that the input / output instruction is invalid when it is low level and the input / output instruction is valid when it is high level.

As shown in this figure, first, at time T1, the HOLD REQ signal of the DMA controller becomes valid, then the HOLD ACK signal of the DMA controller becomes valid, and burst transfer is started ((c), ( d),
(B)). Here, at time T2, the main processor executes an I / O read to the DMA controller. At this time, a chip select signal is output from the I / O decoder 31, which is supplied to the AND gate 42 and the AND gate 45.

During this time, the main processor 3 accesses the DMA controller 11. Then, the I / O read is executed at time T2, and in this I / O read cycle, it is confirmed whether the I / O instruction executed immediately before is valid or invalid. In this read cycle, the timing signal input from the system bus 1 to the AND gate 42 shown in FIG. 8 becomes valid, the chip select signal output from the I / O decoder 31 is input to the result display circuit 32, and from there. The processing result of the I / O instruction is the bidirectional buffer 3
It is output to 5. The result display circuit 32 is periodically cleared by the flip-flop 51, and the I / O
If the instruction is not processed successfully, the flip-flop 53
Is also low level, the output of the result display circuit 32 is low level. This is input to the bidirectional buffer 35,
It is read by the main processor 3 via the system bus 1.

As a result, the main processor 3 receives the last I
Recognize that the / O instruction was invalid. In this case, the chip select signal output from the I / O decoder 31 becomes high level and is input to the AND gate 45.
The output signal of the flip-flop 54 is at a low level due to the masking effect of the AND gate 43, and DM
No chip select signal is input to the A controller 11 (FIG. 9 (g)).

The output of the result display circuit 32 input to the bidirectional buffer 35 is 16 in the system bus 1 in advance.
In the bit data bus, it is decided which position to set. Therefore, the main processor 3 selects and reads the content and determines whether the input / output instruction is valid or invalid.

Thereafter, similar processing is repeated at times T3 and T4, during which the DMA controller 11 executes burst transfer to the main memory 2. At the time T4, when the burst transfer is completed, if the I / O instruction is executed in the next write cycle, the I immediately after the time T5 is reached.
Flip-flop 54 shown in FIG. 8 in the / O read cycle.
Output becomes high level, and the chip select signal is input to the DMA controller 11 through the AND gate 45 (FIG. 9 (g)). At the same time, the output signal of the result display circuit 32 also becomes high level, and the main processor 3 recognizes this. Then, the main processor 3 executes the I / O write instruction at time T6, and the DMA controller 11
To process input / output instructions.

After that, at time T7, the main processor 3 executes an operation for reading the processing result of the input / output instruction. In this case, the chip select signal is input from the I / O decoder 31 to the result display circuit 32 via the OR gate 41. As a result, the result display circuit 32 outputs a 1-bit signal indicating the result of the input / output instruction to the bidirectional buffer 35. The reading of the output of the result display circuit 32 at time T7 is performed by a method different from the processing performed between times T2 and T5.

FIG. 10 shows a fifth example of the above processing.
3 shows an I / O read operation flowchart of the invention. In the fifth invention, the success or failure of the input / output instruction is recognized with the smallest number of dynamic steps by using the device as shown in FIG. That is, as shown in step S1 of FIG. 10, the main processor 3 executes I / O read to the DMA controller 11. Here, the main processor 3 reads the output of the result display circuit 32 from the bidirectional buffer 35. Then, in step S2, the result display bit in this output is recognized. In this way, the DMA controller 11
It is possible to immediately recognize whether or not the burst transfer is being executed by only the I / O read for, and the processing efficiency and speed can be improved.

FIG. 11 shows an I / O write operation flowchart of the fifth invention. It is most efficient to recognize the result display bit by the processing shown in FIG. However,
It can be recognized also by the method shown in this figure. First, in step S1, measures are taken to inhibit interruption of the main processor itself.

Next, in step S2, I / O write to the DMA controller is executed. When the I / O write is executed, as described above, the chip select signal is input from the I / O decoder 31 shown in FIG. 8 to the result display circuit 32 via the OR gate 41. The result of the display bit is read by such a method, and step S4
In, the result display bit is determined.

When the result display bit has the content of the input / output instruction failure, the interrupt disabled state is temporarily released in step S5, and the process returns to step S1 again at an appropriate interval. In this way, the interrupt disabled state causes another interrupt to occur immediately after executing the input / output instruction to the DMA controller, and rewrites the contents of the result display circuit 32 of the DMA bus master module 30 during the processing. This is to prevent this. If it is determined in step S4 that the execution result of the input / output instruction is valid, the process proceeds to step S6 to cancel the interrupt prohibition measures so far and then proceed to another process.

FIG. 12 shows a diagram for explaining the DMA data format of the sixth invention. As described above, the main processor 3 can accept the result display bit indicating whether the input / output instruction is valid or invalid in both the I / O read operation and the I / O write operation. Here, in the present invention, as shown in FIGS. 12A and 12B, at the time of I / O write and I / O write
DMA controller 11 in any case during O read
It is stored in the bidirectional buffer 35 in combination with the DMA data and the like output from the main processor 3 and read.

That is, when the 16-bit data bus is provided, for example, the DMA read data is set to 8 bits, and the result display bit is included for 1 bit. Since only the result display bit is recognized at the time of I / O write, other parts are unused undefined data. As a result, it becomes possible for the main processor 3 to recognize the result of the validity of the input / output instruction without occupying the system bus 1 in the DMA read cycle. The configuration of the result display circuit shown in FIG. 8 and the circuit for storing and outputting these result display bits and the like may be replaced with various circuits having the same function.

[0061]

According to the DMA bus master module device and control method of the present invention described above, the following effects can be expected. According to the first aspect of the present invention, the release of the internal bus by the DMA controller is detected, and before it acquires the bus right of the internal bus again, mask processing is performed so as to cut off the supply path of the bus right grant signal. Since the presence or absence of processing completion is notified to other modules such as the main processor, it becomes possible to use it with priority immediately after releasing the internal bus, and to prevent overrun or underrun of other modules. It can be prevented. This is particularly effective for a DMA controller configured such that the burst transfer is not terminated even when the HOLD ACK signal is forcibly turned off during execution of the burst transfer.

According to the second aspect of the invention, the mask circuit of the DMA controller is activated after interrupting another module's interrupt with respect to its own module. It is possible to prevent a failure such as an interruption caused by a module and making the DMA controller wait for a long time. Also,
According to the third aspect of the present invention, after the interrupt is temporarily prohibited by the second aspect of the invention, if the DMA controller does not release the internal bus, the interrupt measure is released, so that an interrupt from another module to another module is interrupted. It is possible to prevent adverse effects such as waiting for a long time.

In the fourth invention, when the input / output instruction is issued, the input / output instruction is invalidated during the burst transfer, and after the burst transfer is completed, the input / output instruction is validated and the result is displayed. As compared with the case where the activation of the mask circuit is recognized, information such as burst transfer completion can be obtained with a smaller number of dynamic steps.

According to the fifth aspect of the invention, the result display circuit is read in the read cycle after the input / output instruction is issued to determine whether the input / output instruction is valid or invalid. Therefore, the result can be recognized in a very short dynamic step. . Furthermore, according to the sixth aspect of the invention, the result of the input / output instruction is combined with the DMA read data and output, so that information for recognizing the validity of the input / output instruction is obtained without occupying the system bus. be able to.

[Brief description of drawings]

FIG. 1 is a block diagram of a DMA bus master module device of the first invention.

FIG. 2 is a block diagram of a main part of a general information processing apparatus.

FIG. 3 is a diagram illustrating the relationship between burst transfer and system bus right.

FIG. 4 is an operation flowchart of the second invention.

FIG. 5 is a timing chart of the second invention.

FIG. 6 is an operation flowchart of the third invention.

FIG. 7 is a timing chart of the third invention.

FIG. 8 is a block diagram of a device of the fourth invention.

FIG. 9 is an operation timing chart of the device of the fourth invention.

FIG. 10 is an I / O read operation flowchart of the fifth invention.

FIG. 11 is an I / O write operation flowchart of the fifth invention.

FIG. 12 is an explanatory diagram of a DMA data format of the sixth invention.

[Explanation of symbols]

 1 System Bus 2 Main Memory 3 Main Processor 10 DMA Bus Master Module 11 DMA Controller 15 Internal Bus 20 Mask Circuit

Claims (6)

[Claims] 1. A direct memory access controller that releases the bus right at a predetermined timing while occupying the system bus and performing burst transfer, and enables another module to occupy the system bus. Before the direct memory access controller acquires the bus right of the internal bus again by detecting the release of the internal bus by the direct memory access controller, the supply path of the bus right grant signal of the internal bus A DMA bus master module, comprising: a mask circuit for performing a mask process to cut off the signal, and a sense circuit for holding a status signal for notifying the other module of the completion of the mask process by the mask circuit. apparatus. 2. A direct memory access controller that releases the bus right at a predetermined timing while occupying the system bus and executing burst transfer, and enables another module to occupy the system bus. Before the direct memory access controller acquires the bus right of the internal bus again by detecting the release of the internal bus by the direct memory access controller, the supply path of the bus right grant signal of the internal bus A mask circuit for performing mask processing so as to cut off, and a sense circuit for holding a status signal for notifying the other module of the end of the mask processing by the mask circuit, wherein the other module is its own module in advance. After clearing the interrupt of another module to the And the activation of the mask circuit requires timing, reads the sense circuit recognizes the completion notification of the mask processing, the direct
A method for controlling a DMA bus master module, comprising issuing an input / output instruction to a memory access controller. 3. When the other module reads the sense circuit and recognizes that the mask processing is not completed yet, the other module cancels the interrupt exclusion measure of the other module for its own module. 3. The method of controlling a DMA bus master module according to claim 2, wherein: 4. A direct memory access controller that releases the bus right at a predetermined timing while occupying the system bus and performing burst transfer, and enables another module to occupy the system bus. At Taimyig where the bus right of the system bus was released,
When an I / O command is issued from another module, the I / O command is invalidated during execution of the burst transfer,
A DMA bus master module device comprising a result display circuit for validating the input / output command after the burst transfer and displaying the result. 5. A direct memory access controller that releases the bus right at a predetermined timing while occupying the system bus and performing burst transfer, and allows another module to occupy the system bus. At Taimyig where the bus right of the system bus was released,
When an I / O command is issued from another module, the I / O command is invalidated during execution of the burst transfer,
After the burst transfer is completed, the input / output instruction is validated, and a result display circuit for displaying the result is provided, and the other module is configured to perform the read / write operation after issuing the input / output instruction to the direct memory access controller. A method for controlling a DMA bus master module, comprising reading a result display circuit. 6. A direct memory access controller which releases the bus right at a predetermined timing while occupying the system bus and performing burst transfer, and enables another module to occupy the system bus. At Taimyig where the bus right of the system bus was released,
When an I / O command is issued from another module, the I / O command is invalidated during execution of the burst transfer,
After the burst transfer is completed, a result display circuit is provided for validating the input / output command and displaying the result, and the other module is configured to display the result display circuit in the DMA data output from the direct memory access controller. A method for controlling a DMA bus master module, which is characterized in that the output including the above is read.