JPH0620039B2 - Manufacturing method of semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device having a hetero interface.

A heterogeneous compound semiconductor layer is formed by a metal organic chemical vapor deposition method, so-called
The technology of forming a hetero interface by MOCVD is
Although it is being applied to the manufacturing technology of various semiconductor devices, in this case, the hetero interface is applied only to the plane direction of the compound semiconductor layer, that is, to the direction along the deposition surface. No attention has been paid to the formation of a hetero interface in the direction intersecting with.

The present inventors have found that a first compound semiconductor layer, such as an AlGaAs layer, and a second compound semiconductor layer, such as GaAs, which are different from each other.
In the case of epitaxially growing the layer with MOCVD, the growth temperature, that is, the substrate temperature is selected to be a predetermined temperature in the temperature range of 650 to 850 ° C. In addition, a large number of islands of AlGaAs atomic layers can be formed in an array by controlling their spread width. For example, a GaAs layer of the second compound semiconductor layer is epitaxially grown by burying these islands on these islands. I found that Based on this, in the present invention, a large number of islands having a required width are arrayed by controlling the temperature at 650 to 850 ° C. described above, and they are formed on the side surfaces of these islands, that is, in the plane direction of the deposition surface of the semiconductor layer. The array of fine hetero interfaces is positively and appropriately formed in the direction.

For example, as shown in FIG. 1, the substrate (1), for example, G
On the aAs substrate, a first compound semiconductor layer such as G
Epitaxially grow aAs (2) by MOCVD, and then switch the source gas to supply the second compound semiconductor layer (3) with M
When epitaxially grown by OCVD, both semiconductor layers
A low atomic layer island (4) is generated at the interface of (2) and (3) .This island (4) is the epitaxial growth temperature of the hetero interface of both layers (2) and (3), that is, the substrate temperature during MOCVD. It is possible to select the width W of the AlAs formed on the side surface of the island (4) by selecting the width W of the island (4) and hence the pitch by this temperature control.
/ GaAs hetero interface, that is, the first semiconductor layer (2),
A large number of hetero interfaces intersecting with the deposition surface direction of the second semiconductor layer (3) are formed.

FIG. 2 shows the result of measurement of the relationship between the growth temperature and the width W of the island (4).

This measurement is performed using GaAs substrate as shown in Fig. 3.
Six AlGaAs layers as the first compound semiconductor layer (2) and GaA as the second compound semiconductor layer (3) on the (1)
Five s layers were alternately formed by MOCVD, and a sample was formed in which independent quantum wells were formed in the second compound semiconductor layer (3), and the full width at half maximum of fault luminescence was measured for the sample. .

Next, a specific example of manufacturing a semiconductor device by the manufacturing method of the present invention will be described with reference to FIG. This example is for obtaining a modulation transistor of electron transfer velocity, so-called VMT,
In this example, the GaAs buffer layer (12) is provided on the semi-insulating GaAs substrate (11) with one conductivity type, for example, n-type A.
lGaAs first compound semiconductor layer (13) and undoped GaAs
The second compound semiconductor layer (14) and the third compound semiconductor layer (15) of AlGaAs of the first conductivity type, for example, n-type, are sequentially formed by MOCV.
Epitaxial growth by D. And the semiconductor layer (1
5) and (14) are maintained at a required distance with a required interval, and n-type impurities are selectively ion-implanted to form source and drain regions (16) and (17), respectively. ) And (17), a gate electrode (18) is deposited on the third semiconductor layer (15), and ohmic ohmic source and drain electrodes (19) and (15) are formed on the regions (16) and (17). Form (20).

In this case, the first to third compound semiconductor layers (13)
The epitaxial growth temperature of (15) is set as follows.
That is, the growth temperature in the vicinity of the hetero-interface H ₁ between the first and second compound semiconductor layers (13) and (14) is set to, for example, 650 to 750 ° C., and the second and third compound semiconductor layers (14) and ( By setting the growth temperature in the vicinity of the hetero interface H ₂ between 15) to, for example, 750 to 850 ° C., islands (4) having different widths W ₁ and W ₂ are arrayed as shown in FIGS. 5A and 5B. To do so.

In such a structure, the first heterojunction H ₁ of the second compound semiconductor layer (13) between the source and drain regions (16) and (17) is controlled by controlling the voltage applied to the gate electrode (18). The main channel can be selectively formed either on the side or on the second heterojunction H ₂ .
Particularly, in the configuration of the present invention, as described above, both interfaces H ₁ and H
₂ , the island widths W ₁ and W ₂ are formed so as to be different from each other, and the arrangement pitches of the heterojunctions in both directions are different. Therefore, for example, any one of the junctions H ₁ or Since H ₂ has a different island width in the plane direction, the scattering type of electrons is different between H ₁ and H ₂ , and therefore the electron mobility in the plane direction is different in each Tehro junction H ₁ and H ₂ . ,
By controlling the gate voltage, a speed-modulated transistor, that is, a VMT structure is formed.

Although the present invention is applied to the case of obtaining the VMT in the above-mentioned example, it can be applied to various semiconductor devices which set a required electron mobility in the lateral direction.

Further, according to the manufacturing method of the present invention, not only a superlattice structure formed by stacking two-dimensional heterojunctions, but also a three-dimensional superlattice in a zero-dimensional k-space or an actual space due to a temporal change in epitaxial growth temperature. It is possible to realize a structure, that is, a structure in which two kinds of semiconductors are present in a bubble shape among each other.

As described above, according to the present invention, the array structure of the hetero interface intersecting with the plane direction of the semiconductor layer epitaxially grown by the control of the epitaxial growth temperature in MOCVD is formed with a controlled pitch. Various semiconductor devices can be manufactured without increasing the number or using a special epitaxial growth device, and the profit is large in practical use.

[Brief description of drawings]

FIG. 1 is an enlarged cross-sectional view of an essential part for explaining the manufacturing method of the present invention,
FIG. 2 is a measurement curve diagram of the relationship between the epitaxial growth temperature and the island width, FIG. 3 is an explanatory diagram of the measurement sample, and FIG.
The figure is an enlarged cross-sectional view of an example of a semiconductor device obtained by the manufacturing method of the present invention, and FIGS. 5A and 5B are schematic linear enlarged cross-sectional views of the heterojunction portion thereof. (1) and (11) are substitutes, (2), (3), (13) and (1
4) and (15) are compound semiconductor layers, and (4) is an island.

Claims (1)

[Claims] 1. A step of epitaxially growing at least a first compound semiconductor layer and a second compound semiconductor layer, which are different from each other, by a metal organic chemical vapor deposition method to form a hetero interface, and the above-mentioned epitaxial growth temperature. From 650 to 850
On the surface of the first compound semiconductor layer on which the second compound semiconductor layer is deposited, the width of the island spreading in the surface direction is controlled by selecting in the temperature range of ° C. A method for manufacturing a semiconductor device, characterized in that the fine hetero interfaces of (1) are arrayed and formed at required intervals.